0001 # SPDX-License-Identifier: GPL-2.0-only
0002 #
0003 # FPGA framework configuration
0004 #
0005
0006 menuconfig FPGA
0007 tristate "FPGA Configuration Framework"
0008 help
0009 Say Y here if you want support for configuring FPGAs from the
0010 kernel. The FPGA framework adds an FPGA manager class and FPGA
0011 manager drivers.
0012
0013 if FPGA
0014
0015 config FPGA_MGR_SOCFPGA
0016 tristate "Altera SOCFPGA FPGA Manager"
0017 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
0018 help
0019 FPGA manager driver support for Altera SOCFPGA.
0020
0021 config FPGA_MGR_SOCFPGA_A10
0022 tristate "Altera SoCFPGA Arria10"
0023 depends on ARCH_INTEL_SOCFPGA || COMPILE_TEST
0024 select REGMAP_MMIO
0025 help
0026 FPGA manager driver support for Altera Arria10 SoCFPGA.
0027
0028 config ALTERA_PR_IP_CORE
0029 tristate "Altera Partial Reconfiguration IP Core"
0030 help
0031 Core driver support for Altera Partial Reconfiguration IP component
0032
0033 config ALTERA_PR_IP_CORE_PLAT
0034 tristate "Platform support of Altera Partial Reconfiguration IP Core"
0035 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
0036 help
0037 Platform driver support for Altera Partial Reconfiguration IP
0038 component
0039
0040 config FPGA_MGR_ALTERA_PS_SPI
0041 tristate "Altera FPGA Passive Serial over SPI"
0042 depends on SPI
0043 select BITREVERSE
0044 help
0045 FPGA manager driver support for Altera Arria/Cyclone/Stratix
0046 using the passive serial interface over SPI.
0047
0048 config FPGA_MGR_ALTERA_CVP
0049 tristate "Altera CvP FPGA Manager"
0050 depends on PCI
0051 help
0052 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
0053 Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
0054
0055 config FPGA_MGR_ZYNQ_FPGA
0056 tristate "Xilinx Zynq FPGA"
0057 depends on ARCH_ZYNQ || COMPILE_TEST
0058 help
0059 FPGA manager driver support for Xilinx Zynq FPGAs.
0060
0061 config FPGA_MGR_STRATIX10_SOC
0062 tristate "Intel Stratix10 SoC FPGA Manager"
0063 depends on (ARCH_INTEL_SOCFPGA && INTEL_STRATIX10_SERVICE)
0064 help
0065 FPGA manager driver support for the Intel Stratix10 SoC.
0066
0067 config FPGA_MGR_XILINX_SPI
0068 tristate "Xilinx Configuration over Slave Serial (SPI)"
0069 depends on SPI
0070 help
0071 FPGA manager driver support for Xilinx FPGA configuration
0072 over slave serial interface.
0073
0074 config FPGA_MGR_ICE40_SPI
0075 tristate "Lattice iCE40 SPI"
0076 depends on OF && SPI
0077 help
0078 FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
0079
0080 config FPGA_MGR_MACHXO2_SPI
0081 tristate "Lattice MachXO2 SPI"
0082 depends on SPI
0083 help
0084 FPGA manager driver support for Lattice MachXO2 configuration
0085 over slave SPI interface.
0086
0087 config FPGA_MGR_TS73XX
0088 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
0089 depends on ARCH_EP93XX && MACH_TS72XX
0090 help
0091 FPGA manager driver support for the Altera Cyclone II FPGA
0092 present on the TS-73xx SBC boards.
0093
0094 config FPGA_BRIDGE
0095 tristate "FPGA Bridge Framework"
0096 help
0097 Say Y here if you want to support bridges connected between host
0098 processors and FPGAs or between FPGAs.
0099
0100 config SOCFPGA_FPGA_BRIDGE
0101 tristate "Altera SoCFPGA FPGA Bridges"
0102 depends on ARCH_INTEL_SOCFPGA && FPGA_BRIDGE
0103 help
0104 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
0105 devices.
0106
0107 config ALTERA_FREEZE_BRIDGE
0108 tristate "Altera FPGA Freeze Bridge"
0109 depends on FPGA_BRIDGE && HAS_IOMEM
0110 help
0111 Say Y to enable drivers for Altera FPGA Freeze bridges. A
0112 freeze bridge is a bridge that exists in the FPGA fabric to
0113 isolate one region of the FPGA from the busses while that
0114 region is being reprogrammed.
0115
0116 config XILINX_PR_DECOUPLER
0117 tristate "Xilinx LogiCORE PR Decoupler"
0118 depends on FPGA_BRIDGE
0119 depends on HAS_IOMEM
0120 help
0121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
0122 or Xilinx Dynamic Function eXchange AIX Shutdown Manager.
0123 The PR Decoupler exists in the FPGA fabric to isolate one
0124 region of the FPGA from the busses while that region is
0125 being reprogrammed during partial reconfig.
0126 The Dynamic Function eXchange AXI shutdown manager prevents
0127 AXI traffic from passing through the bridge. The controller
0128 safely handles AXI4MM and AXI4-Lite interfaces on a
0129 Reconfigurable Partition when it is undergoing dynamic
0130 reconfiguration, preventing the system deadlock that can
0131 occur if AXI transactions are interrupted by DFX.
0132
0133 config FPGA_REGION
0134 tristate "FPGA Region"
0135 depends on FPGA_BRIDGE
0136 help
0137 FPGA Region common code. An FPGA Region controls an FPGA Manager
0138 and the FPGA Bridges associated with either a reconfigurable
0139 region of an FPGA or a whole FPGA.
0140
0141 config OF_FPGA_REGION
0142 tristate "FPGA Region Device Tree Overlay Support"
0143 depends on OF && FPGA_REGION
0144 help
0145 Support for loading FPGA images by applying a Device Tree
0146 overlay.
0147
0148 config FPGA_DFL
0149 tristate "FPGA Device Feature List (DFL) support"
0150 select FPGA_BRIDGE
0151 select FPGA_REGION
0152 depends on HAS_IOMEM
0153 help
0154 Device Feature List (DFL) defines a feature list structure that
0155 creates a linked list of feature headers within the MMIO space
0156 to provide an extensible way of adding features for FPGA.
0157 Driver can walk through the feature headers to enumerate feature
0158 devices (e.g. FPGA Management Engine, Port and Accelerator
0159 Function Unit) and their private features for target FPGA devices.
0160
0161 Select this option to enable common support for Field-Programmable
0162 Gate Array (FPGA) solutions which implement Device Feature List.
0163 It provides enumeration APIs and feature device infrastructure.
0164
0165 config FPGA_DFL_FME
0166 tristate "FPGA DFL FME Driver"
0167 depends on FPGA_DFL && HWMON && PERF_EVENTS
0168 help
0169 The FPGA Management Engine (FME) is a feature device implemented
0170 under Device Feature List (DFL) framework. Select this option to
0171 enable the platform device driver for FME which implements all
0172 FPGA platform level management features. There shall be one FME
0173 per DFL based FPGA device.
0174
0175 config FPGA_DFL_FME_MGR
0176 tristate "FPGA DFL FME Manager Driver"
0177 depends on FPGA_DFL_FME && HAS_IOMEM
0178 help
0179 Say Y to enable FPGA Manager driver for FPGA Management Engine.
0180
0181 config FPGA_DFL_FME_BRIDGE
0182 tristate "FPGA DFL FME Bridge Driver"
0183 depends on FPGA_DFL_FME && HAS_IOMEM
0184 help
0185 Say Y to enable FPGA Bridge driver for FPGA Management Engine.
0186
0187 config FPGA_DFL_FME_REGION
0188 tristate "FPGA DFL FME Region Driver"
0189 depends on FPGA_DFL_FME && HAS_IOMEM
0190 help
0191 Say Y to enable FPGA Region driver for FPGA Management Engine.
0192
0193 config FPGA_DFL_AFU
0194 tristate "FPGA DFL AFU Driver"
0195 depends on FPGA_DFL
0196 help
0197 This is the driver for FPGA Accelerated Function Unit (AFU) which
0198 implements AFU and Port management features. A User AFU connects
0199 to the FPGA infrastructure via a Port. There may be more than one
0200 Port/AFU per DFL based FPGA device.
0201
0202 config FPGA_DFL_NIOS_INTEL_PAC_N3000
0203 tristate "FPGA DFL NIOS Driver for Intel PAC N3000"
0204 depends on FPGA_DFL
0205 select REGMAP
0206 help
0207 This is the driver for the N3000 Nios private feature on Intel
0208 PAC (Programmable Acceleration Card) N3000. It communicates
0209 with the embedded Nios processor to configure the retimers on
0210 the card. It also instantiates the SPI master (spi-altera) for
0211 the card's BMC (Board Management Controller).
0212
0213 config FPGA_DFL_PCI
0214 tristate "FPGA DFL PCIe Device Driver"
0215 depends on PCI && FPGA_DFL
0216 help
0217 Select this option to enable PCIe driver for PCIe-based
0218 Field-Programmable Gate Array (FPGA) solutions which implement
0219 the Device Feature List (DFL). This driver provides interfaces
0220 for userspace applications to configure, enumerate, open and access
0221 FPGA accelerators on the FPGA DFL devices, enables system level
0222 management functions such as FPGA partial reconfiguration, power
0223 management and virtualization with DFL framework and DFL feature
0224 device drivers.
0225
0226 To compile this as a module, choose M here.
0227
0228 config FPGA_MGR_ZYNQMP_FPGA
0229 tristate "Xilinx ZynqMP FPGA"
0230 depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
0231 help
0232 FPGA manager driver support for Xilinx ZynqMP FPGAs.
0233 This driver uses the processor configuration port(PCAP)
0234 to configure the programmable logic(PL) through PS
0235 on ZynqMP SoC.
0236
0237 config FPGA_MGR_VERSAL_FPGA
0238 tristate "Xilinx Versal FPGA"
0239 depends on ARCH_ZYNQMP || COMPILE_TEST
0240 help
0241 Select this option to enable FPGA manager driver support for
0242 Xilinx Versal SoC. This driver uses the firmware interface to
0243 configure the programmable logic(PL).
0244
0245 To compile this as a module, choose M here.
0246
0247 config FPGA_M10_BMC_SEC_UPDATE
0248 tristate "Intel MAX10 BMC Secure Update driver"
0249 depends on MFD_INTEL_M10_BMC && FW_UPLOAD
0250 help
0251 Secure update support for the Intel MAX10 board management
0252 controller.
0253
0254 This is a subdriver of the Intel MAX10 board management controller
0255 (BMC) and provides support for secure updates for the BMC image,
0256 the FPGA image, the Root Entry Hashes, etc.
0257
0258 config FPGA_MGR_MICROCHIP_SPI
0259 tristate "Microchip Polarfire SPI FPGA manager"
0260 depends on SPI
0261 help
0262 FPGA manager driver support for Microchip Polarfire FPGAs
0263 programming over slave SPI interface with .dat formatted
0264 bitstream image.
0265
0266 endif # FPGA
