drivers/firmware/qcom_scm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
0003  */
0004 #ifndef __QCOM_SCM_INT_H
0005 #define __QCOM_SCM_INT_H
0006
0007 enum qcom_scm_convention {
0008     SMC_CONVENTION_UNKNOWN,
0009     SMC_CONVENTION_LEGACY,
0010     SMC_CONVENTION_ARM_32,
0011     SMC_CONVENTION_ARM_64,
0012 };
0013
0014 extern enum qcom_scm_convention qcom_scm_convention;
0015
0016 #define MAX_QCOM_SCM_ARGS 10
0017 #define MAX_QCOM_SCM_RETS 3
0018
0019 enum qcom_scm_arg_types {
0020     QCOM_SCM_VAL,
0021     QCOM_SCM_RO,
0022     QCOM_SCM_RW,
0023     QCOM_SCM_BUFVAL,
0024 };
0025
0026 #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
0027                (((a) & 0x3) << 4) | \
0028                (((b) & 0x3) << 6) | \
0029                (((c) & 0x3) << 8) | \
0030                (((d) & 0x3) << 10) | \
0031                (((e) & 0x3) << 12) | \
0032                (((f) & 0x3) << 14) | \
0033                (((g) & 0x3) << 16) | \
0034                (((h) & 0x3) << 18) | \
0035                (((i) & 0x3) << 20) | \
0036                (((j) & 0x3) << 22) | \
0037                ((num) & 0xf))
0038
0039 #define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
0040
0041
0042 /**
0043  * struct qcom_scm_desc
0044  * @arginfo:    Metadata describing the arguments in args[]
0045  * @args:   The array of arguments for the secure syscall
0046  */
0047 struct qcom_scm_desc {
0048     u32 svc;
0049     u32 cmd;
0050     u32 arginfo;
0051     u64 args[MAX_QCOM_SCM_ARGS];
0052     u32 owner;
0053 };
0054
0055 /**
0056  * struct qcom_scm_res
0057  * @result: The values returned by the secure syscall
0058  */
0059 struct qcom_scm_res {
0060     u64 result[MAX_QCOM_SCM_RETS];
0061 };
0062
0063 #define SCM_SMC_FNID(s, c)  ((((s) & 0xFF) << 8) | ((c) & 0xFF))
0064 extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
0065               enum qcom_scm_convention qcom_convention,
0066               struct qcom_scm_res *res, bool atomic);
0067 #define scm_smc_call(dev, desc, res, atomic) \
0068     __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
0069
0070 #define SCM_LEGACY_FNID(s, c)   (((s) << 10) | ((c) & 0x3ff))
0071 extern int scm_legacy_call_atomic(struct device *dev,
0072                   const struct qcom_scm_desc *desc,
0073                   struct qcom_scm_res *res);
0074 extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
0075                struct qcom_scm_res *res);
0076
0077 #define QCOM_SCM_SVC_BOOT       0x01
0078 #define QCOM_SCM_BOOT_SET_ADDR      0x01
0079 #define QCOM_SCM_BOOT_TERMINATE_PC  0x02
0080 #define QCOM_SCM_BOOT_SET_DLOAD_MODE    0x10
0081 #define QCOM_SCM_BOOT_SET_ADDR_MC   0x11
0082 #define QCOM_SCM_BOOT_SET_REMOTE_STATE  0x0a
0083 #define QCOM_SCM_FLUSH_FLAG_MASK    0x3
0084 #define QCOM_SCM_BOOT_MAX_CPUS      4
0085 #define QCOM_SCM_BOOT_MC_FLAG_AARCH64   BIT(0)
0086 #define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT  BIT(1)
0087 #define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT  BIT(2)
0088
0089 #define QCOM_SCM_SVC_PIL        0x02
0090 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
0091 #define QCOM_SCM_PIL_PAS_MEM_SETUP  0x02
0092 #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
0093 #define QCOM_SCM_PIL_PAS_SHUTDOWN   0x06
0094 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED   0x07
0095 #define QCOM_SCM_PIL_PAS_MSS_RESET  0x0a
0096
0097 #define QCOM_SCM_SVC_IO         0x05
0098 #define QCOM_SCM_IO_READ        0x01
0099 #define QCOM_SCM_IO_WRITE       0x02
0100
0101 #define QCOM_SCM_SVC_INFO       0x06
0102 #define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
0103
0104 #define QCOM_SCM_SVC_MP             0x0c
0105 #define QCOM_SCM_MP_RESTORE_SEC_CFG     0x02
0106 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE  0x03
0107 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT  0x04
0108 #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE  0x05
0109 #define QCOM_SCM_MP_VIDEO_VAR           0x08
0110 #define QCOM_SCM_MP_ASSIGN          0x16
0111
0112 #define QCOM_SCM_SVC_OCMEM      0x0f
0113 #define QCOM_SCM_OCMEM_LOCK_CMD     0x01
0114 #define QCOM_SCM_OCMEM_UNLOCK_CMD   0x02
0115
0116 #define QCOM_SCM_SVC_ES         0x10    /* Enterprise Security */
0117 #define QCOM_SCM_ES_INVALIDATE_ICE_KEY  0x03
0118 #define QCOM_SCM_ES_CONFIG_SET_ICE_KEY  0x04
0119
0120 #define QCOM_SCM_SVC_HDCP       0x11
0121 #define QCOM_SCM_HDCP_INVOKE        0x01
0122
0123 #define QCOM_SCM_SVC_LMH            0x13
0124 #define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE   0x01
0125 #define QCOM_SCM_LMH_LIMIT_DCVSH        0x10
0126
0127 #define QCOM_SCM_SVC_SMMU_PROGRAM       0x15
0128 #define QCOM_SCM_SMMU_PT_FORMAT         0x01
0129 #define QCOM_SCM_SMMU_CONFIG_ERRATA1        0x03
0130 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
0131
0132 extern void __qcom_scm_init(void);
0133
0134 /* common error codes */
0135 #define QCOM_SCM_V2_EBUSY   -12
0136 #define QCOM_SCM_ENOMEM     -5
0137 #define QCOM_SCM_EOPNOTSUPP -4
0138 #define QCOM_SCM_EINVAL_ADDR    -3
0139 #define QCOM_SCM_EINVAL_ARG -2
0140 #define QCOM_SCM_ERROR      -1
0141 #define QCOM_SCM_INTERRUPTED    1
0142
0143 static inline int qcom_scm_remap_error(int err)
0144 {
0145     switch (err) {
0146     case QCOM_SCM_ERROR:
0147         return -EIO;
0148     case QCOM_SCM_EINVAL_ADDR:
0149     case QCOM_SCM_EINVAL_ARG:
0150         return -EINVAL;
0151     case QCOM_SCM_EOPNOTSUPP:
0152         return -EOPNOTSUPP;
0153     case QCOM_SCM_ENOMEM:
0154         return -ENOMEM;
0155     case QCOM_SCM_V2_EBUSY:
0156         return -EBUSY;
0157     }
0158     return -EINVAL;
0159 }
0160
0161 #endif