0001
0002 #ifndef _FIREWIRE_OHCI_H
0003 #define _FIREWIRE_OHCI_H
0004
0005
0006
0007 #define OHCI1394_Version 0x000
0008 #define OHCI1394_GUID_ROM 0x004
0009 #define OHCI1394_ATRetries 0x008
0010 #define OHCI1394_CSRData 0x00C
0011 #define OHCI1394_CSRCompareData 0x010
0012 #define OHCI1394_CSRControl 0x014
0013 #define OHCI1394_ConfigROMhdr 0x018
0014 #define OHCI1394_BusID 0x01C
0015 #define OHCI1394_BusOptions 0x020
0016 #define OHCI1394_GUIDHi 0x024
0017 #define OHCI1394_GUIDLo 0x028
0018 #define OHCI1394_ConfigROMmap 0x034
0019 #define OHCI1394_PostedWriteAddressLo 0x038
0020 #define OHCI1394_PostedWriteAddressHi 0x03C
0021 #define OHCI1394_VendorID 0x040
0022 #define OHCI1394_HCControlSet 0x050
0023 #define OHCI1394_HCControlClear 0x054
0024 #define OHCI1394_HCControl_BIBimageValid 0x80000000
0025 #define OHCI1394_HCControl_noByteSwapData 0x40000000
0026 #define OHCI1394_HCControl_programPhyEnable 0x00800000
0027 #define OHCI1394_HCControl_aPhyEnhanceEnable 0x00400000
0028 #define OHCI1394_HCControl_LPS 0x00080000
0029 #define OHCI1394_HCControl_postedWriteEnable 0x00040000
0030 #define OHCI1394_HCControl_linkEnable 0x00020000
0031 #define OHCI1394_HCControl_softReset 0x00010000
0032 #define OHCI1394_SelfIDBuffer 0x064
0033 #define OHCI1394_SelfIDCount 0x068
0034 #define OHCI1394_SelfIDCount_selfIDError 0x80000000
0035 #define OHCI1394_IRMultiChanMaskHiSet 0x070
0036 #define OHCI1394_IRMultiChanMaskHiClear 0x074
0037 #define OHCI1394_IRMultiChanMaskLoSet 0x078
0038 #define OHCI1394_IRMultiChanMaskLoClear 0x07C
0039 #define OHCI1394_IntEventSet 0x080
0040 #define OHCI1394_IntEventClear 0x084
0041 #define OHCI1394_IntMaskSet 0x088
0042 #define OHCI1394_IntMaskClear 0x08C
0043 #define OHCI1394_IsoXmitIntEventSet 0x090
0044 #define OHCI1394_IsoXmitIntEventClear 0x094
0045 #define OHCI1394_IsoXmitIntMaskSet 0x098
0046 #define OHCI1394_IsoXmitIntMaskClear 0x09C
0047 #define OHCI1394_IsoRecvIntEventSet 0x0A0
0048 #define OHCI1394_IsoRecvIntEventClear 0x0A4
0049 #define OHCI1394_IsoRecvIntMaskSet 0x0A8
0050 #define OHCI1394_IsoRecvIntMaskClear 0x0AC
0051 #define OHCI1394_InitialBandwidthAvailable 0x0B0
0052 #define OHCI1394_InitialChannelsAvailableHi 0x0B4
0053 #define OHCI1394_InitialChannelsAvailableLo 0x0B8
0054 #define OHCI1394_FairnessControl 0x0DC
0055 #define OHCI1394_LinkControlSet 0x0E0
0056 #define OHCI1394_LinkControlClear 0x0E4
0057 #define OHCI1394_LinkControl_rcvSelfID (1 << 9)
0058 #define OHCI1394_LinkControl_rcvPhyPkt (1 << 10)
0059 #define OHCI1394_LinkControl_cycleTimerEnable (1 << 20)
0060 #define OHCI1394_LinkControl_cycleMaster (1 << 21)
0061 #define OHCI1394_LinkControl_cycleSource (1 << 22)
0062 #define OHCI1394_NodeID 0x0E8
0063 #define OHCI1394_NodeID_idValid 0x80000000
0064 #define OHCI1394_NodeID_root 0x40000000
0065 #define OHCI1394_NodeID_nodeNumber 0x0000003f
0066 #define OHCI1394_NodeID_busNumber 0x0000ffc0
0067 #define OHCI1394_PhyControl 0x0EC
0068 #define OHCI1394_PhyControl_Read(addr) (((addr) << 8) | 0x00008000)
0069 #define OHCI1394_PhyControl_ReadDone 0x80000000
0070 #define OHCI1394_PhyControl_ReadData(r) (((r) & 0x00ff0000) >> 16)
0071 #define OHCI1394_PhyControl_Write(addr, data) (((addr) << 8) | (data) | 0x00004000)
0072 #define OHCI1394_PhyControl_WritePending 0x00004000
0073 #define OHCI1394_IsochronousCycleTimer 0x0F0
0074 #define OHCI1394_AsReqFilterHiSet 0x100
0075 #define OHCI1394_AsReqFilterHiClear 0x104
0076 #define OHCI1394_AsReqFilterLoSet 0x108
0077 #define OHCI1394_AsReqFilterLoClear 0x10C
0078 #define OHCI1394_PhyReqFilterHiSet 0x110
0079 #define OHCI1394_PhyReqFilterHiClear 0x114
0080 #define OHCI1394_PhyReqFilterLoSet 0x118
0081 #define OHCI1394_PhyReqFilterLoClear 0x11C
0082 #define OHCI1394_PhyUpperBound 0x120
0083
0084 #define OHCI1394_AsReqTrContextBase 0x180
0085 #define OHCI1394_AsReqTrContextControlSet 0x180
0086 #define OHCI1394_AsReqTrContextControlClear 0x184
0087 #define OHCI1394_AsReqTrCommandPtr 0x18C
0088
0089 #define OHCI1394_AsRspTrContextBase 0x1A0
0090 #define OHCI1394_AsRspTrContextControlSet 0x1A0
0091 #define OHCI1394_AsRspTrContextControlClear 0x1A4
0092 #define OHCI1394_AsRspTrCommandPtr 0x1AC
0093
0094 #define OHCI1394_AsReqRcvContextBase 0x1C0
0095 #define OHCI1394_AsReqRcvContextControlSet 0x1C0
0096 #define OHCI1394_AsReqRcvContextControlClear 0x1C4
0097 #define OHCI1394_AsReqRcvCommandPtr 0x1CC
0098
0099 #define OHCI1394_AsRspRcvContextBase 0x1E0
0100 #define OHCI1394_AsRspRcvContextControlSet 0x1E0
0101 #define OHCI1394_AsRspRcvContextControlClear 0x1E4
0102 #define OHCI1394_AsRspRcvCommandPtr 0x1EC
0103
0104
0105 #define OHCI1394_IsoXmitContextBase(n) (0x200 + 16 * (n))
0106 #define OHCI1394_IsoXmitContextControlSet(n) (0x200 + 16 * (n))
0107 #define OHCI1394_IsoXmitContextControlClear(n) (0x204 + 16 * (n))
0108 #define OHCI1394_IsoXmitCommandPtr(n) (0x20C + 16 * (n))
0109
0110
0111 #define OHCI1394_IsoRcvContextBase(n) (0x400 + 32 * (n))
0112 #define OHCI1394_IsoRcvContextControlSet(n) (0x400 + 32 * (n))
0113 #define OHCI1394_IsoRcvContextControlClear(n) (0x404 + 32 * (n))
0114 #define OHCI1394_IsoRcvCommandPtr(n) (0x40C + 32 * (n))
0115 #define OHCI1394_IsoRcvContextMatch(n) (0x410 + 32 * (n))
0116
0117
0118 #define OHCI1394_reqTxComplete 0x00000001
0119 #define OHCI1394_respTxComplete 0x00000002
0120 #define OHCI1394_ARRQ 0x00000004
0121 #define OHCI1394_ARRS 0x00000008
0122 #define OHCI1394_RQPkt 0x00000010
0123 #define OHCI1394_RSPkt 0x00000020
0124 #define OHCI1394_isochTx 0x00000040
0125 #define OHCI1394_isochRx 0x00000080
0126 #define OHCI1394_postedWriteErr 0x00000100
0127 #define OHCI1394_lockRespErr 0x00000200
0128 #define OHCI1394_selfIDComplete 0x00010000
0129 #define OHCI1394_busReset 0x00020000
0130 #define OHCI1394_regAccessFail 0x00040000
0131 #define OHCI1394_phy 0x00080000
0132 #define OHCI1394_cycleSynch 0x00100000
0133 #define OHCI1394_cycle64Seconds 0x00200000
0134 #define OHCI1394_cycleLost 0x00400000
0135 #define OHCI1394_cycleInconsistent 0x00800000
0136 #define OHCI1394_unrecoverableError 0x01000000
0137 #define OHCI1394_cycleTooLong 0x02000000
0138 #define OHCI1394_phyRegRcvd 0x04000000
0139 #define OHCI1394_masterIntEnable 0x80000000
0140
0141 #define OHCI1394_evt_no_status 0x0
0142 #define OHCI1394_evt_long_packet 0x2
0143 #define OHCI1394_evt_missing_ack 0x3
0144 #define OHCI1394_evt_underrun 0x4
0145 #define OHCI1394_evt_overrun 0x5
0146 #define OHCI1394_evt_descriptor_read 0x6
0147 #define OHCI1394_evt_data_read 0x7
0148 #define OHCI1394_evt_data_write 0x8
0149 #define OHCI1394_evt_bus_reset 0x9
0150 #define OHCI1394_evt_timeout 0xa
0151 #define OHCI1394_evt_tcode_err 0xb
0152 #define OHCI1394_evt_reserved_b 0xc
0153 #define OHCI1394_evt_reserved_c 0xd
0154 #define OHCI1394_evt_unknown 0xe
0155 #define OHCI1394_evt_flushed 0xf
0156
0157 #define OHCI1394_phy_tcode 0xe
0158
0159 #endif