drivers/firewire/init_ohci1394_dma.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
0004  *
0005  * Copyright (C) 2006-2007      Bernhard Kaindl <bk@suse.de>
0006  *
0007  * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
0008  * this file has functions to:
0009  * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
0010  * - reset and initialize them and make them join the IEEE1394 bus and
0011  * - enable physical DMA on them to allow remote debugging
0012  *
0013  * All code and data is marked as __init and __initdata, respective as
0014  * during boot, all OHCI1394 controllers may be claimed by the firewire
0015  * stack and at this point, this code should not touch them anymore.
0016  *
0017  * To use physical DMA after the initialization of the firewire stack,
0018  * be sure that the stack enables it and (re-)attach after the bus reset
0019  * which may be caused by the firewire stack initialization.
0020  */
0021
0022 #include <linux/delay.h>
0023 #include <linux/io.h>
0024 #include <linux/kernel.h>
0025 #include <linux/pci.h>      /* for PCI defines */
0026 #include <linux/string.h>
0027
0028 #include <asm/pci-direct.h> /* for direct PCI config space access */
0029 #include <asm/fixmap.h>
0030
0031 #include <linux/init_ohci1394_dma.h>
0032 #include "ohci.h"
0033
0034 int __initdata init_ohci1394_dma_early;
0035
0036 struct ohci {
0037     void __iomem *registers;
0038 };
0039
0040 static inline void reg_write(const struct ohci *ohci, int offset, u32 data)
0041 {
0042     writel(data, ohci->registers + offset);
0043 }
0044
0045 static inline u32 reg_read(const struct ohci *ohci, int offset)
0046 {
0047     return readl(ohci->registers + offset);
0048 }
0049
0050 #define OHCI_LOOP_COUNT     100 /* Number of loops for reg read waits */
0051
0052 /* Reads a PHY register of an OHCI-1394 controller */
0053 static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr)
0054 {
0055     int i;
0056     u32 r;
0057
0058     reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
0059
0060     for (i = 0; i < OHCI_LOOP_COUNT; i++) {
0061         if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
0062             break;
0063         mdelay(1);
0064     }
0065     r = reg_read(ohci, OHCI1394_PhyControl);
0066
0067     return (r & 0x00ff0000) >> 16;
0068 }
0069
0070 /* Writes to a PHY register of an OHCI-1394 controller */
0071 static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data)
0072 {
0073     int i;
0074
0075     reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
0076
0077     for (i = 0; i < OHCI_LOOP_COUNT; i++) {
0078         if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000))
0079             break;
0080         mdelay(1);
0081     }
0082 }
0083
0084 /* Resets an OHCI-1394 controller (for sane state before initialization) */
0085 static inline void __init init_ohci1394_soft_reset(struct ohci *ohci)
0086 {
0087     int i;
0088
0089     reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
0090
0091     for (i = 0; i < OHCI_LOOP_COUNT; i++) {
0092         if (!(reg_read(ohci, OHCI1394_HCControlSet)
0093                    & OHCI1394_HCControl_softReset))
0094             break;
0095         mdelay(1);
0096     }
0097 }
0098
0099 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
0100 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
0101 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
0102
0103 /* Basic OHCI-1394 register and port inititalization */
0104 static inline void __init init_ohci1394_initialize(struct ohci *ohci)
0105 {
0106     u32 bus_options;
0107     int num_ports, i;
0108
0109     /* Put some defaults to these undefined bus options */
0110     bus_options = reg_read(ohci, OHCI1394_BusOptions);
0111     bus_options |=  0x60000000; /* Enable CMC and ISC */
0112     bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
0113     bus_options &= ~0x18000000; /* Disable PMC and BMC */
0114     reg_write(ohci, OHCI1394_BusOptions, bus_options);
0115
0116     /* Set the bus number */
0117     reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
0118
0119     /* Enable posted writes */
0120     reg_write(ohci, OHCI1394_HCControlSet,
0121             OHCI1394_HCControl_postedWriteEnable);
0122
0123     /* Clear link control register */
0124     reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
0125
0126     /* enable phys */
0127     reg_write(ohci, OHCI1394_LinkControlSet,
0128             OHCI1394_LinkControl_rcvPhyPkt);
0129
0130     /* Don't accept phy packets into AR request context */
0131     reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
0132
0133     /* Clear the Isochonouys interrupt masks */
0134     reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
0135     reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
0136     reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
0137     reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
0138
0139     /* Accept asynchronous transfer requests from all nodes for now */
0140     reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
0141
0142     /* Specify asynchronous transfer retries */
0143     reg_write(ohci, OHCI1394_ATRetries,
0144           OHCI1394_MAX_AT_REQ_RETRIES |
0145           (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
0146           (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
0147
0148     /* We don't want hardware swapping */
0149     reg_write(ohci, OHCI1394_HCControlClear,
0150           OHCI1394_HCControl_noByteSwapData);
0151
0152     /* Enable link */
0153     reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
0154
0155     /* If anything is connected to a port, make sure it is enabled */
0156     num_ports = get_phy_reg(ohci, 2) & 0xf;
0157     for (i = 0; i < num_ports; i++) {
0158         unsigned int status;
0159
0160         set_phy_reg(ohci, 7, i);
0161         status = get_phy_reg(ohci, 8);
0162
0163         if (status & 0x20)
0164             set_phy_reg(ohci, 8, status & ~1);
0165     }
0166 }
0167
0168 /**
0169  * init_ohci1394_wait_for_busresets - wait until bus resets are completed
0170  *
0171  * OHCI1394 initialization itself and any device going on- or offline
0172  * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
0173  * specifies that physical DMA is disabled on each bus reset and it
0174  * has to be enabled after each bus reset when needed. We resort
0175  * to polling here because on early boot, we have no interrupts.
0176  */
0177 static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci)
0178 {
0179     int i, events;
0180
0181     for (i = 0; i < 9; i++) {
0182         mdelay(200);
0183         events = reg_read(ohci, OHCI1394_IntEventSet);
0184         if (events & OHCI1394_busReset)
0185             reg_write(ohci, OHCI1394_IntEventClear,
0186                     OHCI1394_busReset);
0187     }
0188 }
0189
0190 /**
0191  * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
0192  * This enables remote DMA access over IEEE1394 from every host for the low
0193  * 4GB of address space. DMA accesses above 4GB are not available currently.
0194  */
0195 static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci)
0196 {
0197     reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
0198     reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
0199     reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
0200 }
0201
0202 /**
0203  * init_ohci1394_reset_and_init_dma - init controller and enable DMA
0204  * This initializes the given controller and enables physical DMA engine in it.
0205  */
0206 static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci)
0207 {
0208     /* Start off with a soft reset, clears everything to a sane state. */
0209     init_ohci1394_soft_reset(ohci);
0210
0211     /* Accessing some registers without LPS enabled may cause lock up */
0212     reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
0213
0214     /* Disable and clear interrupts */
0215     reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
0216     reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
0217
0218     mdelay(50); /* Wait 50msec to make sure we have full link enabled */
0219
0220     init_ohci1394_initialize(ohci);
0221     /*
0222      * The initialization causes at least one IEEE1394 bus reset. Enabling
0223      * physical DMA only works *after* *all* bus resets have calmed down:
0224      */
0225     init_ohci1394_wait_for_busresets(ohci);
0226
0227     /* We had to wait and do this now if we want to debug early problems */
0228     init_ohci1394_enable_physical_dma(ohci);
0229 }
0230
0231 /**
0232  * init_ohci1394_controller - Map the registers of the controller and init DMA
0233  * This maps the registers of the specified controller and initializes it
0234  */
0235 static inline void __init init_ohci1394_controller(int num, int slot, int func)
0236 {
0237     unsigned long ohci_base;
0238     struct ohci ohci;
0239
0240     printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
0241              " at %02x:%02x.%x\n", num, slot, func);
0242
0243     ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
0244                            & PCI_BASE_ADDRESS_MEM_MASK;
0245
0246     set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
0247
0248     ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
0249
0250     init_ohci1394_reset_and_init_dma(&ohci);
0251 }
0252
0253 /**
0254  * debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them
0255  * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
0256  */
0257 void __init init_ohci1394_dma_on_all_controllers(void)
0258 {
0259     int num, slot, func;
0260     u32 class;
0261
0262     if (!early_pci_allowed())
0263         return;
0264
0265     /* Poor man's PCI discovery, the only thing we can do at early boot */
0266     for (num = 0; num < 32; num++) {
0267         for (slot = 0; slot < 32; slot++) {
0268             for (func = 0; func < 8; func++) {
0269                 class = read_pci_config(num, slot, func,
0270                             PCI_CLASS_REVISION);
0271                 if (class == 0xffffffff)
0272                     continue; /* No device at this func */
0273
0274                 if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
0275                     continue; /* Not an OHCI-1394 device */
0276
0277                 init_ohci1394_controller(num, slot, func);
0278                 break; /* Assume one controller per device */
0279             }
0280         }
0281     }
0282     printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
0283 }
0284
0285 /**
0286  * setup_init_ohci1394_early - enables early OHCI1394 DMA initialization
0287  */
0288 static int __init setup_ohci1394_dma(char *opt)
0289 {
0290     if (!strcmp(opt, "early"))
0291         init_ohci1394_dma_early = 1;
0292     return 0;
0293 }
0294
0295 /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
0296 early_param("ohci1394_dma", setup_ohci1394_dma);