drivers/edac/ti_edac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
0004  *
0005  * Texas Instruments DDR3 ECC error correction and detection driver
0006  *
0007  * This program is free software; you can redistribute it and/or modify it
0008  * under the terms and conditions of the GNU General Public License,
0009  * version 2, as published by the Free Software Foundation.
0010  *
0011  * This program is distributed in the hope it will be useful, but WITHOUT
0012  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0013  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
0014  * more details.
0015  *
0016  * You should have received a copy of the GNU General Public License along with
0017  * this program.  If not, see <http://www.gnu.org/licenses/>.
0018  */
0019
0020 #include <linux/init.h>
0021 #include <linux/edac.h>
0022 #include <linux/io.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_device.h>
0026 #include <linux/module.h>
0027
0028 #include "edac_module.h"
0029
0030 /* EMIF controller registers */
0031 #define EMIF_SDRAM_CONFIG       0x008
0032 #define EMIF_IRQ_STATUS         0x0ac
0033 #define EMIF_IRQ_ENABLE_SET     0x0b4
0034 #define EMIF_ECC_CTRL           0x110
0035 #define EMIF_1B_ECC_ERR_CNT     0x130
0036 #define EMIF_1B_ECC_ERR_THRSH       0x134
0037 #define EMIF_1B_ECC_ERR_ADDR_LOG    0x13c
0038 #define EMIF_2B_ECC_ERR_ADDR_LOG    0x140
0039
0040 /* Bit definitions for EMIF_SDRAM_CONFIG */
0041 #define SDRAM_TYPE_SHIFT        29
0042 #define SDRAM_TYPE_MASK         GENMASK(31, 29)
0043 #define SDRAM_TYPE_DDR3         (3 << SDRAM_TYPE_SHIFT)
0044 #define SDRAM_TYPE_DDR2         (2 << SDRAM_TYPE_SHIFT)
0045 #define SDRAM_NARROW_MODE_MASK      GENMASK(15, 14)
0046 #define SDRAM_K2_NARROW_MODE_SHIFT  12
0047 #define SDRAM_K2_NARROW_MODE_MASK   GENMASK(13, 12)
0048 #define SDRAM_ROWSIZE_SHIFT     7
0049 #define SDRAM_ROWSIZE_MASK      GENMASK(9, 7)
0050 #define SDRAM_IBANK_SHIFT       4
0051 #define SDRAM_IBANK_MASK        GENMASK(6, 4)
0052 #define SDRAM_K2_IBANK_SHIFT        5
0053 #define SDRAM_K2_IBANK_MASK     GENMASK(6, 5)
0054 #define SDRAM_K2_EBANK_SHIFT        3
0055 #define SDRAM_K2_EBANK_MASK     BIT(SDRAM_K2_EBANK_SHIFT)
0056 #define SDRAM_PAGESIZE_SHIFT        0
0057 #define SDRAM_PAGESIZE_MASK     GENMASK(2, 0)
0058 #define SDRAM_K2_PAGESIZE_SHIFT     0
0059 #define SDRAM_K2_PAGESIZE_MASK      GENMASK(1, 0)
0060
0061 #define EMIF_1B_ECC_ERR_THRSH_SHIFT 24
0062
0063 /* IRQ bit definitions */
0064 #define EMIF_1B_ECC_ERR         BIT(5)
0065 #define EMIF_2B_ECC_ERR         BIT(4)
0066 #define EMIF_WR_ECC_ERR         BIT(3)
0067 #define EMIF_SYS_ERR            BIT(0)
0068 /* Bit 31 enables ECC and 28 enables RMW */
0069 #define ECC_ENABLED         (BIT(31) | BIT(28))
0070
0071 #define EDAC_MOD_NAME           "ti-emif-edac"
0072
0073 enum {
0074     EMIF_TYPE_DRA7,
0075     EMIF_TYPE_K2
0076 };
0077
0078 struct ti_edac {
0079     void __iomem *reg;
0080 };
0081
0082 static u32 ti_edac_readl(struct ti_edac *edac, u16 offset)
0083 {
0084     return readl_relaxed(edac->reg + offset);
0085 }
0086
0087 static void ti_edac_writel(struct ti_edac *edac, u32 val, u16 offset)
0088 {
0089     writel_relaxed(val, edac->reg + offset);
0090 }
0091
0092 static irqreturn_t ti_edac_isr(int irq, void *data)
0093 {
0094     struct mem_ctl_info *mci = data;
0095     struct ti_edac *edac = mci->pvt_info;
0096     u32 irq_status;
0097     u32 err_addr;
0098     int err_count;
0099
0100     irq_status = ti_edac_readl(edac, EMIF_IRQ_STATUS);
0101
0102     if (irq_status & EMIF_1B_ECC_ERR) {
0103         err_addr = ti_edac_readl(edac, EMIF_1B_ECC_ERR_ADDR_LOG);
0104         err_count = ti_edac_readl(edac, EMIF_1B_ECC_ERR_CNT);
0105         ti_edac_writel(edac, err_count, EMIF_1B_ECC_ERR_CNT);
0106         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
0107                      err_addr >> PAGE_SHIFT,
0108                      err_addr & ~PAGE_MASK, -1, 0, 0, 0,
0109                      mci->ctl_name, "1B");
0110     }
0111
0112     if (irq_status & EMIF_2B_ECC_ERR) {
0113         err_addr = ti_edac_readl(edac, EMIF_2B_ECC_ERR_ADDR_LOG);
0114         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0115                      err_addr >> PAGE_SHIFT,
0116                      err_addr & ~PAGE_MASK, -1, 0, 0, 0,
0117                      mci->ctl_name, "2B");
0118     }
0119
0120     if (irq_status & EMIF_WR_ECC_ERR)
0121         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0122                      0, 0, -1, 0, 0, 0,
0123                      mci->ctl_name, "WR");
0124
0125     ti_edac_writel(edac, irq_status, EMIF_IRQ_STATUS);
0126
0127     return IRQ_HANDLED;
0128 }
0129
0130 static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type)
0131 {
0132     struct dimm_info *dimm;
0133     struct ti_edac *edac = mci->pvt_info;
0134     int bits;
0135     u32 val;
0136     u32 memsize;
0137
0138     dimm = edac_get_dimm(mci, 0, 0, 0);
0139
0140     val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG);
0141
0142     if (type == EMIF_TYPE_DRA7) {
0143         bits = ((val & SDRAM_PAGESIZE_MASK) >> SDRAM_PAGESIZE_SHIFT) + 8;
0144         bits += ((val & SDRAM_ROWSIZE_MASK) >> SDRAM_ROWSIZE_SHIFT) + 9;
0145         bits += (val & SDRAM_IBANK_MASK) >> SDRAM_IBANK_SHIFT;
0146
0147         if (val & SDRAM_NARROW_MODE_MASK) {
0148             bits++;
0149             dimm->dtype = DEV_X16;
0150         } else {
0151             bits += 2;
0152             dimm->dtype = DEV_X32;
0153         }
0154     } else {
0155         bits = 16;
0156         bits += ((val & SDRAM_K2_PAGESIZE_MASK) >>
0157             SDRAM_K2_PAGESIZE_SHIFT) + 8;
0158         bits += (val & SDRAM_K2_IBANK_MASK) >> SDRAM_K2_IBANK_SHIFT;
0159         bits += (val & SDRAM_K2_EBANK_MASK) >> SDRAM_K2_EBANK_SHIFT;
0160
0161         val = (val & SDRAM_K2_NARROW_MODE_MASK) >>
0162             SDRAM_K2_NARROW_MODE_SHIFT;
0163         switch (val) {
0164         case 0:
0165             bits += 3;
0166             dimm->dtype = DEV_X64;
0167             break;
0168         case 1:
0169             bits += 2;
0170             dimm->dtype = DEV_X32;
0171             break;
0172         case 2:
0173             bits++;
0174             dimm->dtype = DEV_X16;
0175             break;
0176         }
0177     }
0178
0179     memsize = 1 << bits;
0180
0181     dimm->nr_pages = memsize >> PAGE_SHIFT;
0182     dimm->grain = 4;
0183     if ((val & SDRAM_TYPE_MASK) == SDRAM_TYPE_DDR2)
0184         dimm->mtype = MEM_DDR2;
0185     else
0186         dimm->mtype = MEM_DDR3;
0187
0188     val = ti_edac_readl(edac, EMIF_ECC_CTRL);
0189     if (val & ECC_ENABLED)
0190         dimm->edac_mode = EDAC_SECDED;
0191     else
0192         dimm->edac_mode = EDAC_NONE;
0193 }
0194
0195 static const struct of_device_id ti_edac_of_match[] = {
0196     { .compatible = "ti,emif-keystone", .data = (void *)EMIF_TYPE_K2 },
0197     { .compatible = "ti,emif-dra7xx", .data = (void *)EMIF_TYPE_DRA7 },
0198     {},
0199 };
0200 MODULE_DEVICE_TABLE(of, ti_edac_of_match);
0201
0202 static int _emif_get_id(struct device_node *node)
0203 {
0204     struct device_node *np;
0205     const __be32 *addrp;
0206     u32 addr, my_addr;
0207     int my_id = 0;
0208
0209     addrp = of_get_address(node, 0, NULL, NULL);
0210     my_addr = (u32)of_translate_address(node, addrp);
0211
0212     for_each_matching_node(np, ti_edac_of_match) {
0213         if (np == node)
0214             continue;
0215
0216         addrp = of_get_address(np, 0, NULL, NULL);
0217         addr = (u32)of_translate_address(np, addrp);
0218
0219         edac_printk(KERN_INFO, EDAC_MOD_NAME,
0220                 "addr=%x, my_addr=%x\n",
0221                 addr, my_addr);
0222
0223         if (addr < my_addr)
0224             my_id++;
0225     }
0226
0227     return my_id;
0228 }
0229
0230 static int ti_edac_probe(struct platform_device *pdev)
0231 {
0232     int error_irq = 0, ret = -ENODEV;
0233     struct device *dev = &pdev->dev;
0234     struct resource *res;
0235     void __iomem *reg;
0236     struct mem_ctl_info *mci;
0237     struct edac_mc_layer layers[1];
0238     const struct of_device_id *id;
0239     struct ti_edac *edac;
0240     int emif_id;
0241
0242     id = of_match_device(ti_edac_of_match, &pdev->dev);
0243     if (!id)
0244         return -ENODEV;
0245
0246     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0247     reg = devm_ioremap_resource(dev, res);
0248     if (IS_ERR(reg))
0249         return PTR_ERR(reg);
0250
0251     layers[0].type = EDAC_MC_LAYER_ALL_MEM;
0252     layers[0].size = 1;
0253
0254     /* Allocate ID number for our EMIF controller */
0255     emif_id = _emif_get_id(pdev->dev.of_node);
0256     if (emif_id < 0)
0257         return -EINVAL;
0258
0259     mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac));
0260     if (!mci)
0261         return -ENOMEM;
0262
0263     mci->pdev = &pdev->dev;
0264     edac = mci->pvt_info;
0265     edac->reg = reg;
0266     platform_set_drvdata(pdev, mci);
0267
0268     mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
0269     mci->edac_ctl_cap = EDAC_FLAG_SECDED | EDAC_FLAG_NONE;
0270     mci->mod_name = EDAC_MOD_NAME;
0271     mci->ctl_name = id->compatible;
0272     mci->dev_name = dev_name(&pdev->dev);
0273
0274     /* Setup memory layout */
0275     ti_edac_setup_dimm(mci, (u32)(id->data));
0276
0277     /* add EMIF ECC error handler */
0278     error_irq = platform_get_irq(pdev, 0);
0279     if (error_irq < 0) {
0280         ret = error_irq;
0281         goto err;
0282     }
0283
0284     ret = devm_request_irq(dev, error_irq, ti_edac_isr, 0,
0285                    "emif-edac-irq", mci);
0286     if (ret) {
0287         edac_printk(KERN_ERR, EDAC_MOD_NAME,
0288                 "request_irq fail for EMIF EDAC irq\n");
0289         goto err;
0290     }
0291
0292     ret = edac_mc_add_mc(mci);
0293     if (ret) {
0294         edac_printk(KERN_ERR, EDAC_MOD_NAME,
0295                 "Failed to register mci: %d.\n", ret);
0296         goto err;
0297     }
0298
0299     /* Generate an interrupt with each 1b error */
0300     ti_edac_writel(edac, 1 << EMIF_1B_ECC_ERR_THRSH_SHIFT,
0301                EMIF_1B_ECC_ERR_THRSH);
0302
0303     /* Enable interrupts */
0304     ti_edac_writel(edac,
0305                EMIF_1B_ECC_ERR | EMIF_2B_ECC_ERR | EMIF_WR_ECC_ERR,
0306                EMIF_IRQ_ENABLE_SET);
0307
0308     return 0;
0309
0310 err:
0311     edac_mc_free(mci);
0312     return ret;
0313 }
0314
0315 static int ti_edac_remove(struct platform_device *pdev)
0316 {
0317     struct mem_ctl_info *mci = platform_get_drvdata(pdev);
0318
0319     edac_mc_del_mc(&pdev->dev);
0320     edac_mc_free(mci);
0321
0322     return 0;
0323 }
0324
0325 static struct platform_driver ti_edac_driver = {
0326     .probe = ti_edac_probe,
0327     .remove = ti_edac_remove,
0328     .driver = {
0329            .name = EDAC_MOD_NAME,
0330            .of_match_table = ti_edac_of_match,
0331     },
0332 };
0333
0334 module_platform_driver(ti_edac_driver);
0335
0336 MODULE_AUTHOR("Texas Instruments Inc.");
0337 MODULE_DESCRIPTION("EDAC Driver for Texas Instruments DDR3 MC");
0338 MODULE_LICENSE("GPL v2");