drivers/edac/skx_common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Common codes for both the skx_edac driver and Intel 10nm server EDAC driver.
0004  * Originally split out from the skx_edac driver.
0005  *
0006  * Copyright (c) 2018, Intel Corporation.
0007  */
0008
0009 #ifndef _SKX_COMM_EDAC_H
0010 #define _SKX_COMM_EDAC_H
0011
0012 #include <linux/bits.h>
0013
0014 #define MSG_SIZE        1024
0015
0016 /*
0017  * Debug macros
0018  */
0019 #define skx_printk(level, fmt, arg...)          \
0020     edac_printk(level, "skx", fmt, ##arg)
0021
0022 #define skx_mc_printk(mci, level, fmt, arg...)      \
0023     edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
0024
0025 /*
0026  * Get a bit field at register value <v>, from bit <lo> to bit <hi>
0027  */
0028 #define GET_BITFIELD(v, lo, hi) \
0029     (((v) & GENMASK_ULL((hi), (lo))) >> (lo))
0030
0031 #define SKX_NUM_IMC     2   /* Memory controllers per socket */
0032 #define SKX_NUM_CHANNELS    3   /* Channels per memory controller */
0033 #define SKX_NUM_DIMMS       2   /* Max DIMMS per channel */
0034
0035 #define I10NM_NUM_DDR_IMC   4
0036 #define I10NM_NUM_DDR_CHANNELS  2
0037 #define I10NM_NUM_DDR_DIMMS 2
0038
0039 #define I10NM_NUM_HBM_IMC   16
0040 #define I10NM_NUM_HBM_CHANNELS  2
0041 #define I10NM_NUM_HBM_DIMMS 1
0042
0043 #define I10NM_NUM_IMC       (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
0044 #define I10NM_NUM_CHANNELS  MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
0045 #define I10NM_NUM_DIMMS     MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
0046
0047 #define MAX(a, b)   ((a) > (b) ? (a) : (b))
0048 #define NUM_IMC     MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
0049 #define NUM_CHANNELS    MAX(SKX_NUM_CHANNELS, I10NM_NUM_CHANNELS)
0050 #define NUM_DIMMS   MAX(SKX_NUM_DIMMS, I10NM_NUM_DIMMS)
0051
0052 #define IS_DIMM_PRESENT(r)      GET_BITFIELD(r, 15, 15)
0053 #define IS_NVDIMM_PRESENT(r, i)     GET_BITFIELD(r, i, i)
0054
0055 /*
0056  * Each cpu socket contains some pci devices that provide global
0057  * information, and also some that are local to each of the two
0058  * memory controllers on the die.
0059  */
0060 struct skx_dev {
0061     struct list_head list;
0062     u8 bus[4];
0063     int seg;
0064     struct pci_dev *sad_all;
0065     struct pci_dev *util_all;
0066     struct pci_dev *uracu; /* for i10nm CPU */
0067     struct pci_dev *pcu_cr3; /* for HBM memory detection */
0068     u32 mcroute;
0069     struct skx_imc {
0070         struct mem_ctl_info *mci;
0071         struct pci_dev *mdev; /* for i10nm CPU */
0072         void __iomem *mbase;  /* for i10nm CPU */
0073         int chan_mmio_sz;     /* for i10nm CPU */
0074         int num_channels; /* channels per memory controller */
0075         int num_dimms; /* dimms per channel */
0076         bool hbm_mc;
0077         u8 mc;  /* system wide mc# */
0078         u8 lmc; /* socket relative mc# */
0079         u8 src_id, node_id;
0080         struct skx_channel {
0081             struct pci_dev  *cdev;
0082             struct pci_dev  *edev;
0083             u32 retry_rd_err_log_s;
0084             u32 retry_rd_err_log_d;
0085             struct skx_dimm {
0086                 u8 close_pg;
0087                 u8 bank_xor_enable;
0088                 u8 fine_grain_bank;
0089                 u8 rowbits;
0090                 u8 colbits;
0091             } dimms[NUM_DIMMS];
0092         } chan[NUM_CHANNELS];
0093     } imc[NUM_IMC];
0094 };
0095
0096 struct skx_pvt {
0097     struct skx_imc  *imc;
0098 };
0099
0100 enum type {
0101     SKX,
0102     I10NM,
0103     SPR
0104 };
0105
0106 enum {
0107     INDEX_SOCKET,
0108     INDEX_MEMCTRL,
0109     INDEX_CHANNEL,
0110     INDEX_DIMM,
0111     INDEX_NM_FIRST,
0112     INDEX_NM_MEMCTRL = INDEX_NM_FIRST,
0113     INDEX_NM_CHANNEL,
0114     INDEX_NM_DIMM,
0115     INDEX_MAX
0116 };
0117
0118 #define BIT_NM_MEMCTRL  BIT_ULL(INDEX_NM_MEMCTRL)
0119 #define BIT_NM_CHANNEL  BIT_ULL(INDEX_NM_CHANNEL)
0120 #define BIT_NM_DIMM BIT_ULL(INDEX_NM_DIMM)
0121
0122 struct decoded_addr {
0123     struct skx_dev *dev;
0124     u64 addr;
0125     int socket;
0126     int imc;
0127     int channel;
0128     u64 chan_addr;
0129     int sktways;
0130     int chanways;
0131     int dimm;
0132     int rank;
0133     int channel_rank;
0134     u64 rank_address;
0135     int row;
0136     int column;
0137     int bank_address;
0138     int bank_group;
0139 };
0140
0141 struct res_config {
0142     enum type type;
0143     /* Configuration agent device ID */
0144     unsigned int decs_did;
0145     /* Default bus number configuration register offset */
0146     int busno_cfg_offset;
0147     /* Per DDR channel memory-mapped I/O size */
0148     int ddr_chan_mmio_sz;
0149     /* Per HBM channel memory-mapped I/O size */
0150     int hbm_chan_mmio_sz;
0151     bool support_ddr5;
0152     /* SAD device number and function number */
0153     unsigned int sad_all_devfn;
0154     int sad_all_offset;
0155     /* Offsets of retry_rd_err_log registers */
0156     u32 *offsets_scrub;
0157     u32 *offsets_demand;
0158 };
0159
0160 typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci,
0161                  struct res_config *cfg);
0162 typedef bool (*skx_decode_f)(struct decoded_addr *res);
0163 typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err);
0164
0165 int __init skx_adxl_get(void);
0166 void __exit skx_adxl_put(void);
0167 void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log);
0168 void skx_set_mem_cfg(bool mem_cfg_2lm);
0169
0170 int skx_get_src_id(struct skx_dev *d, int off, u8 *id);
0171 int skx_get_node_id(struct skx_dev *d, u8 *id);
0172
0173 int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list);
0174
0175 int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm);
0176
0177 int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
0178               struct skx_imc *imc, int chan, int dimmno,
0179               struct res_config *cfg);
0180
0181 int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
0182             int chan, int dimmno, const char *mod_str);
0183
0184 int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
0185              const char *ctl_name, const char *mod_str,
0186              get_dimm_config_f get_dimm_config,
0187              struct res_config *cfg);
0188
0189 int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
0190             void *data);
0191
0192 void skx_remove(void);
0193
0194 #endif /* _SKX_COMM_EDAC_H */