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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * EDAC driver for Intel(R) Xeon(R) Skylake processors
0004  * Copyright (c) 2016, Intel Corporation.
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/processor.h>
0009 #include <asm/cpu_device_id.h>
0010 #include <asm/intel-family.h>
0011 #include <asm/mce.h>
0012 
0013 #include "edac_module.h"
0014 #include "skx_common.h"
0015 
0016 #define EDAC_MOD_STR    "skx_edac"
0017 
0018 /*
0019  * Debug macros
0020  */
0021 #define skx_printk(level, fmt, arg...)          \
0022     edac_printk(level, "skx", fmt, ##arg)
0023 
0024 #define skx_mc_printk(mci, level, fmt, arg...)      \
0025     edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg)
0026 
0027 static struct list_head *skx_edac_list;
0028 
0029 static u64 skx_tolm, skx_tohm;
0030 static int skx_num_sockets;
0031 static unsigned int nvdimm_count;
0032 
0033 #define MASK26  0x3FFFFFF       /* Mask for 2^26 */
0034 #define MASK29  0x1FFFFFFF      /* Mask for 2^29 */
0035 
0036 static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx)
0037 {
0038     struct skx_dev *d;
0039 
0040     list_for_each_entry(d, skx_edac_list, list) {
0041         if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number)
0042             return d;
0043     }
0044 
0045     return NULL;
0046 }
0047 
0048 enum munittype {
0049     CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD,
0050     ERRCHAN0, ERRCHAN1, ERRCHAN2,
0051 };
0052 
0053 struct munit {
0054     u16 did;
0055     u16 devfn[SKX_NUM_IMC];
0056     u8  busidx;
0057     u8  per_socket;
0058     enum munittype mtype;
0059 };
0060 
0061 /*
0062  * List of PCI device ids that we need together with some device
0063  * number and function numbers to tell which memory controller the
0064  * device belongs to.
0065  */
0066 static const struct munit skx_all_munits[] = {
0067     { 0x2054, { }, 1, 1, SAD_ALL },
0068     { 0x2055, { }, 1, 1, UTIL_ALL },
0069     { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 },
0070     { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 },
0071     { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 },
0072     { 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 },
0073     { 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 },
0074     { 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 },
0075     { 0x208e, { }, 1, 0, SAD },
0076     { }
0077 };
0078 
0079 static int get_all_munits(const struct munit *m)
0080 {
0081     struct pci_dev *pdev, *prev;
0082     struct skx_dev *d;
0083     u32 reg;
0084     int i = 0, ndev = 0;
0085 
0086     prev = NULL;
0087     for (;;) {
0088         pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev);
0089         if (!pdev)
0090             break;
0091         ndev++;
0092         if (m->per_socket == SKX_NUM_IMC) {
0093             for (i = 0; i < SKX_NUM_IMC; i++)
0094                 if (m->devfn[i] == pdev->devfn)
0095                     break;
0096             if (i == SKX_NUM_IMC)
0097                 goto fail;
0098         }
0099         d = get_skx_dev(pdev->bus, m->busidx);
0100         if (!d)
0101             goto fail;
0102 
0103         /* Be sure that the device is enabled */
0104         if (unlikely(pci_enable_device(pdev) < 0)) {
0105             skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n",
0106                    PCI_VENDOR_ID_INTEL, m->did);
0107             goto fail;
0108         }
0109 
0110         switch (m->mtype) {
0111         case CHAN0:
0112         case CHAN1:
0113         case CHAN2:
0114             pci_dev_get(pdev);
0115             d->imc[i].chan[m->mtype].cdev = pdev;
0116             break;
0117         case ERRCHAN0:
0118         case ERRCHAN1:
0119         case ERRCHAN2:
0120             pci_dev_get(pdev);
0121             d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev;
0122             break;
0123         case SAD_ALL:
0124             pci_dev_get(pdev);
0125             d->sad_all = pdev;
0126             break;
0127         case UTIL_ALL:
0128             pci_dev_get(pdev);
0129             d->util_all = pdev;
0130             break;
0131         case SAD:
0132             /*
0133              * one of these devices per core, including cores
0134              * that don't exist on this SKU. Ignore any that
0135              * read a route table of zero, make sure all the
0136              * non-zero values match.
0137              */
0138             pci_read_config_dword(pdev, 0xB4, &reg);
0139             if (reg != 0) {
0140                 if (d->mcroute == 0) {
0141                     d->mcroute = reg;
0142                 } else if (d->mcroute != reg) {
0143                     skx_printk(KERN_ERR, "mcroute mismatch\n");
0144                     goto fail;
0145                 }
0146             }
0147             ndev--;
0148             break;
0149         }
0150 
0151         prev = pdev;
0152     }
0153 
0154     return ndev;
0155 fail:
0156     pci_dev_put(pdev);
0157     return -ENODEV;
0158 }
0159 
0160 static struct res_config skx_cfg = {
0161     .type           = SKX,
0162     .decs_did       = 0x2016,
0163     .busno_cfg_offset   = 0xcc,
0164 };
0165 
0166 static const struct x86_cpu_id skx_cpuids[] = {
0167     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg),
0168     { }
0169 };
0170 MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
0171 
0172 static bool skx_check_ecc(u32 mcmtr)
0173 {
0174     return !!GET_BITFIELD(mcmtr, 2, 2);
0175 }
0176 
0177 static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg)
0178 {
0179     struct skx_pvt *pvt = mci->pvt_info;
0180     u32 mtr, mcmtr, amap, mcddrtcfg;
0181     struct skx_imc *imc = pvt->imc;
0182     struct dimm_info *dimm;
0183     int i, j;
0184     int ndimms;
0185 
0186     /* Only the mcmtr on the first channel is effective */
0187     pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr);
0188 
0189     for (i = 0; i < SKX_NUM_CHANNELS; i++) {
0190         ndimms = 0;
0191         pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap);
0192         pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg);
0193         for (j = 0; j < SKX_NUM_DIMMS; j++) {
0194             dimm = edac_get_dimm(mci, i, j, 0);
0195             pci_read_config_dword(imc->chan[i].cdev,
0196                           0x80 + 4 * j, &mtr);
0197             if (IS_DIMM_PRESENT(mtr)) {
0198                 ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg);
0199             } else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) {
0200                 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
0201                                   EDAC_MOD_STR);
0202                 nvdimm_count++;
0203             }
0204         }
0205         if (ndimms && !skx_check_ecc(mcmtr)) {
0206             skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc);
0207             return -ENODEV;
0208         }
0209     }
0210 
0211     return 0;
0212 }
0213 
0214 #define SKX_MAX_SAD 24
0215 
0216 #define SKX_GET_SAD(d, i, reg)  \
0217     pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg))
0218 #define SKX_GET_ILV(d, i, reg)  \
0219     pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg))
0220 
0221 #define SKX_SAD_MOD3MODE(sad)   GET_BITFIELD((sad), 30, 31)
0222 #define SKX_SAD_MOD3(sad)   GET_BITFIELD((sad), 27, 27)
0223 #define SKX_SAD_LIMIT(sad)  (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26)
0224 #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6)
0225 #define SKX_SAD_ATTR(sad)   GET_BITFIELD((sad), 3, 4)
0226 #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2)
0227 #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0)
0228 
0229 #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0)
0230 #define SKX_ILV_TARGET(tgt) ((tgt) & 7)
0231 
0232 static void skx_show_retry_rd_err_log(struct decoded_addr *res,
0233                       char *msg, int len,
0234                       bool scrub_err)
0235 {
0236     u32 log0, log1, log2, log3, log4;
0237     u32 corr0, corr1, corr2, corr3;
0238     struct pci_dev *edev;
0239     int n;
0240 
0241     edev = res->dev->imc[res->imc].chan[res->channel].edev;
0242 
0243     pci_read_config_dword(edev, 0x154, &log0);
0244     pci_read_config_dword(edev, 0x148, &log1);
0245     pci_read_config_dword(edev, 0x150, &log2);
0246     pci_read_config_dword(edev, 0x15c, &log3);
0247     pci_read_config_dword(edev, 0x114, &log4);
0248 
0249     n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]",
0250              log0, log1, log2, log3, log4);
0251 
0252     pci_read_config_dword(edev, 0x104, &corr0);
0253     pci_read_config_dword(edev, 0x108, &corr1);
0254     pci_read_config_dword(edev, 0x10c, &corr2);
0255     pci_read_config_dword(edev, 0x110, &corr3);
0256 
0257     if (len - n > 0)
0258         snprintf(msg + n, len - n,
0259              " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
0260              corr0 & 0xffff, corr0 >> 16,
0261              corr1 & 0xffff, corr1 >> 16,
0262              corr2 & 0xffff, corr2 >> 16,
0263              corr3 & 0xffff, corr3 >> 16);
0264 }
0265 
0266 static bool skx_sad_decode(struct decoded_addr *res)
0267 {
0268     struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list);
0269     u64 addr = res->addr;
0270     int i, idx, tgt, lchan, shift;
0271     u32 sad, ilv;
0272     u64 limit, prev_limit;
0273     int remote = 0;
0274 
0275     /* Simple sanity check for I/O space or out of range */
0276     if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) {
0277         edac_dbg(0, "Address 0x%llx out of range\n", addr);
0278         return false;
0279     }
0280 
0281 restart:
0282     prev_limit = 0;
0283     for (i = 0; i < SKX_MAX_SAD; i++) {
0284         SKX_GET_SAD(d, i, sad);
0285         limit = SKX_SAD_LIMIT(sad);
0286         if (SKX_SAD_ENABLE(sad)) {
0287             if (addr >= prev_limit && addr <= limit)
0288                 goto sad_found;
0289         }
0290         prev_limit = limit + 1;
0291     }
0292     edac_dbg(0, "No SAD entry for 0x%llx\n", addr);
0293     return false;
0294 
0295 sad_found:
0296     SKX_GET_ILV(d, i, ilv);
0297 
0298     switch (SKX_SAD_INTERLEAVE(sad)) {
0299     case 0:
0300         idx = GET_BITFIELD(addr, 6, 8);
0301         break;
0302     case 1:
0303         idx = GET_BITFIELD(addr, 8, 10);
0304         break;
0305     case 2:
0306         idx = GET_BITFIELD(addr, 12, 14);
0307         break;
0308     case 3:
0309         idx = GET_BITFIELD(addr, 30, 32);
0310         break;
0311     }
0312 
0313     tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3);
0314 
0315     /* If point to another node, find it and start over */
0316     if (SKX_ILV_REMOTE(tgt)) {
0317         if (remote) {
0318             edac_dbg(0, "Double remote!\n");
0319             return false;
0320         }
0321         remote = 1;
0322         list_for_each_entry(d, skx_edac_list, list) {
0323             if (d->imc[0].src_id == SKX_ILV_TARGET(tgt))
0324                 goto restart;
0325         }
0326         edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt));
0327         return false;
0328     }
0329 
0330     if (SKX_SAD_MOD3(sad) == 0) {
0331         lchan = SKX_ILV_TARGET(tgt);
0332     } else {
0333         switch (SKX_SAD_MOD3MODE(sad)) {
0334         case 0:
0335             shift = 6;
0336             break;
0337         case 1:
0338             shift = 8;
0339             break;
0340         case 2:
0341             shift = 12;
0342             break;
0343         default:
0344             edac_dbg(0, "illegal mod3mode\n");
0345             return false;
0346         }
0347         switch (SKX_SAD_MOD3ASMOD2(sad)) {
0348         case 0:
0349             lchan = (addr >> shift) % 3;
0350             break;
0351         case 1:
0352             lchan = (addr >> shift) % 2;
0353             break;
0354         case 2:
0355             lchan = (addr >> shift) % 2;
0356             lchan = (lchan << 1) | !lchan;
0357             break;
0358         case 3:
0359             lchan = ((addr >> shift) % 2) << 1;
0360             break;
0361         }
0362         lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1);
0363     }
0364 
0365     res->dev = d;
0366     res->socket = d->imc[0].src_id;
0367     res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2);
0368     res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19);
0369 
0370     edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n",
0371          res->addr, res->socket, res->imc, res->channel);
0372     return true;
0373 }
0374 
0375 #define SKX_MAX_TAD 8
0376 
0377 #define SKX_GET_TADBASE(d, mc, i, reg)          \
0378     pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg))
0379 #define SKX_GET_TADWAYNESS(d, mc, i, reg)       \
0380     pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg))
0381 #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg)  \
0382     pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg))
0383 
0384 #define SKX_TAD_BASE(b)     ((u64)GET_BITFIELD((b), 12, 31) << 26)
0385 #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5)
0386 #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7)
0387 #define SKX_TAD_LIMIT(b)    (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26)
0388 #define SKX_TAD_OFFSET(b)   ((u64)GET_BITFIELD((b), 4, 23) << 26)
0389 #define SKX_TAD_SKTWAYS(b)  (1 << GET_BITFIELD((b), 10, 11))
0390 #define SKX_TAD_CHNWAYS(b)  (GET_BITFIELD((b), 8, 9) + 1)
0391 
0392 /* which bit used for both socket and channel interleave */
0393 static int skx_granularity[] = { 6, 8, 12, 30 };
0394 
0395 static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits)
0396 {
0397     addr >>= shift;
0398     addr /= ways;
0399     addr <<= shift;
0400 
0401     return addr | (lowbits & ((1ull << shift) - 1));
0402 }
0403 
0404 static bool skx_tad_decode(struct decoded_addr *res)
0405 {
0406     int i;
0407     u32 base, wayness, chnilvoffset;
0408     int skt_interleave_bit, chn_interleave_bit;
0409     u64 channel_addr;
0410 
0411     for (i = 0; i < SKX_MAX_TAD; i++) {
0412         SKX_GET_TADBASE(res->dev, res->imc, i, base);
0413         SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness);
0414         if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness))
0415             goto tad_found;
0416     }
0417     edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr);
0418     return false;
0419 
0420 tad_found:
0421     res->sktways = SKX_TAD_SKTWAYS(wayness);
0422     res->chanways = SKX_TAD_CHNWAYS(wayness);
0423     skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)];
0424     chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)];
0425 
0426     SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset);
0427     channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset);
0428 
0429     if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) {
0430         /* Must handle channel first, then socket */
0431         channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
0432                          res->chanways, channel_addr);
0433         channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
0434                          res->sktways, channel_addr);
0435     } else {
0436         /* Handle socket then channel. Preserve low bits from original address */
0437         channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit,
0438                          res->sktways, res->addr);
0439         channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit,
0440                          res->chanways, res->addr);
0441     }
0442 
0443     res->chan_addr = channel_addr;
0444 
0445     edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n",
0446          res->addr, res->chan_addr, res->sktways, res->chanways);
0447     return true;
0448 }
0449 
0450 #define SKX_MAX_RIR 4
0451 
0452 #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg)       \
0453     pci_read_config_dword((d)->imc[mc].chan[ch].cdev,   \
0454                   0x108 + 4 * (i), &(reg))
0455 #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg)      \
0456     pci_read_config_dword((d)->imc[mc].chan[ch].cdev,   \
0457                   0x120 + 16 * (idx) + 4 * (i), &(reg))
0458 
0459 #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31)
0460 #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29)
0461 #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29))
0462 #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19)
0463 #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26))
0464 
0465 static bool skx_rir_decode(struct decoded_addr *res)
0466 {
0467     int i, idx, chan_rank;
0468     int shift;
0469     u32 rirway, rirlv;
0470     u64 rank_addr, prev_limit = 0, limit;
0471 
0472     if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg)
0473         shift = 6;
0474     else
0475         shift = 13;
0476 
0477     for (i = 0; i < SKX_MAX_RIR; i++) {
0478         SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway);
0479         limit = SKX_RIR_LIMIT(rirway);
0480         if (SKX_RIR_VALID(rirway)) {
0481             if (prev_limit <= res->chan_addr &&
0482                 res->chan_addr <= limit)
0483                 goto rir_found;
0484         }
0485         prev_limit = limit;
0486     }
0487     edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr);
0488     return false;
0489 
0490 rir_found:
0491     rank_addr = res->chan_addr >> shift;
0492     rank_addr /= SKX_RIR_WAYS(rirway);
0493     rank_addr <<= shift;
0494     rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0);
0495 
0496     res->rank_address = rank_addr;
0497     idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway);
0498 
0499     SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv);
0500     res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv);
0501     chan_rank = SKX_RIR_CHAN_RANK(rirlv);
0502     res->channel_rank = chan_rank;
0503     res->dimm = chan_rank / 4;
0504     res->rank = chan_rank % 4;
0505 
0506     edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n",
0507          res->addr, res->dimm, res->rank,
0508          res->channel_rank, res->rank_address);
0509     return true;
0510 }
0511 
0512 static u8 skx_close_row[] = {
0513     15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33
0514 };
0515 
0516 static u8 skx_close_column[] = {
0517     3, 4, 5, 14, 19, 23, 24, 25, 26, 27
0518 };
0519 
0520 static u8 skx_open_row[] = {
0521     14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33
0522 };
0523 
0524 static u8 skx_open_column[] = {
0525     3, 4, 5, 6, 7, 8, 9, 10, 11, 12
0526 };
0527 
0528 static u8 skx_open_fine_column[] = {
0529     3, 4, 5, 7, 8, 9, 10, 11, 12, 13
0530 };
0531 
0532 static int skx_bits(u64 addr, int nbits, u8 *bits)
0533 {
0534     int i, res = 0;
0535 
0536     for (i = 0; i < nbits; i++)
0537         res |= ((addr >> bits[i]) & 1) << i;
0538     return res;
0539 }
0540 
0541 static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1)
0542 {
0543     int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1);
0544 
0545     if (do_xor)
0546         ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1);
0547 
0548     return ret;
0549 }
0550 
0551 static bool skx_mad_decode(struct decoded_addr *r)
0552 {
0553     struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm];
0554     int bg0 = dimm->fine_grain_bank ? 6 : 13;
0555 
0556     if (dimm->close_pg) {
0557         r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row);
0558         r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column);
0559         r->column |= 0x400; /* C10 is autoprecharge, always set */
0560         r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28);
0561         r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21);
0562     } else {
0563         r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row);
0564         if (dimm->fine_grain_bank)
0565             r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column);
0566         else
0567             r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column);
0568         r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23);
0569         r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21);
0570     }
0571     r->row &= (1u << dimm->rowbits) - 1;
0572 
0573     edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n",
0574          r->addr, r->row, r->column, r->bank_address,
0575          r->bank_group);
0576     return true;
0577 }
0578 
0579 static bool skx_decode(struct decoded_addr *res)
0580 {
0581     return skx_sad_decode(res) && skx_tad_decode(res) &&
0582         skx_rir_decode(res) && skx_mad_decode(res);
0583 }
0584 
0585 static struct notifier_block skx_mce_dec = {
0586     .notifier_call  = skx_mce_check_error,
0587     .priority   = MCE_PRIO_EDAC,
0588 };
0589 
0590 #ifdef CONFIG_EDAC_DEBUG
0591 /*
0592  * Debug feature.
0593  * Exercise the address decode logic by writing an address to
0594  * /sys/kernel/debug/edac/skx_test/addr.
0595  */
0596 static struct dentry *skx_test;
0597 
0598 static int debugfs_u64_set(void *data, u64 val)
0599 {
0600     struct mce m;
0601 
0602     pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
0603 
0604     memset(&m, 0, sizeof(m));
0605     /* ADDRV + MemRd + Unknown channel */
0606     m.status = MCI_STATUS_ADDRV + 0x90;
0607     /* One corrected error */
0608     m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
0609     m.addr = val;
0610     skx_mce_check_error(NULL, 0, &m);
0611 
0612     return 0;
0613 }
0614 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
0615 
0616 static void setup_skx_debug(void)
0617 {
0618     skx_test = edac_debugfs_create_dir("skx_test");
0619     if (!skx_test)
0620         return;
0621 
0622     if (!edac_debugfs_create_file("addr", 0200, skx_test,
0623                       NULL, &fops_u64_wo)) {
0624         debugfs_remove(skx_test);
0625         skx_test = NULL;
0626     }
0627 }
0628 
0629 static void teardown_skx_debug(void)
0630 {
0631     debugfs_remove_recursive(skx_test);
0632 }
0633 #else
0634 static inline void setup_skx_debug(void) {}
0635 static inline void teardown_skx_debug(void) {}
0636 #endif /*CONFIG_EDAC_DEBUG*/
0637 
0638 /*
0639  * skx_init:
0640  *  make sure we are running on the correct cpu model
0641  *  search for all the devices we need
0642  *  check which DIMMs are present.
0643  */
0644 static int __init skx_init(void)
0645 {
0646     const struct x86_cpu_id *id;
0647     struct res_config *cfg;
0648     const struct munit *m;
0649     const char *owner;
0650     int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8};
0651     u8 mc = 0, src_id, node_id;
0652     struct skx_dev *d;
0653 
0654     edac_dbg(2, "\n");
0655 
0656     owner = edac_get_owner();
0657     if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
0658         return -EBUSY;
0659 
0660     if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
0661         return -ENODEV;
0662 
0663     id = x86_match_cpu(skx_cpuids);
0664     if (!id)
0665         return -ENODEV;
0666 
0667     cfg = (struct res_config *)id->driver_data;
0668 
0669     rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm);
0670     if (rc)
0671         return rc;
0672 
0673     rc = skx_get_all_bus_mappings(cfg, &skx_edac_list);
0674     if (rc < 0)
0675         goto fail;
0676     if (rc == 0) {
0677         edac_dbg(2, "No memory controllers found\n");
0678         return -ENODEV;
0679     }
0680     skx_num_sockets = rc;
0681 
0682     for (m = skx_all_munits; m->did; m++) {
0683         rc = get_all_munits(m);
0684         if (rc < 0)
0685             goto fail;
0686         if (rc != m->per_socket * skx_num_sockets) {
0687             edac_dbg(2, "Expected %d, got %d of 0x%x\n",
0688                  m->per_socket * skx_num_sockets, rc, m->did);
0689             rc = -ENODEV;
0690             goto fail;
0691         }
0692     }
0693 
0694     list_for_each_entry(d, skx_edac_list, list) {
0695         rc = skx_get_src_id(d, 0xf0, &src_id);
0696         if (rc < 0)
0697             goto fail;
0698         rc = skx_get_node_id(d, &node_id);
0699         if (rc < 0)
0700             goto fail;
0701         edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id);
0702         for (i = 0; i < SKX_NUM_IMC; i++) {
0703             d->imc[i].mc = mc++;
0704             d->imc[i].lmc = i;
0705             d->imc[i].src_id = src_id;
0706             d->imc[i].node_id = node_id;
0707             rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev,
0708                           "Skylake Socket", EDAC_MOD_STR,
0709                           skx_get_dimm_config, cfg);
0710             if (rc < 0)
0711                 goto fail;
0712         }
0713     }
0714 
0715     skx_set_decode(skx_decode, skx_show_retry_rd_err_log);
0716 
0717     if (nvdimm_count && skx_adxl_get() == -ENODEV)
0718         skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n");
0719 
0720     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0721     opstate_init();
0722 
0723     setup_skx_debug();
0724 
0725     mce_register_decode_chain(&skx_mce_dec);
0726 
0727     return 0;
0728 fail:
0729     skx_remove();
0730     return rc;
0731 }
0732 
0733 static void __exit skx_exit(void)
0734 {
0735     edac_dbg(2, "\n");
0736     mce_unregister_decode_chain(&skx_mce_dec);
0737     teardown_skx_debug();
0738     if (nvdimm_count)
0739         skx_adxl_put();
0740     skx_remove();
0741 }
0742 
0743 module_init(skx_init);
0744 module_exit(skx_exit);
0745 
0746 module_param(edac_op_state, int, 0444);
0747 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
0748 
0749 MODULE_LICENSE("GPL v2");
0750 MODULE_AUTHOR("Tony Luck");
0751 MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
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