drivers/edac/r82600_edac.c

0001 /*
0002  * Radisys 82600 Embedded chipset Memory Controller kernel module
0003  * (C) 2005 EADS Astrium
0004  * This file may be distributed under the terms of the
0005  * GNU General Public License.
0006  *
0007  * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
0008  * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
0009  *
0010  * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
0011  *
0012  * Written with reference to 82600 High Integration Dual PCI System
0013  * Controller Data Book:
0014  * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
0015  * references to this document given in []
0016  */
0017
0018 #include <linux/module.h>
0019 #include <linux/init.h>
0020 #include <linux/pci.h>
0021 #include <linux/pci_ids.h>
0022 #include <linux/edac.h>
0023 #include "edac_module.h"
0024
0025 #define EDAC_MOD_STR    "r82600_edac"
0026
0027 #define r82600_printk(level, fmt, arg...) \
0028     edac_printk(level, "r82600", fmt, ##arg)
0029
0030 #define r82600_mc_printk(mci, level, fmt, arg...) \
0031     edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
0032
0033 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
0034  * supports up to four banks of memory. The four banks can support a mix of
0035  * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
0036  * each of which can be any size from 16MB to 512MB. Both registered (control
0037  * signals buffered) and unbuffered DIMM types are supported. Mixing of
0038  * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
0039  * is not allowed. The 82600 SDRAM interface operates at the same frequency as
0040  * the CPU bus, 66MHz, 100MHz or 133MHz."
0041  */
0042
0043 #define R82600_NR_CSROWS 4
0044 #define R82600_NR_CHANS  1
0045 #define R82600_NR_DIMMS  4
0046
0047 #define R82600_BRIDGE_ID  0x8200
0048
0049 /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
0050 #define R82600_DRAMC    0x57    /* Various SDRAM related control bits
0051                  * all bits are R/W
0052                  *
0053                  * 7    SDRAM ISA Hole Enable
0054                  * 6    Flash Page Mode Enable
0055                  * 5    ECC Enable: 1=ECC 0=noECC
0056                  * 4    DRAM DIMM Type: 1=
0057                  * 3    BIOS Alias Disable
0058                  * 2    SDRAM BIOS Flash Write Enable
0059                  * 1:0  SDRAM Refresh Rate: 00=Disabled
0060                  *          01=7.8usec (256Mbit SDRAMs)
0061                  *          10=15.6us 11=125usec
0062                  */
0063
0064 #define R82600_SDRAMC   0x76    /* "SDRAM Control Register"
0065                  * More SDRAM related control bits
0066                  * all bits are R/W
0067                  *
0068                  * 15:8 Reserved.
0069                  *
0070                  * 7:5  Special SDRAM Mode Select
0071                  *
0072                  * 4    Force ECC
0073                  *
0074                  *        1=Drive ECC bits to 0 during
0075                  *          write cycles (i.e. ECC test mode)
0076                  *
0077                  *        0=Normal ECC functioning
0078                  *
0079                  * 3    Enhanced Paging Enable
0080                  *
0081                  * 2    CAS# Latency 0=3clks 1=2clks
0082                  *
0083                  * 1    RAS# to CAS# Delay 0=3 1=2
0084                  *
0085                  * 0    RAS# Precharge     0=3 1=2
0086                  */
0087
0088 #define R82600_EAP  0x80    /* ECC Error Address Pointer Register
0089                  *
0090                  * 31    Disable Hardware Scrubbing (RW)
0091                  *        0=Scrub on corrected read
0092                  *        1=Don't scrub on corrected read
0093                  *
0094                  * 30:12 Error Address Pointer (RO)
0095                  *        Upper 19 bits of error address
0096                  *
0097                  * 11:4  Syndrome Bits (RO)
0098                  *
0099                  * 3     BSERR# on multibit error (RW)
0100                  *        1=enable 0=disable
0101                  *
0102                  * 2     NMI on Single Bit Eror (RW)
0103                  *        1=NMI triggered by SBE n.b. other
0104                  *          prerequeists
0105                  *        0=NMI not triggered
0106                  *
0107                  * 1     MBE (R/WC)
0108                  *        read 1=MBE at EAP (see above)
0109                  *        read 0=no MBE, or SBE occurred first
0110                  *        write 1=Clear MBE status (must also
0111                  *          clear SBE)
0112                  *        write 0=NOP
0113                  *
0114                  * 1     SBE (R/WC)
0115                  *        read 1=SBE at EAP (see above)
0116                  *        read 0=no SBE, or MBE occurred first
0117                  *        write 1=Clear SBE status (must also
0118                  *          clear MBE)
0119                  *        write 0=NOP
0120                  */
0121
0122 #define R82600_DRBA 0x60    /* + 0x60..0x63 SDRAM Row Boundary Address
0123                  *  Registers
0124                  *
0125                  * 7:0  Address lines 30:24 - upper limit of
0126                  * each row [p57]
0127                  */
0128
0129 struct r82600_error_info {
0130     u32 eapr;
0131 };
0132
0133 static bool disable_hardware_scrub;
0134
0135 static struct edac_pci_ctl_info *r82600_pci;
0136
0137 static void r82600_get_error_info(struct mem_ctl_info *mci,
0138                 struct r82600_error_info *info)
0139 {
0140     struct pci_dev *pdev;
0141
0142     pdev = to_pci_dev(mci->pdev);
0143     pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
0144
0145     if (info->eapr & BIT(0))
0146         /* Clear error to allow next error to be reported [p.62] */
0147         pci_write_bits32(pdev, R82600_EAP,
0148                  ((u32) BIT(0) & (u32) BIT(1)),
0149                  ((u32) BIT(0) & (u32) BIT(1)));
0150
0151     if (info->eapr & BIT(1))
0152         /* Clear error to allow next error to be reported [p.62] */
0153         pci_write_bits32(pdev, R82600_EAP,
0154                  ((u32) BIT(0) & (u32) BIT(1)),
0155                  ((u32) BIT(0) & (u32) BIT(1)));
0156 }
0157
0158 static int r82600_process_error_info(struct mem_ctl_info *mci,
0159                 struct r82600_error_info *info,
0160                 int handle_errors)
0161 {
0162     int error_found;
0163     u32 eapaddr, page;
0164     u32 syndrome;
0165
0166     error_found = 0;
0167
0168     /* bits 30:12 store the upper 19 bits of the 32 bit error address */
0169     eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
0170     /* Syndrome in bits 11:4 [p.62]       */
0171     syndrome = (info->eapr >> 4) & 0xFF;
0172
0173     /* the R82600 reports at less than page *
0174      * granularity (upper 19 bits only)     */
0175     page = eapaddr >> PAGE_SHIFT;
0176
0177     if (info->eapr & BIT(0)) {  /* CE? */
0178         error_found = 1;
0179
0180         if (handle_errors)
0181             edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0182                          page, 0, syndrome,
0183                          edac_mc_find_csrow_by_page(mci, page),
0184                          0, -1,
0185                          mci->ctl_name, "");
0186     }
0187
0188     if (info->eapr & BIT(1)) {  /* UE? */
0189         error_found = 1;
0190
0191         if (handle_errors)
0192             /* 82600 doesn't give enough info */
0193             edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0194                          page, 0, 0,
0195                          edac_mc_find_csrow_by_page(mci, page),
0196                          0, -1,
0197                          mci->ctl_name, "");
0198     }
0199
0200     return error_found;
0201 }
0202
0203 static void r82600_check(struct mem_ctl_info *mci)
0204 {
0205     struct r82600_error_info info;
0206
0207     r82600_get_error_info(mci, &info);
0208     r82600_process_error_info(mci, &info, 1);
0209 }
0210
0211 static inline int ecc_enabled(u8 dramcr)
0212 {
0213     return dramcr & BIT(5);
0214 }
0215
0216 static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
0217             u8 dramcr)
0218 {
0219     struct csrow_info *csrow;
0220     struct dimm_info *dimm;
0221     int index;
0222     u8 drbar;       /* SDRAM Row Boundary Address Register */
0223     u32 row_high_limit, row_high_limit_last;
0224     u32 reg_sdram, ecc_on, row_base;
0225
0226     ecc_on = ecc_enabled(dramcr);
0227     reg_sdram = dramcr & BIT(4);
0228     row_high_limit_last = 0;
0229
0230     for (index = 0; index < mci->nr_csrows; index++) {
0231         csrow = mci->csrows[index];
0232         dimm = csrow->channels[0]->dimm;
0233
0234         /* find the DRAM Chip Select Base address and mask */
0235         pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
0236
0237         edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
0238
0239         row_high_limit = ((u32) drbar << 24);
0240 /*      row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
0241
0242         edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
0243              index, row_high_limit, row_high_limit_last);
0244
0245         /* Empty row [p.57] */
0246         if (row_high_limit == row_high_limit_last)
0247             continue;
0248
0249         row_base = row_high_limit_last;
0250
0251         csrow->first_page = row_base >> PAGE_SHIFT;
0252         csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
0253
0254         dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
0255         /* Error address is top 19 bits - so granularity is      *
0256          * 14 bits                                               */
0257         dimm->grain = 1 << 14;
0258         dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
0259         /* FIXME - check that this is unknowable with this chipset */
0260         dimm->dtype = DEV_UNKNOWN;
0261
0262         /* Mode is global on 82600 */
0263         dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
0264         row_high_limit_last = row_high_limit;
0265     }
0266 }
0267
0268 static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
0269 {
0270     struct mem_ctl_info *mci;
0271     struct edac_mc_layer layers[2];
0272     u8 dramcr;
0273     u32 eapr;
0274     u32 scrub_disabled;
0275     u32 sdram_refresh_rate;
0276     struct r82600_error_info discard;
0277
0278     edac_dbg(0, "\n");
0279     pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
0280     pci_read_config_dword(pdev, R82600_EAP, &eapr);
0281     scrub_disabled = eapr & BIT(31);
0282     sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
0283     edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
0284     edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
0285     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0286     layers[0].size = R82600_NR_CSROWS;
0287     layers[0].is_virt_csrow = true;
0288     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0289     layers[1].size = R82600_NR_CHANS;
0290     layers[1].is_virt_csrow = false;
0291     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
0292     if (mci == NULL)
0293         return -ENOMEM;
0294
0295     edac_dbg(0, "mci = %p\n", mci);
0296     mci->pdev = &pdev->dev;
0297     mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
0298     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
0299     /* FIXME try to work out if the chip leads have been used for COM2
0300      * instead on this board? [MA6?] MAYBE:
0301      */
0302
0303     /* On the R82600, the pins for memory bits 72:65 - i.e. the   *
0304      * EC bits are shared with the pins for COM2 (!), so if COM2  *
0305      * is enabled, we assume COM2 is wired up, and thus no EDAC   *
0306      * is possible.                                               */
0307     mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
0308
0309     if (ecc_enabled(dramcr)) {
0310         if (scrub_disabled)
0311             edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
0312                  mci, eapr);
0313     } else
0314         mci->edac_cap = EDAC_FLAG_NONE;
0315
0316     mci->mod_name = EDAC_MOD_STR;
0317     mci->ctl_name = "R82600";
0318     mci->dev_name = pci_name(pdev);
0319     mci->edac_check = r82600_check;
0320     mci->ctl_page_to_phys = NULL;
0321     r82600_init_csrows(mci, pdev, dramcr);
0322     r82600_get_error_info(mci, &discard);   /* clear counters */
0323
0324     /* Here we assume that we will never see multiple instances of this
0325      * type of memory controller.  The ID is therefore hardcoded to 0.
0326      */
0327     if (edac_mc_add_mc(mci)) {
0328         edac_dbg(3, "failed edac_mc_add_mc()\n");
0329         goto fail;
0330     }
0331
0332     /* get this far and it's successful */
0333
0334     if (disable_hardware_scrub) {
0335         edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
0336         pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
0337     }
0338
0339     /* allocating generic PCI control info */
0340     r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
0341     if (!r82600_pci) {
0342         printk(KERN_WARNING
0343             "%s(): Unable to create PCI control\n",
0344             __func__);
0345         printk(KERN_WARNING
0346             "%s(): PCI error report via EDAC not setup\n",
0347             __func__);
0348     }
0349
0350     edac_dbg(3, "success\n");
0351     return 0;
0352
0353 fail:
0354     edac_mc_free(mci);
0355     return -ENODEV;
0356 }
0357
0358 /* returns count (>= 0), or negative on error */
0359 static int r82600_init_one(struct pci_dev *pdev,
0360                const struct pci_device_id *ent)
0361 {
0362     edac_dbg(0, "\n");
0363
0364     /* don't need to call pci_enable_device() */
0365     return r82600_probe1(pdev, ent->driver_data);
0366 }
0367
0368 static void r82600_remove_one(struct pci_dev *pdev)
0369 {
0370     struct mem_ctl_info *mci;
0371
0372     edac_dbg(0, "\n");
0373
0374     if (r82600_pci)
0375         edac_pci_release_generic_ctl(r82600_pci);
0376
0377     if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0378         return;
0379
0380     edac_mc_free(mci);
0381 }
0382
0383 static const struct pci_device_id r82600_pci_tbl[] = {
0384     {
0385      PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
0386      },
0387     {
0388      0,
0389      }          /* 0 terminated list. */
0390 };
0391
0392 MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
0393
0394 static struct pci_driver r82600_driver = {
0395     .name = EDAC_MOD_STR,
0396     .probe = r82600_init_one,
0397     .remove = r82600_remove_one,
0398     .id_table = r82600_pci_tbl,
0399 };
0400
0401 static int __init r82600_init(void)
0402 {
0403        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0404        opstate_init();
0405
0406     return pci_register_driver(&r82600_driver);
0407 }
0408
0409 static void __exit r82600_exit(void)
0410 {
0411     pci_unregister_driver(&r82600_driver);
0412 }
0413
0414 module_init(r82600_init);
0415 module_exit(r82600_exit);
0416
0417 MODULE_LICENSE("GPL");
0418 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
0419         "on behalf of EADS Astrium");
0420 MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
0421
0422 module_param(disable_hardware_scrub, bool, 0644);
0423 MODULE_PARM_DESC(disable_hardware_scrub,
0424          "If set, disable the chipset's automatic scrub for CEs");
0425
0426 module_param(edac_op_state, int, 0444);
0427 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");