drivers/edac/ppc4xx_edac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2008 Nuovation System Designs, LLC
0004  *   Grant Erickson <gerickson@nuovations.com>
0005  *
0006  * This file defines processor mnemonics for accessing and managing
0007  * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
0008  * 440SPe, 460EX, 460GT and 460SX.
0009  */
0010
0011 #ifndef __PPC4XX_EDAC_H
0012 #define __PPC4XX_EDAC_H
0013
0014 #include <linux/types.h>
0015
0016 /*
0017  * Macro for generating register field mnemonics
0018  */
0019 #define PPC_REG_BITS            32
0020 #define PPC_REG_VAL(bit, val)       ((val) << ((PPC_REG_BITS - 1) - (bit)))
0021 #define PPC_REG_DECODE(bit, val)    ((val) >> ((PPC_REG_BITS - 1) - (bit)))
0022
0023 /*
0024  * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
0025  * relevant to ECC)
0026  */
0027 #define SDRAM_BESR          0x00    /* Error status (read/clear) */
0028 #define SDRAM_BESRT         0x01    /* Error statuss (test/set)  */
0029 #define SDRAM_BEARL         0x02    /* Error address low         */
0030 #define SDRAM_BEARH         0x03    /* Error address high        */
0031 #define SDRAM_WMIRQ         0x06    /* Write master (read/clear) */
0032 #define SDRAM_WMIRQT            0x07    /* Write master (test/set)   */
0033 #define SDRAM_MCOPT1            0x20    /* Controller options 1      */
0034 #define SDRAM_MBXCF_BASE        0x40    /* Bank n configuration base */
0035 #define SDRAM_MBXCF(n)          (SDRAM_MBXCF_BASE + (4 * (n)))
0036 #define SDRAM_MB0CF         SDRAM_MBXCF(0)
0037 #define SDRAM_MB1CF         SDRAM_MBXCF(1)
0038 #define SDRAM_MB2CF         SDRAM_MBXCF(2)
0039 #define SDRAM_MB3CF         SDRAM_MBXCF(3)
0040 #define SDRAM_ECCCR         0x98    /* ECC error status      */
0041 #define SDRAM_ECCES         SDRAM_ECCCR
0042
0043 /*
0044  * PLB Master IDs
0045  */
0046 #define SDRAM_PLB_M0ID_FIRST        0
0047 #define SDRAM_PLB_M0ID_ICU      SDRAM_PLB_M0ID_FIRST
0048 #define SDRAM_PLB_M0ID_PCIE0        1
0049 #define SDRAM_PLB_M0ID_PCIE1        2
0050 #define SDRAM_PLB_M0ID_DMA      3
0051 #define SDRAM_PLB_M0ID_DCU      4
0052 #define SDRAM_PLB_M0ID_OPB      5
0053 #define SDRAM_PLB_M0ID_MAL      6
0054 #define SDRAM_PLB_M0ID_SEC      7
0055 #define SDRAM_PLB_M0ID_AHB      8
0056 #define SDRAM_PLB_M0ID_LAST     SDRAM_PLB_M0ID_AHB
0057 #define SDRAM_PLB_M0ID_COUNT        (SDRAM_PLB_M0ID_LAST - \
0058                      SDRAM_PLB_M0ID_FIRST + 1)
0059
0060 /*
0061  * Memory Controller Bus Error Status Register
0062  */
0063 #define SDRAM_BESR_MASK         PPC_REG_VAL(7, 0xFF)
0064 #define SDRAM_BESR_M0ID_MASK        PPC_REG_VAL(3, 0xF)
0065 #define SDRAM_BESR_M0ID_DECODE(n)   PPC_REG_DECODE(3, n)
0066 #define SDRAM_BESR_M0ID_ICU     PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
0067 #define SDRAM_BESR_M0ID_PCIE0       PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
0068 #define SDRAM_BESR_M0ID_PCIE1       PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
0069 #define SDRAM_BESR_M0ID_DMA     PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
0070 #define SDRAM_BESR_M0ID_DCU     PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
0071 #define SDRAM_BESR_M0ID_OPB     PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
0072 #define SDRAM_BESR_M0ID_MAL     PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
0073 #define SDRAM_BESR_M0ID_SEC     PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
0074 #define SDRAM_BESR_M0ID_AHB     PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
0075 #define SDRAM_BESR_M0ET_MASK        PPC_REG_VAL(6, 0x7)
0076 #define SDRAM_BESR_M0ET_NONE        PPC_REG_VAL(6, 0)
0077 #define SDRAM_BESR_M0ET_ECC     PPC_REG_VAL(6, 1)
0078 #define SDRAM_BESR_M0RW_MASK        PPC_REG_VAL(7, 1)
0079 #define SDRAM_BESR_M0RW_WRITE       PPC_REG_VAL(7, 0)
0080 #define SDRAM_BESR_M0RW_READ        PPC_REG_VAL(7, 1)
0081
0082 /*
0083  * Memory Controller PLB Write Master Interrupt Register
0084  */
0085 #define SDRAM_WMIRQ_MASK        PPC_REG_VAL(8, 0x1FF)
0086 #define SDRAM_WMIRQ_ENCODE(id)      PPC_REG_VAL((id % \
0087                              SDRAM_PLB_M0ID_COUNT), 1)
0088 #define SDRAM_WMIRQ_ICU         PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
0089 #define SDRAM_WMIRQ_PCIE0       PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
0090 #define SDRAM_WMIRQ_PCIE1       PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
0091 #define SDRAM_WMIRQ_DMA         PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
0092 #define SDRAM_WMIRQ_DCU         PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
0093 #define SDRAM_WMIRQ_OPB         PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
0094 #define SDRAM_WMIRQ_MAL         PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
0095 #define SDRAM_WMIRQ_SEC         PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
0096 #define SDRAM_WMIRQ_AHB         PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
0097
0098 /*
0099  * Memory Controller Options 1 Register
0100  */
0101 #define SDRAM_MCOPT1_MCHK_MASK      PPC_REG_VAL(3, 0x3)  /* ECC mask         */
0102 #define SDRAM_MCOPT1_MCHK_NON       PPC_REG_VAL(3, 0x0)  /* No ECC gen       */
0103 #define SDRAM_MCOPT1_MCHK_GEN       PPC_REG_VAL(3, 0x2)  /* ECC gen      */
0104 #define SDRAM_MCOPT1_MCHK_CHK       PPC_REG_VAL(3, 0x1)  /* ECC gen and chk  */
0105 #define SDRAM_MCOPT1_MCHK_CHK_REP   PPC_REG_VAL(3, 0x3)  /* ECC gen/chk/rpt  */
0106 #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
0107 #define SDRAM_MCOPT1_RDEN_MASK      PPC_REG_VAL(4, 0x1)  /* Rgstrd DIMM mask */
0108 #define SDRAM_MCOPT1_RDEN       PPC_REG_VAL(4, 0x1)  /* Rgstrd DIMM enbl */
0109 #define SDRAM_MCOPT1_WDTH_MASK      PPC_REG_VAL(7, 0x1)  /* Width mask       */
0110 #define SDRAM_MCOPT1_WDTH_32        PPC_REG_VAL(7, 0x0)  /* 32 bits      */
0111 #define SDRAM_MCOPT1_WDTH_16        PPC_REG_VAL(7, 0x1)  /* 16 bits      */
0112 #define SDRAM_MCOPT1_DDR_TYPE_MASK  PPC_REG_VAL(11, 0x1) /* DDR type mask    */
0113 #define SDRAM_MCOPT1_DDR1_TYPE      PPC_REG_VAL(11, 0x0) /* DDR1 type        */
0114 #define SDRAM_MCOPT1_DDR2_TYPE      PPC_REG_VAL(11, 0x1) /* DDR2 type        */
0115
0116 /*
0117  * Memory Bank 0 - n Configuration Register
0118  */
0119 #define SDRAM_MBCF_BA_MASK      PPC_REG_VAL(12, 0x1FFF)
0120 #define SDRAM_MBCF_SZ_MASK      PPC_REG_VAL(19, 0xF)
0121 #define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf)
0122 #define SDRAM_MBCF_SZ_4MB       PPC_REG_VAL(19, 0x0)
0123 #define SDRAM_MBCF_SZ_8MB       PPC_REG_VAL(19, 0x1)
0124 #define SDRAM_MBCF_SZ_16MB      PPC_REG_VAL(19, 0x2)
0125 #define SDRAM_MBCF_SZ_32MB      PPC_REG_VAL(19, 0x3)
0126 #define SDRAM_MBCF_SZ_64MB      PPC_REG_VAL(19, 0x4)
0127 #define SDRAM_MBCF_SZ_128MB     PPC_REG_VAL(19, 0x5)
0128 #define SDRAM_MBCF_SZ_256MB     PPC_REG_VAL(19, 0x6)
0129 #define SDRAM_MBCF_SZ_512MB     PPC_REG_VAL(19, 0x7)
0130 #define SDRAM_MBCF_SZ_1GB       PPC_REG_VAL(19, 0x8)
0131 #define SDRAM_MBCF_SZ_2GB       PPC_REG_VAL(19, 0x9)
0132 #define SDRAM_MBCF_SZ_4GB       PPC_REG_VAL(19, 0xA)
0133 #define SDRAM_MBCF_SZ_8GB       PPC_REG_VAL(19, 0xB)
0134 #define SDRAM_MBCF_AM_MASK      PPC_REG_VAL(23, 0xF)
0135 #define SDRAM_MBCF_AM_MODE0     PPC_REG_VAL(23, 0x0)
0136 #define SDRAM_MBCF_AM_MODE1     PPC_REG_VAL(23, 0x1)
0137 #define SDRAM_MBCF_AM_MODE2     PPC_REG_VAL(23, 0x2)
0138 #define SDRAM_MBCF_AM_MODE3     PPC_REG_VAL(23, 0x3)
0139 #define SDRAM_MBCF_AM_MODE4     PPC_REG_VAL(23, 0x4)
0140 #define SDRAM_MBCF_AM_MODE5     PPC_REG_VAL(23, 0x5)
0141 #define SDRAM_MBCF_AM_MODE6     PPC_REG_VAL(23, 0x6)
0142 #define SDRAM_MBCF_AM_MODE7     PPC_REG_VAL(23, 0x7)
0143 #define SDRAM_MBCF_AM_MODE8     PPC_REG_VAL(23, 0x8)
0144 #define SDRAM_MBCF_AM_MODE9     PPC_REG_VAL(23, 0x9)
0145 #define SDRAM_MBCF_BE_MASK      PPC_REG_VAL(31, 0x1)
0146 #define SDRAM_MBCF_BE_DISABLE       PPC_REG_VAL(31, 0x0)
0147 #define SDRAM_MBCF_BE_ENABLE        PPC_REG_VAL(31, 0x1)
0148
0149 /*
0150  * ECC Error Status
0151  */
0152 #define SDRAM_ECCES_MASK        PPC_REG_VAL(21, 0x3FFFFF)
0153 #define SDRAM_ECCES_BNCE_MASK       PPC_REG_VAL(15, 0xFFFF)
0154 #define SDRAM_ECCES_BNCE_ENCODE(lane)   PPC_REG_VAL(((lane) & 0xF), 1)
0155 #define SDRAM_ECCES_CKBER_MASK      PPC_REG_VAL(17, 0x3)
0156 #define SDRAM_ECCES_CKBER_NONE      PPC_REG_VAL(17, 0)
0157 #define SDRAM_ECCES_CKBER_16_ECC_0_3    PPC_REG_VAL(17, 2)
0158 #define SDRAM_ECCES_CKBER_32_ECC_0_3    PPC_REG_VAL(17, 1)
0159 #define SDRAM_ECCES_CKBER_32_ECC_4_8    PPC_REG_VAL(17, 2)
0160 #define SDRAM_ECCES_CKBER_32_ECC_0_8    PPC_REG_VAL(17, 3)
0161 #define SDRAM_ECCES_CE          PPC_REG_VAL(18, 1)
0162 #define SDRAM_ECCES_UE          PPC_REG_VAL(19, 1)
0163 #define SDRAM_ECCES_BKNER_MASK      PPC_REG_VAL(21, 0x3)
0164 #define SDRAM_ECCES_BK0ER       PPC_REG_VAL(20, 1)
0165 #define SDRAM_ECCES_BK1ER       PPC_REG_VAL(21, 1)
0166
0167 #endif /* __PPC4XX_EDAC_H */