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0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2009 Wind River Systems,
0007  *   written by Ralf Baechle <ralf@linux-mips.org>
0008  *
0009  * Copyright (c) 2013 by Cisco Systems, Inc.
0010  * All rights reserved.
0011  */
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/slab.h>
0015 #include <linux/io.h>
0016 #include <linux/edac.h>
0017 #include <linux/ctype.h>
0018 
0019 #include <asm/octeon/octeon.h>
0020 #include <asm/octeon/cvmx-lmcx-defs.h>
0021 
0022 #include "edac_module.h"
0023 
0024 #define OCTEON_MAX_MC 4
0025 
0026 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
0027 
0028 struct octeon_lmc_pvt {
0029     unsigned long inject;
0030     unsigned long error_type;
0031     unsigned long dimm;
0032     unsigned long rank;
0033     unsigned long bank;
0034     unsigned long row;
0035     unsigned long col;
0036 };
0037 
0038 static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
0039 {
0040     union cvmx_lmcx_mem_cfg0 cfg0;
0041     bool do_clear = false;
0042     char msg[64];
0043 
0044     cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));
0045     if (cfg0.s.sec_err || cfg0.s.ded_err) {
0046         union cvmx_lmcx_fadr fadr;
0047         fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
0048         snprintf(msg, sizeof(msg),
0049              "DIMM %d rank %d bank %d row %d col %d",
0050              fadr.cn30xx.fdimm, fadr.cn30xx.fbunk,
0051              fadr.cn30xx.fbank, fadr.cn30xx.frow, fadr.cn30xx.fcol);
0052     }
0053 
0054     if (cfg0.s.sec_err) {
0055         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
0056                      -1, -1, -1, msg, "");
0057         cfg0.s.sec_err = -1;    /* Done, re-arm */
0058         do_clear = true;
0059     }
0060 
0061     if (cfg0.s.ded_err) {
0062         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0063                      -1, -1, -1, msg, "");
0064         cfg0.s.ded_err = -1;    /* Done, re-arm */
0065         do_clear = true;
0066     }
0067     if (do_clear)
0068         cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);
0069 }
0070 
0071 static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
0072 {
0073     struct octeon_lmc_pvt *pvt = mci->pvt_info;
0074     union cvmx_lmcx_int int_reg;
0075     bool do_clear = false;
0076     char msg[64];
0077 
0078     if (!pvt->inject)
0079         int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
0080     else {
0081         int_reg.u64 = 0;
0082         if (pvt->error_type == 1)
0083             int_reg.s.sec_err = 1;
0084         if (pvt->error_type == 2)
0085             int_reg.s.ded_err = 1;
0086     }
0087 
0088     if (int_reg.s.sec_err || int_reg.s.ded_err) {
0089         union cvmx_lmcx_fadr fadr;
0090         if (likely(!pvt->inject))
0091             fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
0092         else {
0093             fadr.cn61xx.fdimm = pvt->dimm;
0094             fadr.cn61xx.fbunk = pvt->rank;
0095             fadr.cn61xx.fbank = pvt->bank;
0096             fadr.cn61xx.frow = pvt->row;
0097             fadr.cn61xx.fcol = pvt->col;
0098         }
0099         snprintf(msg, sizeof(msg),
0100              "DIMM %d rank %d bank %d row %d col %d",
0101              fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
0102              fadr.cn61xx.fbank, fadr.cn61xx.frow, fadr.cn61xx.fcol);
0103     }
0104 
0105     if (int_reg.s.sec_err) {
0106         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
0107                      -1, -1, -1, msg, "");
0108         int_reg.s.sec_err = -1; /* Done, re-arm */
0109         do_clear = true;
0110     }
0111 
0112     if (int_reg.s.ded_err) {
0113         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0114                      -1, -1, -1, msg, "");
0115         int_reg.s.ded_err = -1; /* Done, re-arm */
0116         do_clear = true;
0117     }
0118 
0119     if (do_clear) {
0120         if (likely(!pvt->inject))
0121             cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
0122         else
0123             pvt->inject = 0;
0124     }
0125 }
0126 
0127 /************************ MC SYSFS parts ***********************************/
0128 
0129 /* Only a couple naming differences per template, so very similar */
0130 #define TEMPLATE_SHOW(reg)                      \
0131 static ssize_t octeon_mc_inject_##reg##_show(struct device *dev,    \
0132                    struct device_attribute *attr,       \
0133                    char *data)              \
0134 {                                   \
0135     struct mem_ctl_info *mci = to_mci(dev);             \
0136     struct octeon_lmc_pvt *pvt = mci->pvt_info;         \
0137     return sprintf(data, "%016llu\n", (u64)pvt->reg);       \
0138 }
0139 
0140 #define TEMPLATE_STORE(reg)                     \
0141 static ssize_t octeon_mc_inject_##reg##_store(struct device *dev,   \
0142                    struct device_attribute *attr,       \
0143                    const char *data, size_t count)      \
0144 {                                   \
0145     struct mem_ctl_info *mci = to_mci(dev);             \
0146     struct octeon_lmc_pvt *pvt = mci->pvt_info;         \
0147     if (isdigit(*data)) {                       \
0148         if (!kstrtoul(data, 0, &pvt->reg))          \
0149             return count;                   \
0150     }                               \
0151     return 0;                           \
0152 }
0153 
0154 TEMPLATE_SHOW(inject);
0155 TEMPLATE_STORE(inject);
0156 TEMPLATE_SHOW(dimm);
0157 TEMPLATE_STORE(dimm);
0158 TEMPLATE_SHOW(bank);
0159 TEMPLATE_STORE(bank);
0160 TEMPLATE_SHOW(rank);
0161 TEMPLATE_STORE(rank);
0162 TEMPLATE_SHOW(row);
0163 TEMPLATE_STORE(row);
0164 TEMPLATE_SHOW(col);
0165 TEMPLATE_STORE(col);
0166 
0167 static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
0168                       struct device_attribute *attr,
0169                       const char *data,
0170                       size_t count)
0171 {
0172     struct mem_ctl_info *mci = to_mci(dev);
0173     struct octeon_lmc_pvt *pvt = mci->pvt_info;
0174 
0175     if (!strncmp(data, "single", 6))
0176         pvt->error_type = 1;
0177     else if (!strncmp(data, "double", 6))
0178         pvt->error_type = 2;
0179 
0180     return count;
0181 }
0182 
0183 static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
0184                      struct device_attribute *attr,
0185                      char *data)
0186 {
0187     struct mem_ctl_info *mci = to_mci(dev);
0188     struct octeon_lmc_pvt *pvt = mci->pvt_info;
0189     if (pvt->error_type == 1)
0190         return sprintf(data, "single");
0191     else if (pvt->error_type == 2)
0192         return sprintf(data, "double");
0193 
0194     return 0;
0195 }
0196 
0197 static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
0198            octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
0199 static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
0200            octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
0201 static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
0202            octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
0203 static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
0204            octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
0205 static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
0206            octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
0207 static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
0208            octeon_mc_inject_row_show, octeon_mc_inject_row_store);
0209 static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
0210            octeon_mc_inject_col_show, octeon_mc_inject_col_store);
0211 
0212 static struct attribute *octeon_dev_attrs[] = {
0213     &dev_attr_inject.attr,
0214     &dev_attr_error_type.attr,
0215     &dev_attr_dimm.attr,
0216     &dev_attr_rank.attr,
0217     &dev_attr_bank.attr,
0218     &dev_attr_row.attr,
0219     &dev_attr_col.attr,
0220     NULL
0221 };
0222 
0223 ATTRIBUTE_GROUPS(octeon_dev);
0224 
0225 static int octeon_lmc_edac_probe(struct platform_device *pdev)
0226 {
0227     struct mem_ctl_info *mci;
0228     struct edac_mc_layer layers[1];
0229     int mc = pdev->id;
0230 
0231     opstate_init();
0232 
0233     layers[0].type = EDAC_MC_LAYER_CHANNEL;
0234     layers[0].size = 1;
0235     layers[0].is_virt_csrow = false;
0236 
0237     if (OCTEON_IS_OCTEON1PLUS()) {
0238         union cvmx_lmcx_mem_cfg0 cfg0;
0239 
0240         cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
0241         if (!cfg0.s.ecc_ena) {
0242             dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
0243             return 0;
0244         }
0245 
0246         mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
0247         if (!mci)
0248             return -ENXIO;
0249 
0250         mci->pdev = &pdev->dev;
0251         mci->dev_name = dev_name(&pdev->dev);
0252 
0253         mci->mod_name = "octeon-lmc";
0254         mci->ctl_name = "octeon-lmc-err";
0255         mci->edac_check = octeon_lmc_edac_poll;
0256 
0257         if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
0258             dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
0259             edac_mc_free(mci);
0260             return -ENXIO;
0261         }
0262 
0263         cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
0264         cfg0.s.intr_ded_ena = 0;    /* We poll */
0265         cfg0.s.intr_sec_ena = 0;
0266         cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);
0267     } else {
0268         /* OCTEON II */
0269         union cvmx_lmcx_int_en en;
0270         union cvmx_lmcx_config config;
0271 
0272         config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
0273         if (!config.s.ecc_ena) {
0274             dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
0275             return 0;
0276         }
0277 
0278         mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
0279         if (!mci)
0280             return -ENXIO;
0281 
0282         mci->pdev = &pdev->dev;
0283         mci->dev_name = dev_name(&pdev->dev);
0284 
0285         mci->mod_name = "octeon-lmc";
0286         mci->ctl_name = "co_lmc_err";
0287         mci->edac_check = octeon_lmc_edac_poll_o2;
0288 
0289         if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
0290             dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
0291             edac_mc_free(mci);
0292             return -ENXIO;
0293         }
0294 
0295         en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
0296         en.s.intr_ded_ena = 0;  /* We poll */
0297         en.s.intr_sec_ena = 0;
0298         cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
0299     }
0300     platform_set_drvdata(pdev, mci);
0301 
0302     return 0;
0303 }
0304 
0305 static int octeon_lmc_edac_remove(struct platform_device *pdev)
0306 {
0307     struct mem_ctl_info *mci = platform_get_drvdata(pdev);
0308 
0309     edac_mc_del_mc(&pdev->dev);
0310     edac_mc_free(mci);
0311     return 0;
0312 }
0313 
0314 static struct platform_driver octeon_lmc_edac_driver = {
0315     .probe = octeon_lmc_edac_probe,
0316     .remove = octeon_lmc_edac_remove,
0317     .driver = {
0318            .name = "octeon_lmc_edac",
0319     }
0320 };
0321 module_platform_driver(octeon_lmc_edac_driver);
0322 
0323 MODULE_LICENSE("GPL");
0324 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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