drivers/edac/mpc85xx_edac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Freescale MPC85xx Memory Controller kernel module
0004  * Author: Dave Jiang <djiang@mvista.com>
0005  *
0006  * 2006-2007 (c) MontaVista Software, Inc.
0007  */
0008 #ifndef _MPC85XX_EDAC_H_
0009 #define _MPC85XX_EDAC_H_
0010
0011 #define MPC85XX_REVISION " Ver: 2.0.0"
0012 #define EDAC_MOD_STR    "MPC85xx_edac"
0013
0014 #define mpc85xx_printk(level, fmt, arg...) \
0015     edac_printk(level, "MPC85xx", fmt, ##arg)
0016
0017 /*
0018  * L2 Err defines
0019  */
0020 #define MPC85XX_L2_ERRINJHI 0x0000
0021 #define MPC85XX_L2_ERRINJLO 0x0004
0022 #define MPC85XX_L2_ERRINJCTL    0x0008
0023 #define MPC85XX_L2_CAPTDATAHI   0x0020
0024 #define MPC85XX_L2_CAPTDATALO   0x0024
0025 #define MPC85XX_L2_CAPTECC  0x0028
0026 #define MPC85XX_L2_ERRDET   0x0040
0027 #define MPC85XX_L2_ERRDIS   0x0044
0028 #define MPC85XX_L2_ERRINTEN 0x0048
0029 #define MPC85XX_L2_ERRATTR  0x004c
0030 #define MPC85XX_L2_ERRADDR  0x0050
0031 #define MPC85XX_L2_ERRCTL   0x0058
0032
0033 /* Error Interrupt Enable */
0034 #define L2_EIE_L2CFGINTEN   0x1
0035 #define L2_EIE_SBECCINTEN   0x4
0036 #define L2_EIE_MBECCINTEN   0x8
0037 #define L2_EIE_TPARINTEN    0x10
0038 #define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
0039             L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
0040
0041 /* Error Detect */
0042 #define L2_EDE_L2CFGERR     0x1
0043 #define L2_EDE_SBECCERR     0x4
0044 #define L2_EDE_MBECCERR     0x8
0045 #define L2_EDE_TPARERR      0x10
0046 #define L2_EDE_MULL2ERR     0x80000000
0047
0048 #define L2_EDE_CE_MASK  L2_EDE_SBECCERR
0049 #define L2_EDE_UE_MASK  (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
0050             L2_EDE_TPARERR)
0051 #define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
0052             L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
0053
0054 /*
0055  * PCI Err defines
0056  */
0057 #define PCI_EDE_TOE         0x00000001
0058 #define PCI_EDE_SCM         0x00000002
0059 #define PCI_EDE_IRMSV           0x00000004
0060 #define PCI_EDE_ORMSV           0x00000008
0061 #define PCI_EDE_OWMSV           0x00000010
0062 #define PCI_EDE_TGT_ABRT        0x00000020
0063 #define PCI_EDE_MST_ABRT        0x00000040
0064 #define PCI_EDE_TGT_PERR        0x00000080
0065 #define PCI_EDE_MST_PERR        0x00000100
0066 #define PCI_EDE_RCVD_SERR       0x00000200
0067 #define PCI_EDE_ADDR_PERR       0x00000400
0068 #define PCI_EDE_MULTI_ERR       0x80000000
0069
0070 #define PCI_EDE_PERR_MASK   (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
0071                 PCI_EDE_ADDR_PERR)
0072
0073 #define MPC85XX_PCI_ERR_DR      0x0000
0074 #define MPC85XX_PCI_ERR_CAP_DR      0x0004
0075 #define MPC85XX_PCI_ERR_EN      0x0008
0076 #define   PEX_ERR_ICCAIE_EN_BIT     0x00020000
0077 #define MPC85XX_PCI_ERR_ATTRIB      0x000c
0078 #define MPC85XX_PCI_ERR_ADDR        0x0010
0079 #define   PEX_ERR_ICCAD_DISR_BIT    0x00020000
0080 #define MPC85XX_PCI_ERR_EXT_ADDR    0x0014
0081 #define MPC85XX_PCI_ERR_DL      0x0018
0082 #define MPC85XX_PCI_ERR_DH      0x001c
0083 #define MPC85XX_PCI_GAS_TIMR        0x0020
0084 #define MPC85XX_PCI_PCIX_TIMR       0x0024
0085 #define MPC85XX_PCIE_ERR_CAP_R0     0x0028
0086 #define MPC85XX_PCIE_ERR_CAP_R1     0x002c
0087 #define MPC85XX_PCIE_ERR_CAP_R2     0x0030
0088 #define MPC85XX_PCIE_ERR_CAP_R3     0x0034
0089
0090 struct mpc85xx_l2_pdata {
0091     char *name;
0092     int edac_idx;
0093     void __iomem *l2_vbase;
0094     int irq;
0095 };
0096
0097 struct mpc85xx_pci_pdata {
0098     char *name;
0099     bool is_pcie;
0100     int edac_idx;
0101     void __iomem *pci_vbase;
0102     int irq;
0103 };
0104
0105 #endif