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0001 /*
0002  * Freescale MPC85xx Memory Controller kernel module
0003  *
0004  * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
0005  *
0006  * Author: Dave Jiang <djiang@mvista.com>
0007  *
0008  * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
0009  * the terms of the GNU General Public License version 2. This program
0010  * is licensed "as is" without any warranty of any kind, whether express
0011  * or implied.
0012  *
0013  */
0014 #include <linux/module.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/ctype.h>
0018 #include <linux/io.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/edac.h>
0021 #include <linux/smp.h>
0022 #include <linux/gfp.h>
0023 #include <linux/fsl/edac.h>
0024 
0025 #include <linux/of_platform.h>
0026 #include <linux/of_device.h>
0027 #include <linux/of_address.h>
0028 #include <linux/of_irq.h>
0029 #include "edac_module.h"
0030 #include "mpc85xx_edac.h"
0031 #include "fsl_ddr_edac.h"
0032 
0033 static int edac_dev_idx;
0034 #ifdef CONFIG_PCI
0035 static int edac_pci_idx;
0036 #endif
0037 
0038 /*
0039  * PCI Err defines
0040  */
0041 #ifdef CONFIG_PCI
0042 static u32 orig_pci_err_cap_dr;
0043 static u32 orig_pci_err_en;
0044 #endif
0045 
0046 static u32 orig_l2_err_disable;
0047 
0048 /**************************** PCI Err device ***************************/
0049 #ifdef CONFIG_PCI
0050 
0051 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
0052 {
0053     struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
0054     u32 err_detect;
0055 
0056     err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
0057 
0058     /* master aborts can happen during PCI config cycles */
0059     if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
0060         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
0061         return;
0062     }
0063 
0064     pr_err("PCI error(s) detected\n");
0065     pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
0066 
0067     pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
0068            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
0069     pr_err("PCI/X ERR_ADDR register: %#08x\n",
0070            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
0071     pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
0072            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
0073     pr_err("PCI/X ERR_DL register: %#08x\n",
0074            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
0075     pr_err("PCI/X ERR_DH register: %#08x\n",
0076            in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
0077 
0078     /* clear error bits */
0079     out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
0080 
0081     if (err_detect & PCI_EDE_PERR_MASK)
0082         edac_pci_handle_pe(pci, pci->ctl_name);
0083 
0084     if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
0085         edac_pci_handle_npe(pci, pci->ctl_name);
0086 }
0087 
0088 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
0089 {
0090     struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
0091     u32 err_detect, err_cap_stat;
0092 
0093     err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
0094     err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR);
0095 
0096     pr_err("PCIe error(s) detected\n");
0097     pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
0098     pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat);
0099     pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
0100             in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
0101     pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
0102             in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
0103     pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
0104             in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
0105     pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
0106             in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
0107 
0108     /* clear error bits */
0109     out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
0110 
0111     /* reset error capture */
0112     out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1);
0113 }
0114 
0115 static int mpc85xx_pcie_find_capability(struct device_node *np)
0116 {
0117     struct pci_controller *hose;
0118 
0119     if (!np)
0120         return -EINVAL;
0121 
0122     hose = pci_find_hose_for_OF_device(np);
0123 
0124     return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
0125 }
0126 
0127 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
0128 {
0129     struct edac_pci_ctl_info *pci = dev_id;
0130     struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
0131     u32 err_detect;
0132 
0133     err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
0134 
0135     if (!err_detect)
0136         return IRQ_NONE;
0137 
0138     if (pdata->is_pcie)
0139         mpc85xx_pcie_check(pci);
0140     else
0141         mpc85xx_pci_check(pci);
0142 
0143     return IRQ_HANDLED;
0144 }
0145 
0146 static int mpc85xx_pci_err_probe(struct platform_device *op)
0147 {
0148     struct edac_pci_ctl_info *pci;
0149     struct mpc85xx_pci_pdata *pdata;
0150     struct mpc85xx_edac_pci_plat_data *plat_data;
0151     struct device_node *of_node;
0152     struct resource r;
0153     int res = 0;
0154 
0155     if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
0156         return -ENOMEM;
0157 
0158     pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
0159     if (!pci)
0160         return -ENOMEM;
0161 
0162     /* make sure error reporting method is sane */
0163     switch (edac_op_state) {
0164     case EDAC_OPSTATE_POLL:
0165     case EDAC_OPSTATE_INT:
0166         break;
0167     default:
0168         edac_op_state = EDAC_OPSTATE_INT;
0169         break;
0170     }
0171 
0172     pdata = pci->pvt_info;
0173     pdata->name = "mpc85xx_pci_err";
0174 
0175     plat_data = op->dev.platform_data;
0176     if (!plat_data) {
0177         dev_err(&op->dev, "no platform data");
0178         res = -ENXIO;
0179         goto err;
0180     }
0181     of_node = plat_data->of_node;
0182 
0183     if (mpc85xx_pcie_find_capability(of_node) > 0)
0184         pdata->is_pcie = true;
0185 
0186     dev_set_drvdata(&op->dev, pci);
0187     pci->dev = &op->dev;
0188     pci->mod_name = EDAC_MOD_STR;
0189     pci->ctl_name = pdata->name;
0190     pci->dev_name = dev_name(&op->dev);
0191 
0192     if (edac_op_state == EDAC_OPSTATE_POLL) {
0193         if (pdata->is_pcie)
0194             pci->edac_check = mpc85xx_pcie_check;
0195         else
0196             pci->edac_check = mpc85xx_pci_check;
0197     }
0198 
0199     pdata->edac_idx = edac_pci_idx++;
0200 
0201     res = of_address_to_resource(of_node, 0, &r);
0202     if (res) {
0203         pr_err("%s: Unable to get resource for PCI err regs\n", __func__);
0204         goto err;
0205     }
0206 
0207     /* we only need the error registers */
0208     r.start += 0xe00;
0209 
0210     if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
0211                     pdata->name)) {
0212         pr_err("%s: Error while requesting mem region\n", __func__);
0213         res = -EBUSY;
0214         goto err;
0215     }
0216 
0217     pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
0218     if (!pdata->pci_vbase) {
0219         pr_err("%s: Unable to setup PCI err regs\n", __func__);
0220         res = -ENOMEM;
0221         goto err;
0222     }
0223 
0224     if (pdata->is_pcie) {
0225         orig_pci_err_cap_dr =
0226             in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
0227         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
0228         orig_pci_err_en =
0229             in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
0230         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
0231     } else {
0232         orig_pci_err_cap_dr =
0233             in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
0234 
0235         /* PCI master abort is expected during config cycles */
0236         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
0237 
0238         orig_pci_err_en =
0239             in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
0240 
0241         /* disable master abort reporting */
0242         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
0243     }
0244 
0245     /* clear error bits */
0246     out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
0247 
0248     /* reset error capture */
0249     out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1);
0250 
0251     if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
0252         edac_dbg(3, "failed edac_pci_add_device()\n");
0253         goto err;
0254     }
0255 
0256     if (edac_op_state == EDAC_OPSTATE_INT) {
0257         pdata->irq = irq_of_parse_and_map(of_node, 0);
0258         res = devm_request_irq(&op->dev, pdata->irq,
0259                        mpc85xx_pci_isr,
0260                        IRQF_SHARED,
0261                        "[EDAC] PCI err", pci);
0262         if (res < 0) {
0263             pr_err("%s: Unable to request irq %d for MPC85xx PCI err\n",
0264                 __func__, pdata->irq);
0265             irq_dispose_mapping(pdata->irq);
0266             res = -ENODEV;
0267             goto err2;
0268         }
0269 
0270         pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
0271                pdata->irq);
0272     }
0273 
0274     if (pdata->is_pcie) {
0275         /*
0276          * Enable all PCIe error interrupt & error detect except invalid
0277          * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
0278          * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
0279          * detection enable bit. Because PCIe bus code to initialize and
0280          * configure these PCIe devices on booting will use some invalid
0281          * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
0282          * notice information. So disable this detect to fix ugly print.
0283          */
0284         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
0285              & ~PEX_ERR_ICCAIE_EN_BIT);
0286         out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
0287              | PEX_ERR_ICCAD_DISR_BIT);
0288     }
0289 
0290     devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
0291     edac_dbg(3, "success\n");
0292     pr_info(EDAC_MOD_STR " PCI err registered\n");
0293 
0294     return 0;
0295 
0296 err2:
0297     edac_pci_del_device(&op->dev);
0298 err:
0299     edac_pci_free_ctl_info(pci);
0300     devres_release_group(&op->dev, mpc85xx_pci_err_probe);
0301     return res;
0302 }
0303 
0304 static int mpc85xx_pci_err_remove(struct platform_device *op)
0305 {
0306     struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
0307     struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
0308 
0309     edac_dbg(0, "\n");
0310 
0311     out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, orig_pci_err_cap_dr);
0312     out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
0313 
0314     edac_pci_del_device(&op->dev);
0315     edac_pci_free_ctl_info(pci);
0316 
0317     return 0;
0318 }
0319 
0320 static const struct platform_device_id mpc85xx_pci_err_match[] = {
0321     {
0322         .name = "mpc85xx-pci-edac"
0323     },
0324     {}
0325 };
0326 
0327 static struct platform_driver mpc85xx_pci_err_driver = {
0328     .probe = mpc85xx_pci_err_probe,
0329     .remove = mpc85xx_pci_err_remove,
0330     .id_table = mpc85xx_pci_err_match,
0331     .driver = {
0332         .name = "mpc85xx_pci_err",
0333         .suppress_bind_attrs = true,
0334     },
0335 };
0336 #endif              /* CONFIG_PCI */
0337 
0338 /**************************** L2 Err device ***************************/
0339 
0340 /************************ L2 SYSFS parts ***********************************/
0341 
0342 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
0343                           *edac_dev, char *data)
0344 {
0345     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0346     return sprintf(data, "0x%08x",
0347                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
0348 }
0349 
0350 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
0351                           *edac_dev, char *data)
0352 {
0353     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0354     return sprintf(data, "0x%08x",
0355                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
0356 }
0357 
0358 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
0359                        *edac_dev, char *data)
0360 {
0361     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0362     return sprintf(data, "0x%08x",
0363                in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
0364 }
0365 
0366 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
0367                            *edac_dev, const char *data,
0368                            size_t count)
0369 {
0370     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0371     if (isdigit(*data)) {
0372         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
0373              simple_strtoul(data, NULL, 0));
0374         return count;
0375     }
0376     return 0;
0377 }
0378 
0379 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
0380                            *edac_dev, const char *data,
0381                            size_t count)
0382 {
0383     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0384     if (isdigit(*data)) {
0385         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
0386              simple_strtoul(data, NULL, 0));
0387         return count;
0388     }
0389     return 0;
0390 }
0391 
0392 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
0393                         *edac_dev, const char *data,
0394                         size_t count)
0395 {
0396     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0397     if (isdigit(*data)) {
0398         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
0399              simple_strtoul(data, NULL, 0));
0400         return count;
0401     }
0402     return 0;
0403 }
0404 
0405 static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
0406     {
0407      .attr = {
0408           .name = "inject_data_hi",
0409           .mode = (S_IRUGO | S_IWUSR)
0410           },
0411      .show = mpc85xx_l2_inject_data_hi_show,
0412      .store = mpc85xx_l2_inject_data_hi_store},
0413     {
0414      .attr = {
0415           .name = "inject_data_lo",
0416           .mode = (S_IRUGO | S_IWUSR)
0417           },
0418      .show = mpc85xx_l2_inject_data_lo_show,
0419      .store = mpc85xx_l2_inject_data_lo_store},
0420     {
0421      .attr = {
0422           .name = "inject_ctrl",
0423           .mode = (S_IRUGO | S_IWUSR)
0424           },
0425      .show = mpc85xx_l2_inject_ctrl_show,
0426      .store = mpc85xx_l2_inject_ctrl_store},
0427 
0428     /* End of list */
0429     {
0430      .attr = {.name = NULL}
0431      }
0432 };
0433 
0434 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
0435                         *edac_dev)
0436 {
0437     edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
0438 }
0439 
0440 /***************************** L2 ops ***********************************/
0441 
0442 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
0443 {
0444     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0445     u32 err_detect;
0446 
0447     err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
0448 
0449     if (!(err_detect & L2_EDE_MASK))
0450         return;
0451 
0452     pr_err("ECC Error in CPU L2 cache\n");
0453     pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
0454     pr_err("L2 Error Capture Data High Register: 0x%08x\n",
0455            in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
0456     pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
0457            in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
0458     pr_err("L2 Error Syndrome Register: 0x%08x\n",
0459            in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
0460     pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
0461            in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
0462     pr_err("L2 Error Address Capture Register: 0x%08x\n",
0463            in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
0464 
0465     /* clear error detect register */
0466     out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
0467 
0468     if (err_detect & L2_EDE_CE_MASK)
0469         edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
0470 
0471     if (err_detect & L2_EDE_UE_MASK)
0472         edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
0473 }
0474 
0475 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
0476 {
0477     struct edac_device_ctl_info *edac_dev = dev_id;
0478     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0479     u32 err_detect;
0480 
0481     err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
0482 
0483     if (!(err_detect & L2_EDE_MASK))
0484         return IRQ_NONE;
0485 
0486     mpc85xx_l2_check(edac_dev);
0487 
0488     return IRQ_HANDLED;
0489 }
0490 
0491 static int mpc85xx_l2_err_probe(struct platform_device *op)
0492 {
0493     struct edac_device_ctl_info *edac_dev;
0494     struct mpc85xx_l2_pdata *pdata;
0495     struct resource r;
0496     int res;
0497 
0498     if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
0499         return -ENOMEM;
0500 
0501     edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
0502                           "cpu", 1, "L", 1, 2, NULL, 0,
0503                           edac_dev_idx);
0504     if (!edac_dev) {
0505         devres_release_group(&op->dev, mpc85xx_l2_err_probe);
0506         return -ENOMEM;
0507     }
0508 
0509     pdata = edac_dev->pvt_info;
0510     pdata->name = "mpc85xx_l2_err";
0511     edac_dev->dev = &op->dev;
0512     dev_set_drvdata(edac_dev->dev, edac_dev);
0513     edac_dev->ctl_name = pdata->name;
0514     edac_dev->dev_name = pdata->name;
0515 
0516     res = of_address_to_resource(op->dev.of_node, 0, &r);
0517     if (res) {
0518         pr_err("%s: Unable to get resource for L2 err regs\n", __func__);
0519         goto err;
0520     }
0521 
0522     /* we only need the error registers */
0523     r.start += 0xe00;
0524 
0525     if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
0526                      pdata->name)) {
0527         pr_err("%s: Error while requesting mem region\n", __func__);
0528         res = -EBUSY;
0529         goto err;
0530     }
0531 
0532     pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
0533     if (!pdata->l2_vbase) {
0534         pr_err("%s: Unable to setup L2 err regs\n", __func__);
0535         res = -ENOMEM;
0536         goto err;
0537     }
0538 
0539     out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
0540 
0541     orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
0542 
0543     /* clear the err_dis */
0544     out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
0545 
0546     edac_dev->mod_name = EDAC_MOD_STR;
0547 
0548     if (edac_op_state == EDAC_OPSTATE_POLL)
0549         edac_dev->edac_check = mpc85xx_l2_check;
0550 
0551     mpc85xx_set_l2_sysfs_attributes(edac_dev);
0552 
0553     pdata->edac_idx = edac_dev_idx++;
0554 
0555     if (edac_device_add_device(edac_dev) > 0) {
0556         edac_dbg(3, "failed edac_device_add_device()\n");
0557         goto err;
0558     }
0559 
0560     if (edac_op_state == EDAC_OPSTATE_INT) {
0561         pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
0562         res = devm_request_irq(&op->dev, pdata->irq,
0563                        mpc85xx_l2_isr, IRQF_SHARED,
0564                        "[EDAC] L2 err", edac_dev);
0565         if (res < 0) {
0566             pr_err("%s: Unable to request irq %d for MPC85xx L2 err\n",
0567                 __func__, pdata->irq);
0568             irq_dispose_mapping(pdata->irq);
0569             res = -ENODEV;
0570             goto err2;
0571         }
0572 
0573         pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n", pdata->irq);
0574 
0575         edac_dev->op_state = OP_RUNNING_INTERRUPT;
0576 
0577         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
0578     }
0579 
0580     devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
0581 
0582     edac_dbg(3, "success\n");
0583     pr_info(EDAC_MOD_STR " L2 err registered\n");
0584 
0585     return 0;
0586 
0587 err2:
0588     edac_device_del_device(&op->dev);
0589 err:
0590     devres_release_group(&op->dev, mpc85xx_l2_err_probe);
0591     edac_device_free_ctl_info(edac_dev);
0592     return res;
0593 }
0594 
0595 static int mpc85xx_l2_err_remove(struct platform_device *op)
0596 {
0597     struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
0598     struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
0599 
0600     edac_dbg(0, "\n");
0601 
0602     if (edac_op_state == EDAC_OPSTATE_INT) {
0603         out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
0604         irq_dispose_mapping(pdata->irq);
0605     }
0606 
0607     out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
0608     edac_device_del_device(&op->dev);
0609     edac_device_free_ctl_info(edac_dev);
0610     return 0;
0611 }
0612 
0613 static const struct of_device_id mpc85xx_l2_err_of_match[] = {
0614     { .compatible = "fsl,mpc8536-l2-cache-controller", },
0615     { .compatible = "fsl,mpc8540-l2-cache-controller", },
0616     { .compatible = "fsl,mpc8541-l2-cache-controller", },
0617     { .compatible = "fsl,mpc8544-l2-cache-controller", },
0618     { .compatible = "fsl,mpc8548-l2-cache-controller", },
0619     { .compatible = "fsl,mpc8555-l2-cache-controller", },
0620     { .compatible = "fsl,mpc8560-l2-cache-controller", },
0621     { .compatible = "fsl,mpc8568-l2-cache-controller", },
0622     { .compatible = "fsl,mpc8569-l2-cache-controller", },
0623     { .compatible = "fsl,mpc8572-l2-cache-controller", },
0624     { .compatible = "fsl,p1020-l2-cache-controller", },
0625     { .compatible = "fsl,p1021-l2-cache-controller", },
0626     { .compatible = "fsl,p2020-l2-cache-controller", },
0627     { .compatible = "fsl,t2080-l2-cache-controller", },
0628     {},
0629 };
0630 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
0631 
0632 static struct platform_driver mpc85xx_l2_err_driver = {
0633     .probe = mpc85xx_l2_err_probe,
0634     .remove = mpc85xx_l2_err_remove,
0635     .driver = {
0636         .name = "mpc85xx_l2_err",
0637         .of_match_table = mpc85xx_l2_err_of_match,
0638     },
0639 };
0640 
0641 static const struct of_device_id mpc85xx_mc_err_of_match[] = {
0642     { .compatible = "fsl,mpc8536-memory-controller", },
0643     { .compatible = "fsl,mpc8540-memory-controller", },
0644     { .compatible = "fsl,mpc8541-memory-controller", },
0645     { .compatible = "fsl,mpc8544-memory-controller", },
0646     { .compatible = "fsl,mpc8548-memory-controller", },
0647     { .compatible = "fsl,mpc8555-memory-controller", },
0648     { .compatible = "fsl,mpc8560-memory-controller", },
0649     { .compatible = "fsl,mpc8568-memory-controller", },
0650     { .compatible = "fsl,mpc8569-memory-controller", },
0651     { .compatible = "fsl,mpc8572-memory-controller", },
0652     { .compatible = "fsl,mpc8349-memory-controller", },
0653     { .compatible = "fsl,p1020-memory-controller", },
0654     { .compatible = "fsl,p1021-memory-controller", },
0655     { .compatible = "fsl,p2020-memory-controller", },
0656     { .compatible = "fsl,qoriq-memory-controller", },
0657     {},
0658 };
0659 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
0660 
0661 static struct platform_driver mpc85xx_mc_err_driver = {
0662     .probe = fsl_mc_err_probe,
0663     .remove = fsl_mc_err_remove,
0664     .driver = {
0665         .name = "mpc85xx_mc_err",
0666         .of_match_table = mpc85xx_mc_err_of_match,
0667     },
0668 };
0669 
0670 static struct platform_driver * const drivers[] = {
0671     &mpc85xx_mc_err_driver,
0672     &mpc85xx_l2_err_driver,
0673 #ifdef CONFIG_PCI
0674     &mpc85xx_pci_err_driver,
0675 #endif
0676 };
0677 
0678 static int __init mpc85xx_mc_init(void)
0679 {
0680     int res = 0;
0681     u32 __maybe_unused pvr = 0;
0682 
0683     pr_info("Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software\n");
0684 
0685     /* make sure error reporting method is sane */
0686     switch (edac_op_state) {
0687     case EDAC_OPSTATE_POLL:
0688     case EDAC_OPSTATE_INT:
0689         break;
0690     default:
0691         edac_op_state = EDAC_OPSTATE_INT;
0692         break;
0693     }
0694 
0695     res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
0696     if (res)
0697         pr_warn(EDAC_MOD_STR "drivers fail to register\n");
0698 
0699     return 0;
0700 }
0701 
0702 module_init(mpc85xx_mc_init);
0703 
0704 static void __exit mpc85xx_mc_exit(void)
0705 {
0706     platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
0707 }
0708 
0709 module_exit(mpc85xx_mc_exit);
0710 
0711 MODULE_LICENSE("GPL");
0712 MODULE_AUTHOR("Montavista Software, Inc.");
0713 module_param(edac_op_state, int, 0444);
0714 MODULE_PARM_DESC(edac_op_state,
0715          "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
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