Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/module.h>
0003 #include <linux/slab.h>
0004 
0005 #include <asm/cpu.h>
0006 
0007 #include "mce_amd.h"
0008 
0009 static struct amd_decoder_ops fam_ops;
0010 
0011 static u8 xec_mask   = 0xf;
0012 
0013 static void (*decode_dram_ecc)(int node_id, struct mce *m);
0014 
0015 void amd_register_ecc_decoder(void (*f)(int, struct mce *))
0016 {
0017     decode_dram_ecc = f;
0018 }
0019 EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
0020 
0021 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
0022 {
0023     if (decode_dram_ecc) {
0024         WARN_ON(decode_dram_ecc != f);
0025 
0026         decode_dram_ecc = NULL;
0027     }
0028 }
0029 EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
0030 
0031 /*
0032  * string representation for the different MCA reported error types, see F3x48
0033  * or MSR0000_0411.
0034  */
0035 
0036 /* transaction type */
0037 static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
0038 
0039 /* cache level */
0040 static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
0041 
0042 /* memory transaction type */
0043 static const char * const rrrr_msgs[] = {
0044        "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
0045 };
0046 
0047 /* participating processor */
0048 const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
0049 EXPORT_SYMBOL_GPL(pp_msgs);
0050 
0051 /* request timeout */
0052 static const char * const to_msgs[] = { "no timeout", "timed out" };
0053 
0054 /* memory or i/o */
0055 static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
0056 
0057 /* internal error type */
0058 static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
0059 
0060 static const char * const f15h_mc1_mce_desc[] = {
0061     "UC during a demand linefill from L2",
0062     "Parity error during data load from IC",
0063     "Parity error for IC valid bit",
0064     "Main tag parity error",
0065     "Parity error in prediction queue",
0066     "PFB data/address parity error",
0067     "Parity error in the branch status reg",
0068     "PFB promotion address error",
0069     "Tag error during probe/victimization",
0070     "Parity error for IC probe tag valid bit",
0071     "PFB non-cacheable bit parity error",
0072     "PFB valid bit parity error",           /* xec = 0xd */
0073     "Microcode Patch Buffer",           /* xec = 010 */
0074     "uop queue",
0075     "insn buffer",
0076     "predecode buffer",
0077     "fetch address FIFO",
0078     "dispatch uop queue"
0079 };
0080 
0081 static const char * const f15h_mc2_mce_desc[] = {
0082     "Fill ECC error on data fills",         /* xec = 0x4 */
0083     "Fill parity error on insn fills",
0084     "Prefetcher request FIFO parity error",
0085     "PRQ address parity error",
0086     "PRQ data parity error",
0087     "WCC Tag ECC error",
0088     "WCC Data ECC error",
0089     "WCB Data parity error",
0090     "VB Data ECC or parity error",
0091     "L2 Tag ECC error",             /* xec = 0x10 */
0092     "Hard L2 Tag ECC error",
0093     "Multiple hits on L2 tag",
0094     "XAB parity error",
0095     "PRB address parity error"
0096 };
0097 
0098 static const char * const mc4_mce_desc[] = {
0099     "DRAM ECC error detected on the NB",
0100     "CRC error detected on HT link",
0101     "Link-defined sync error packets detected on HT link",
0102     "HT Master abort",
0103     "HT Target abort",
0104     "Invalid GART PTE entry during GART table walk",
0105     "Unsupported atomic RMW received from an IO link",
0106     "Watchdog timeout due to lack of progress",
0107     "DRAM ECC error detected on the NB",
0108     "SVM DMA Exclusion Vector error",
0109     "HT data error detected on link",
0110     "Protocol error (link, L3, probe filter)",
0111     "NB internal arrays parity error",
0112     "DRAM addr/ctl signals parity error",
0113     "IO link transmission error",
0114     "L3 data cache ECC error",          /* xec = 0x1c */
0115     "L3 cache tag error",
0116     "L3 LRU parity bits error",
0117     "ECC Error in the Probe Filter directory"
0118 };
0119 
0120 static const char * const mc5_mce_desc[] = {
0121     "CPU Watchdog timer expire",
0122     "Wakeup array dest tag",
0123     "AG payload array",
0124     "EX payload array",
0125     "IDRF array",
0126     "Retire dispatch queue",
0127     "Mapper checkpoint array",
0128     "Physical register file EX0 port",
0129     "Physical register file EX1 port",
0130     "Physical register file AG0 port",
0131     "Physical register file AG1 port",
0132     "Flag register file",
0133     "DE error occurred",
0134     "Retire status queue"
0135 };
0136 
0137 static const char * const mc6_mce_desc[] = {
0138     "Hardware Assertion",
0139     "Free List",
0140     "Physical Register File",
0141     "Retire Queue",
0142     "Scheduler table",
0143     "Status Register File",
0144 };
0145 
0146 /* Scalable MCA error strings */
0147 static const char * const smca_ls_mce_desc[] = {
0148     "Load queue parity error",
0149     "Store queue parity error",
0150     "Miss address buffer payload parity error",
0151     "Level 1 TLB parity error",
0152     "DC Tag error type 5",
0153     "DC Tag error type 6",
0154     "DC Tag error type 1",
0155     "Internal error type 1",
0156     "Internal error type 2",
0157     "System Read Data Error Thread 0",
0158     "System Read Data Error Thread 1",
0159     "DC Tag error type 2",
0160     "DC Data error type 1 and poison consumption",
0161     "DC Data error type 2",
0162     "DC Data error type 3",
0163     "DC Tag error type 4",
0164     "Level 2 TLB parity error",
0165     "PDC parity error",
0166     "DC Tag error type 3",
0167     "DC Tag error type 5",
0168     "L2 Fill Data error",
0169 };
0170 
0171 static const char * const smca_ls2_mce_desc[] = {
0172     "An ECC error was detected on a data cache read by a probe or victimization",
0173     "An ECC error or L2 poison was detected on a data cache read by a load",
0174     "An ECC error was detected on a data cache read-modify-write by a store",
0175     "An ECC error or poison bit mismatch was detected on a tag read by a probe or victimization",
0176     "An ECC error or poison bit mismatch was detected on a tag read by a load",
0177     "An ECC error or poison bit mismatch was detected on a tag read by a store",
0178     "An ECC error was detected on an EMEM read by a load",
0179     "An ECC error was detected on an EMEM read-modify-write by a store",
0180     "A parity error was detected in an L1 TLB entry by any access",
0181     "A parity error was detected in an L2 TLB entry by any access",
0182     "A parity error was detected in a PWC entry by any access",
0183     "A parity error was detected in an STQ entry by any access",
0184     "A parity error was detected in an LDQ entry by any access",
0185     "A parity error was detected in a MAB entry by any access",
0186     "A parity error was detected in an SCB entry state field by any access",
0187     "A parity error was detected in an SCB entry address field by any access",
0188     "A parity error was detected in an SCB entry data field by any access",
0189     "A parity error was detected in a WCB entry by any access",
0190     "A poisoned line was detected in an SCB entry by any access",
0191     "A SystemReadDataError error was reported on read data returned from L2 for a load",
0192     "A SystemReadDataError error was reported on read data returned from L2 for an SCB store",
0193     "A SystemReadDataError error was reported on read data returned from L2 for a WCB store",
0194     "A hardware assertion error was reported",
0195     "A parity error was detected in an STLF, SCB EMEM entry or SRB store data by any access",
0196 };
0197 
0198 static const char * const smca_if_mce_desc[] = {
0199     "Op Cache Microtag Probe Port Parity Error",
0200     "IC Microtag or Full Tag Multi-hit Error",
0201     "IC Full Tag Parity Error",
0202     "IC Data Array Parity Error",
0203     "Decoupling Queue PhysAddr Parity Error",
0204     "L0 ITLB Parity Error",
0205     "L1 ITLB Parity Error",
0206     "L2 ITLB Parity Error",
0207     "BPQ Thread 0 Snoop Parity Error",
0208     "BPQ Thread 1 Snoop Parity Error",
0209     "L1 BTB Multi-Match Error",
0210     "L2 BTB Multi-Match Error",
0211     "L2 Cache Response Poison Error",
0212     "System Read Data Error",
0213     "Hardware Assertion Error",
0214     "L1-TLB Multi-Hit",
0215     "L2-TLB Multi-Hit",
0216     "BSR Parity Error",
0217     "CT MCE",
0218 };
0219 
0220 static const char * const smca_l2_mce_desc[] = {
0221     "L2M Tag Multiple-Way-Hit error",
0222     "L2M Tag or State Array ECC Error",
0223     "L2M Data Array ECC Error",
0224     "Hardware Assert Error",
0225 };
0226 
0227 static const char * const smca_de_mce_desc[] = {
0228     "Micro-op cache tag parity error",
0229     "Micro-op cache data parity error",
0230     "Instruction buffer parity error",
0231     "Micro-op queue parity error",
0232     "Instruction dispatch queue parity error",
0233     "Fetch address FIFO parity error",
0234     "Patch RAM data parity error",
0235     "Patch RAM sequencer parity error",
0236     "Micro-op buffer parity error",
0237     "Hardware Assertion MCA Error",
0238 };
0239 
0240 static const char * const smca_ex_mce_desc[] = {
0241     "Watchdog Timeout error",
0242     "Physical register file parity error",
0243     "Flag register file parity error",
0244     "Immediate displacement register file parity error",
0245     "Address generator payload parity error",
0246     "EX payload parity error",
0247     "Checkpoint queue parity error",
0248     "Retire dispatch queue parity error",
0249     "Retire status queue parity error",
0250     "Scheduling queue parity error",
0251     "Branch buffer queue parity error",
0252     "Hardware Assertion error",
0253     "Spec Map parity error",
0254     "Retire Map parity error",
0255 };
0256 
0257 static const char * const smca_fp_mce_desc[] = {
0258     "Physical register file (PRF) parity error",
0259     "Freelist (FL) parity error",
0260     "Schedule queue parity error",
0261     "NSQ parity error",
0262     "Retire queue (RQ) parity error",
0263     "Status register file (SRF) parity error",
0264     "Hardware assertion",
0265 };
0266 
0267 static const char * const smca_l3_mce_desc[] = {
0268     "Shadow Tag Macro ECC Error",
0269     "Shadow Tag Macro Multi-way-hit Error",
0270     "L3M Tag ECC Error",
0271     "L3M Tag Multi-way-hit Error",
0272     "L3M Data ECC Error",
0273     "SDP Parity Error or SystemReadDataError from XI",
0274     "L3 Victim Queue Parity Error",
0275     "L3 Hardware Assertion",
0276 };
0277 
0278 static const char * const smca_cs_mce_desc[] = {
0279     "Illegal Request",
0280     "Address Violation",
0281     "Security Violation",
0282     "Illegal Response",
0283     "Unexpected Response",
0284     "Request or Probe Parity Error",
0285     "Read Response Parity Error",
0286     "Atomic Request Parity Error",
0287     "Probe Filter ECC Error",
0288 };
0289 
0290 static const char * const smca_cs2_mce_desc[] = {
0291     "Illegal Request",
0292     "Address Violation",
0293     "Security Violation",
0294     "Illegal Response",
0295     "Unexpected Response",
0296     "Request or Probe Parity Error",
0297     "Read Response Parity Error",
0298     "Atomic Request Parity Error",
0299     "SDP read response had no match in the CS queue",
0300     "Probe Filter Protocol Error",
0301     "Probe Filter ECC Error",
0302     "SDP read response had an unexpected RETRY error",
0303     "Counter overflow error",
0304     "Counter underflow error",
0305 };
0306 
0307 static const char * const smca_pie_mce_desc[] = {
0308     "Hardware Assert",
0309     "Register security violation",
0310     "Link Error",
0311     "Poison data consumption",
0312     "A deferred error was detected in the DF"
0313 };
0314 
0315 static const char * const smca_umc_mce_desc[] = {
0316     "DRAM ECC error",
0317     "Data poison error",
0318     "SDP parity error",
0319     "Advanced peripheral bus error",
0320     "Address/Command parity error",
0321     "Write data CRC error",
0322     "DCQ SRAM ECC error",
0323     "AES SRAM ECC error",
0324 };
0325 
0326 static const char * const smca_umc2_mce_desc[] = {
0327     "DRAM ECC error",
0328     "Data poison error",
0329     "SDP parity error",
0330     "Reserved",
0331     "Address/Command parity error",
0332     "Write data parity error",
0333     "DCQ SRAM ECC error",
0334     "Reserved",
0335     "Read data parity error",
0336     "Rdb SRAM ECC error",
0337     "RdRsp SRAM ECC error",
0338     "LM32 MP errors",
0339 };
0340 
0341 static const char * const smca_pb_mce_desc[] = {
0342     "An ECC error in the Parameter Block RAM array",
0343 };
0344 
0345 static const char * const smca_psp_mce_desc[] = {
0346     "An ECC or parity error in a PSP RAM instance",
0347 };
0348 
0349 static const char * const smca_psp2_mce_desc[] = {
0350     "High SRAM ECC or parity error",
0351     "Low SRAM ECC or parity error",
0352     "Instruction Cache Bank 0 ECC or parity error",
0353     "Instruction Cache Bank 1 ECC or parity error",
0354     "Instruction Tag Ram 0 parity error",
0355     "Instruction Tag Ram 1 parity error",
0356     "Data Cache Bank 0 ECC or parity error",
0357     "Data Cache Bank 1 ECC or parity error",
0358     "Data Cache Bank 2 ECC or parity error",
0359     "Data Cache Bank 3 ECC or parity error",
0360     "Data Tag Bank 0 parity error",
0361     "Data Tag Bank 1 parity error",
0362     "Data Tag Bank 2 parity error",
0363     "Data Tag Bank 3 parity error",
0364     "Dirty Data Ram parity error",
0365     "TLB Bank 0 parity error",
0366     "TLB Bank 1 parity error",
0367     "System Hub Read Buffer ECC or parity error",
0368 };
0369 
0370 static const char * const smca_smu_mce_desc[] = {
0371     "An ECC or parity error in an SMU RAM instance",
0372 };
0373 
0374 static const char * const smca_smu2_mce_desc[] = {
0375     "High SRAM ECC or parity error",
0376     "Low SRAM ECC or parity error",
0377     "Data Cache Bank A ECC or parity error",
0378     "Data Cache Bank B ECC or parity error",
0379     "Data Tag Cache Bank A ECC or parity error",
0380     "Data Tag Cache Bank B ECC or parity error",
0381     "Instruction Cache Bank A ECC or parity error",
0382     "Instruction Cache Bank B ECC or parity error",
0383     "Instruction Tag Cache Bank A ECC or parity error",
0384     "Instruction Tag Cache Bank B ECC or parity error",
0385     "System Hub Read Buffer ECC or parity error",
0386     "PHY RAM ECC error",
0387 };
0388 
0389 static const char * const smca_mp5_mce_desc[] = {
0390     "High SRAM ECC or parity error",
0391     "Low SRAM ECC or parity error",
0392     "Data Cache Bank A ECC or parity error",
0393     "Data Cache Bank B ECC or parity error",
0394     "Data Tag Cache Bank A ECC or parity error",
0395     "Data Tag Cache Bank B ECC or parity error",
0396     "Instruction Cache Bank A ECC or parity error",
0397     "Instruction Cache Bank B ECC or parity error",
0398     "Instruction Tag Cache Bank A ECC or parity error",
0399     "Instruction Tag Cache Bank B ECC or parity error",
0400 };
0401 
0402 static const char * const smca_mpdma_mce_desc[] = {
0403     "Main SRAM [31:0] bank ECC or parity error",
0404     "Main SRAM [63:32] bank ECC or parity error",
0405     "Main SRAM [95:64] bank ECC or parity error",
0406     "Main SRAM [127:96] bank ECC or parity error",
0407     "Data Cache Bank A ECC or parity error",
0408     "Data Cache Bank B ECC or parity error",
0409     "Data Tag Cache Bank A ECC or parity error",
0410     "Data Tag Cache Bank B ECC or parity error",
0411     "Instruction Cache Bank A ECC or parity error",
0412     "Instruction Cache Bank B ECC or parity error",
0413     "Instruction Tag Cache Bank A ECC or parity error",
0414     "Instruction Tag Cache Bank B ECC or parity error",
0415     "Data Cache Bank A ECC or parity error",
0416     "Data Cache Bank B ECC or parity error",
0417     "Data Tag Cache Bank A ECC or parity error",
0418     "Data Tag Cache Bank B ECC or parity error",
0419     "Instruction Cache Bank A ECC or parity error",
0420     "Instruction Cache Bank B ECC or parity error",
0421     "Instruction Tag Cache Bank A ECC or parity error",
0422     "Instruction Tag Cache Bank B ECC or parity error",
0423     "Data Cache Bank A ECC or parity error",
0424     "Data Cache Bank B ECC or parity error",
0425     "Data Tag Cache Bank A ECC or parity error",
0426     "Data Tag Cache Bank B ECC or parity error",
0427     "Instruction Cache Bank A ECC or parity error",
0428     "Instruction Cache Bank B ECC or parity error",
0429     "Instruction Tag Cache Bank A ECC or parity error",
0430     "Instruction Tag Cache Bank B ECC or parity error",
0431     "System Hub Read Buffer ECC or parity error",
0432     "MPDMA TVF DVSEC Memory ECC or parity error",
0433     "MPDMA TVF MMIO Mailbox0 ECC or parity error",
0434     "MPDMA TVF MMIO Mailbox1 ECC or parity error",
0435     "MPDMA TVF Doorbell Memory ECC or parity error",
0436     "MPDMA TVF SDP Slave Memory 0 ECC or parity error",
0437     "MPDMA TVF SDP Slave Memory 1 ECC or parity error",
0438     "MPDMA TVF SDP Slave Memory 2 ECC or parity error",
0439     "MPDMA TVF SDP Master Memory 0 ECC or parity error",
0440     "MPDMA TVF SDP Master Memory 1 ECC or parity error",
0441     "MPDMA TVF SDP Master Memory 2 ECC or parity error",
0442     "MPDMA TVF SDP Master Memory 3 ECC or parity error",
0443     "MPDMA TVF SDP Master Memory 4 ECC or parity error",
0444     "MPDMA TVF SDP Master Memory 5 ECC or parity error",
0445     "MPDMA TVF SDP Master Memory 6 ECC or parity error",
0446     "MPDMA PTE Command FIFO ECC or parity error",
0447     "MPDMA PTE Hub Data FIFO ECC or parity error",
0448     "MPDMA PTE Internal Data FIFO ECC or parity error",
0449     "MPDMA PTE Command Memory DMA ECC or parity error",
0450     "MPDMA PTE Command Memory Internal ECC or parity error",
0451     "MPDMA PTE DMA Completion FIFO ECC or parity error",
0452     "MPDMA PTE Tablewalk Completion FIFO ECC or parity error",
0453     "MPDMA PTE Descriptor Completion FIFO ECC or parity error",
0454     "MPDMA PTE ReadOnly Completion FIFO ECC or parity error",
0455     "MPDMA PTE DirectWrite Completion FIFO ECC or parity error",
0456     "SDP Watchdog Timer expired",
0457 };
0458 
0459 static const char * const smca_nbio_mce_desc[] = {
0460     "ECC or Parity error",
0461     "PCIE error",
0462     "SDP ErrEvent error",
0463     "SDP Egress Poison Error",
0464     "IOHC Internal Poison Error",
0465 };
0466 
0467 static const char * const smca_pcie_mce_desc[] = {
0468     "CCIX PER Message logging",
0469     "CCIX Read Response with Status: Non-Data Error",
0470     "CCIX Write Response with Status: Non-Data Error",
0471     "CCIX Read Response with Status: Data Error",
0472     "CCIX Non-okay write response with data error",
0473 };
0474 
0475 static const char * const smca_pcie2_mce_desc[] = {
0476     "SDP Parity Error logging",
0477 };
0478 
0479 static const char * const smca_xgmipcs_mce_desc[] = {
0480     "Data Loss Error",
0481     "Training Error",
0482     "Flow Control Acknowledge Error",
0483     "Rx Fifo Underflow Error",
0484     "Rx Fifo Overflow Error",
0485     "CRC Error",
0486     "BER Exceeded Error",
0487     "Tx Vcid Data Error",
0488     "Replay Buffer Parity Error",
0489     "Data Parity Error",
0490     "Replay Fifo Overflow Error",
0491     "Replay Fifo Underflow Error",
0492     "Elastic Fifo Overflow Error",
0493     "Deskew Error",
0494     "Flow Control CRC Error",
0495     "Data Startup Limit Error",
0496     "FC Init Timeout Error",
0497     "Recovery Timeout Error",
0498     "Ready Serial Timeout Error",
0499     "Ready Serial Attempt Error",
0500     "Recovery Attempt Error",
0501     "Recovery Relock Attempt Error",
0502     "Replay Attempt Error",
0503     "Sync Header Error",
0504     "Tx Replay Timeout Error",
0505     "Rx Replay Timeout Error",
0506     "LinkSub Tx Timeout Error",
0507     "LinkSub Rx Timeout Error",
0508     "Rx CMD Packet Error",
0509 };
0510 
0511 static const char * const smca_xgmiphy_mce_desc[] = {
0512     "RAM ECC Error",
0513     "ARC instruction buffer parity error",
0514     "ARC data buffer parity error",
0515     "PHY APB error",
0516 };
0517 
0518 static const char * const smca_nbif_mce_desc[] = {
0519     "Timeout error from GMI",
0520     "SRAM ECC error",
0521     "NTB Error Event",
0522     "SDP Parity error",
0523 };
0524 
0525 static const char * const smca_sata_mce_desc[] = {
0526     "Parity error for port 0",
0527     "Parity error for port 1",
0528     "Parity error for port 2",
0529     "Parity error for port 3",
0530     "Parity error for port 4",
0531     "Parity error for port 5",
0532     "Parity error for port 6",
0533     "Parity error for port 7",
0534 };
0535 
0536 static const char * const smca_usb_mce_desc[] = {
0537     "Parity error or ECC error for S0 RAM0",
0538     "Parity error or ECC error for S0 RAM1",
0539     "Parity error or ECC error for S0 RAM2",
0540     "Parity error for PHY RAM0",
0541     "Parity error for PHY RAM1",
0542     "AXI Slave Response error",
0543 };
0544 
0545 static const char * const smca_gmipcs_mce_desc[] = {
0546     "Data Loss Error",
0547     "Training Error",
0548     "Replay Parity Error",
0549     "Rx Fifo Underflow Error",
0550     "Rx Fifo Overflow Error",
0551     "CRC Error",
0552     "BER Exceeded Error",
0553     "Tx Fifo Underflow Error",
0554     "Replay Buffer Parity Error",
0555     "Tx Overflow Error",
0556     "Replay Fifo Overflow Error",
0557     "Replay Fifo Underflow Error",
0558     "Elastic Fifo Overflow Error",
0559     "Deskew Error",
0560     "Offline Error",
0561     "Data Startup Limit Error",
0562     "FC Init Timeout Error",
0563     "Recovery Timeout Error",
0564     "Ready Serial Timeout Error",
0565     "Ready Serial Attempt Error",
0566     "Recovery Attempt Error",
0567     "Recovery Relock Attempt Error",
0568     "Deskew Abort Error",
0569     "Rx Buffer Error",
0570     "Rx LFDS Fifo Overflow Error",
0571     "Rx LFDS Fifo Underflow Error",
0572     "LinkSub Tx Timeout Error",
0573     "LinkSub Rx Timeout Error",
0574     "Rx CMD Packet Error",
0575     "LFDS Training Timeout Error",
0576     "LFDS FC Init Timeout Error",
0577     "Data Loss Error",
0578 };
0579 
0580 struct smca_mce_desc {
0581     const char * const *descs;
0582     unsigned int num_descs;
0583 };
0584 
0585 static struct smca_mce_desc smca_mce_descs[] = {
0586     [SMCA_LS]   = { smca_ls_mce_desc,   ARRAY_SIZE(smca_ls_mce_desc)    },
0587     [SMCA_LS_V2]    = { smca_ls2_mce_desc,  ARRAY_SIZE(smca_ls2_mce_desc)   },
0588     [SMCA_IF]   = { smca_if_mce_desc,   ARRAY_SIZE(smca_if_mce_desc)    },
0589     [SMCA_L2_CACHE] = { smca_l2_mce_desc,   ARRAY_SIZE(smca_l2_mce_desc)    },
0590     [SMCA_DE]   = { smca_de_mce_desc,   ARRAY_SIZE(smca_de_mce_desc)    },
0591     [SMCA_EX]   = { smca_ex_mce_desc,   ARRAY_SIZE(smca_ex_mce_desc)    },
0592     [SMCA_FP]   = { smca_fp_mce_desc,   ARRAY_SIZE(smca_fp_mce_desc)    },
0593     [SMCA_L3_CACHE] = { smca_l3_mce_desc,   ARRAY_SIZE(smca_l3_mce_desc)    },
0594     [SMCA_CS]   = { smca_cs_mce_desc,   ARRAY_SIZE(smca_cs_mce_desc)    },
0595     [SMCA_CS_V2]    = { smca_cs2_mce_desc,  ARRAY_SIZE(smca_cs2_mce_desc)   },
0596     [SMCA_PIE]  = { smca_pie_mce_desc,  ARRAY_SIZE(smca_pie_mce_desc)   },
0597     [SMCA_UMC]  = { smca_umc_mce_desc,  ARRAY_SIZE(smca_umc_mce_desc)   },
0598     [SMCA_UMC_V2]   = { smca_umc2_mce_desc, ARRAY_SIZE(smca_umc2_mce_desc)  },
0599     [SMCA_PB]   = { smca_pb_mce_desc,   ARRAY_SIZE(smca_pb_mce_desc)    },
0600     [SMCA_PSP]  = { smca_psp_mce_desc,  ARRAY_SIZE(smca_psp_mce_desc)   },
0601     [SMCA_PSP_V2]   = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc)  },
0602     [SMCA_SMU]  = { smca_smu_mce_desc,  ARRAY_SIZE(smca_smu_mce_desc)   },
0603     [SMCA_SMU_V2]   = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc)  },
0604     [SMCA_MP5]  = { smca_mp5_mce_desc,  ARRAY_SIZE(smca_mp5_mce_desc)   },
0605     [SMCA_MPDMA]    = { smca_mpdma_mce_desc,    ARRAY_SIZE(smca_mpdma_mce_desc) },
0606     [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc)  },
0607     [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc)  },
0608     [SMCA_PCIE_V2]  = { smca_pcie2_mce_desc,   ARRAY_SIZE(smca_pcie2_mce_desc)  },
0609     [SMCA_XGMI_PCS] = { smca_xgmipcs_mce_desc, ARRAY_SIZE(smca_xgmipcs_mce_desc)    },
0610     /* NBIF and SHUB have the same error descriptions, for now. */
0611     [SMCA_NBIF] = { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc)  },
0612     [SMCA_SHUB] = { smca_nbif_mce_desc, ARRAY_SIZE(smca_nbif_mce_desc)  },
0613     [SMCA_SATA] = { smca_sata_mce_desc, ARRAY_SIZE(smca_sata_mce_desc)  },
0614     [SMCA_USB]  = { smca_usb_mce_desc,  ARRAY_SIZE(smca_usb_mce_desc)   },
0615     [SMCA_GMI_PCS]  = { smca_gmipcs_mce_desc,  ARRAY_SIZE(smca_gmipcs_mce_desc) },
0616     /* All the PHY bank types have the same error descriptions, for now. */
0617     [SMCA_XGMI_PHY] = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)    },
0618     [SMCA_WAFL_PHY] = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)    },
0619     [SMCA_GMI_PHY]  = { smca_xgmiphy_mce_desc, ARRAY_SIZE(smca_xgmiphy_mce_desc)    },
0620 };
0621 
0622 static bool f12h_mc0_mce(u16 ec, u8 xec)
0623 {
0624     bool ret = false;
0625 
0626     if (MEM_ERROR(ec)) {
0627         u8 ll = LL(ec);
0628         ret = true;
0629 
0630         if (ll == LL_L2)
0631             pr_cont("during L1 linefill from L2.\n");
0632         else if (ll == LL_L1)
0633             pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
0634         else
0635             ret = false;
0636     }
0637     return ret;
0638 }
0639 
0640 static bool f10h_mc0_mce(u16 ec, u8 xec)
0641 {
0642     if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
0643         pr_cont("during data scrub.\n");
0644         return true;
0645     }
0646     return f12h_mc0_mce(ec, xec);
0647 }
0648 
0649 static bool k8_mc0_mce(u16 ec, u8 xec)
0650 {
0651     if (BUS_ERROR(ec)) {
0652         pr_cont("during system linefill.\n");
0653         return true;
0654     }
0655 
0656     return f10h_mc0_mce(ec, xec);
0657 }
0658 
0659 static bool cat_mc0_mce(u16 ec, u8 xec)
0660 {
0661     u8 r4    = R4(ec);
0662     bool ret = true;
0663 
0664     if (MEM_ERROR(ec)) {
0665 
0666         if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
0667             return false;
0668 
0669         switch (r4) {
0670         case R4_DRD:
0671         case R4_DWR:
0672             pr_cont("Data/Tag parity error due to %s.\n",
0673                 (r4 == R4_DRD ? "load/hw prf" : "store"));
0674             break;
0675         case R4_EVICT:
0676             pr_cont("Copyback parity error on a tag miss.\n");
0677             break;
0678         case R4_SNOOP:
0679             pr_cont("Tag parity error during snoop.\n");
0680             break;
0681         default:
0682             ret = false;
0683         }
0684     } else if (BUS_ERROR(ec)) {
0685 
0686         if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
0687             return false;
0688 
0689         pr_cont("System read data error on a ");
0690 
0691         switch (r4) {
0692         case R4_RD:
0693             pr_cont("TLB reload.\n");
0694             break;
0695         case R4_DWR:
0696             pr_cont("store.\n");
0697             break;
0698         case R4_DRD:
0699             pr_cont("load.\n");
0700             break;
0701         default:
0702             ret = false;
0703         }
0704     } else {
0705         ret = false;
0706     }
0707 
0708     return ret;
0709 }
0710 
0711 static bool f15h_mc0_mce(u16 ec, u8 xec)
0712 {
0713     bool ret = true;
0714 
0715     if (MEM_ERROR(ec)) {
0716 
0717         switch (xec) {
0718         case 0x0:
0719             pr_cont("Data Array access error.\n");
0720             break;
0721 
0722         case 0x1:
0723             pr_cont("UC error during a linefill from L2/NB.\n");
0724             break;
0725 
0726         case 0x2:
0727         case 0x11:
0728             pr_cont("STQ access error.\n");
0729             break;
0730 
0731         case 0x3:
0732             pr_cont("SCB access error.\n");
0733             break;
0734 
0735         case 0x10:
0736             pr_cont("Tag error.\n");
0737             break;
0738 
0739         case 0x12:
0740             pr_cont("LDQ access error.\n");
0741             break;
0742 
0743         default:
0744             ret = false;
0745         }
0746     } else if (BUS_ERROR(ec)) {
0747 
0748         if (!xec)
0749             pr_cont("System Read Data Error.\n");
0750         else
0751             pr_cont(" Internal error condition type %d.\n", xec);
0752     } else if (INT_ERROR(ec)) {
0753         if (xec <= 0x1f)
0754             pr_cont("Hardware Assert.\n");
0755         else
0756             ret = false;
0757 
0758     } else
0759         ret = false;
0760 
0761     return ret;
0762 }
0763 
0764 static void decode_mc0_mce(struct mce *m)
0765 {
0766     u16 ec = EC(m->status);
0767     u8 xec = XEC(m->status, xec_mask);
0768 
0769     pr_emerg(HW_ERR "MC0 Error: ");
0770 
0771     /* TLB error signatures are the same across families */
0772     if (TLB_ERROR(ec)) {
0773         if (TT(ec) == TT_DATA) {
0774             pr_cont("%s TLB %s.\n", LL_MSG(ec),
0775                 ((xec == 2) ? "locked miss"
0776                         : (xec ? "multimatch" : "parity")));
0777             return;
0778         }
0779     } else if (fam_ops.mc0_mce(ec, xec))
0780         ;
0781     else
0782         pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
0783 }
0784 
0785 static bool k8_mc1_mce(u16 ec, u8 xec)
0786 {
0787     u8 ll    = LL(ec);
0788     bool ret = true;
0789 
0790     if (!MEM_ERROR(ec))
0791         return false;
0792 
0793     if (ll == 0x2)
0794         pr_cont("during a linefill from L2.\n");
0795     else if (ll == 0x1) {
0796         switch (R4(ec)) {
0797         case R4_IRD:
0798             pr_cont("Parity error during data load.\n");
0799             break;
0800 
0801         case R4_EVICT:
0802             pr_cont("Copyback Parity/Victim error.\n");
0803             break;
0804 
0805         case R4_SNOOP:
0806             pr_cont("Tag Snoop error.\n");
0807             break;
0808 
0809         default:
0810             ret = false;
0811             break;
0812         }
0813     } else
0814         ret = false;
0815 
0816     return ret;
0817 }
0818 
0819 static bool cat_mc1_mce(u16 ec, u8 xec)
0820 {
0821     u8 r4    = R4(ec);
0822     bool ret = true;
0823 
0824     if (!MEM_ERROR(ec))
0825         return false;
0826 
0827     if (TT(ec) != TT_INSTR)
0828         return false;
0829 
0830     if (r4 == R4_IRD)
0831         pr_cont("Data/tag array parity error for a tag hit.\n");
0832     else if (r4 == R4_SNOOP)
0833         pr_cont("Tag error during snoop/victimization.\n");
0834     else if (xec == 0x0)
0835         pr_cont("Tag parity error from victim castout.\n");
0836     else if (xec == 0x2)
0837         pr_cont("Microcode patch RAM parity error.\n");
0838     else
0839         ret = false;
0840 
0841     return ret;
0842 }
0843 
0844 static bool f15h_mc1_mce(u16 ec, u8 xec)
0845 {
0846     bool ret = true;
0847 
0848     if (!MEM_ERROR(ec))
0849         return false;
0850 
0851     switch (xec) {
0852     case 0x0 ... 0xa:
0853         pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
0854         break;
0855 
0856     case 0xd:
0857         pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
0858         break;
0859 
0860     case 0x10:
0861         pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
0862         break;
0863 
0864     case 0x11 ... 0x15:
0865         pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
0866         break;
0867 
0868     default:
0869         ret = false;
0870     }
0871     return ret;
0872 }
0873 
0874 static void decode_mc1_mce(struct mce *m)
0875 {
0876     u16 ec = EC(m->status);
0877     u8 xec = XEC(m->status, xec_mask);
0878 
0879     pr_emerg(HW_ERR "MC1 Error: ");
0880 
0881     if (TLB_ERROR(ec))
0882         pr_cont("%s TLB %s.\n", LL_MSG(ec),
0883             (xec ? "multimatch" : "parity error"));
0884     else if (BUS_ERROR(ec)) {
0885         bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
0886 
0887         pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
0888     } else if (INT_ERROR(ec)) {
0889         if (xec <= 0x3f)
0890             pr_cont("Hardware Assert.\n");
0891         else
0892             goto wrong_mc1_mce;
0893     } else if (fam_ops.mc1_mce(ec, xec))
0894         ;
0895     else
0896         goto wrong_mc1_mce;
0897 
0898     return;
0899 
0900 wrong_mc1_mce:
0901     pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
0902 }
0903 
0904 static bool k8_mc2_mce(u16 ec, u8 xec)
0905 {
0906     bool ret = true;
0907 
0908     if (xec == 0x1)
0909         pr_cont(" in the write data buffers.\n");
0910     else if (xec == 0x3)
0911         pr_cont(" in the victim data buffers.\n");
0912     else if (xec == 0x2 && MEM_ERROR(ec))
0913         pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
0914     else if (xec == 0x0) {
0915         if (TLB_ERROR(ec))
0916             pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
0917                 TT_MSG(ec));
0918         else if (BUS_ERROR(ec))
0919             pr_cont(": %s/ECC error in data read from NB: %s.\n",
0920                 R4_MSG(ec), PP_MSG(ec));
0921         else if (MEM_ERROR(ec)) {
0922             u8 r4 = R4(ec);
0923 
0924             if (r4 >= 0x7)
0925                 pr_cont(": %s error during data copyback.\n",
0926                     R4_MSG(ec));
0927             else if (r4 <= 0x1)
0928                 pr_cont(": %s parity/ECC error during data "
0929                     "access from L2.\n", R4_MSG(ec));
0930             else
0931                 ret = false;
0932         } else
0933             ret = false;
0934     } else
0935         ret = false;
0936 
0937     return ret;
0938 }
0939 
0940 static bool f15h_mc2_mce(u16 ec, u8 xec)
0941 {
0942     bool ret = true;
0943 
0944     if (TLB_ERROR(ec)) {
0945         if (xec == 0x0)
0946             pr_cont("Data parity TLB read error.\n");
0947         else if (xec == 0x1)
0948             pr_cont("Poison data provided for TLB fill.\n");
0949         else
0950             ret = false;
0951     } else if (BUS_ERROR(ec)) {
0952         if (xec > 2)
0953             ret = false;
0954 
0955         pr_cont("Error during attempted NB data read.\n");
0956     } else if (MEM_ERROR(ec)) {
0957         switch (xec) {
0958         case 0x4 ... 0xc:
0959             pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
0960             break;
0961 
0962         case 0x10 ... 0x14:
0963             pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
0964             break;
0965 
0966         default:
0967             ret = false;
0968         }
0969     } else if (INT_ERROR(ec)) {
0970         if (xec <= 0x3f)
0971             pr_cont("Hardware Assert.\n");
0972         else
0973             ret = false;
0974     }
0975 
0976     return ret;
0977 }
0978 
0979 static bool f16h_mc2_mce(u16 ec, u8 xec)
0980 {
0981     u8 r4 = R4(ec);
0982 
0983     if (!MEM_ERROR(ec))
0984         return false;
0985 
0986     switch (xec) {
0987     case 0x04 ... 0x05:
0988         pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
0989         break;
0990 
0991     case 0x09 ... 0x0b:
0992     case 0x0d ... 0x0f:
0993         pr_cont("ECC error in L2 tag (%s).\n",
0994             ((r4 == R4_GEN)   ? "BankReq" :
0995             ((r4 == R4_SNOOP) ? "Prb"     : "Fill")));
0996         break;
0997 
0998     case 0x10 ... 0x19:
0999     case 0x1b:
1000         pr_cont("ECC error in L2 data array (%s).\n",
1001             (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit"  :
1002             ((r4 == R4_GEN)   ? "Attr" :
1003             ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
1004         break;
1005 
1006     case 0x1c ... 0x1d:
1007     case 0x1f:
1008         pr_cont("Parity error in L2 attribute bits (%s).\n",
1009             ((r4 == R4_RD)  ? "Hit"  :
1010             ((r4 == R4_GEN) ? "Attr" : "Fill")));
1011         break;
1012 
1013     default:
1014         return false;
1015     }
1016 
1017     return true;
1018 }
1019 
1020 static void decode_mc2_mce(struct mce *m)
1021 {
1022     u16 ec = EC(m->status);
1023     u8 xec = XEC(m->status, xec_mask);
1024 
1025     pr_emerg(HW_ERR "MC2 Error: ");
1026 
1027     if (!fam_ops.mc2_mce(ec, xec))
1028         pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
1029 }
1030 
1031 static void decode_mc3_mce(struct mce *m)
1032 {
1033     u16 ec = EC(m->status);
1034     u8 xec = XEC(m->status, xec_mask);
1035 
1036     if (boot_cpu_data.x86 >= 0x14) {
1037         pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
1038              " please report on LKML.\n");
1039         return;
1040     }
1041 
1042     pr_emerg(HW_ERR "MC3 Error");
1043 
1044     if (xec == 0x0) {
1045         u8 r4 = R4(ec);
1046 
1047         if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
1048             goto wrong_mc3_mce;
1049 
1050         pr_cont(" during %s.\n", R4_MSG(ec));
1051     } else
1052         goto wrong_mc3_mce;
1053 
1054     return;
1055 
1056  wrong_mc3_mce:
1057     pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
1058 }
1059 
1060 static void decode_mc4_mce(struct mce *m)
1061 {
1062     unsigned int fam = x86_family(m->cpuid);
1063     int node_id = topology_die_id(m->extcpu);
1064     u16 ec = EC(m->status);
1065     u8 xec = XEC(m->status, 0x1f);
1066     u8 offset = 0;
1067 
1068     pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
1069 
1070     switch (xec) {
1071     case 0x0 ... 0xe:
1072 
1073         /* special handling for DRAM ECCs */
1074         if (xec == 0x0 || xec == 0x8) {
1075             /* no ECCs on F11h */
1076             if (fam == 0x11)
1077                 goto wrong_mc4_mce;
1078 
1079             pr_cont("%s.\n", mc4_mce_desc[xec]);
1080 
1081             if (decode_dram_ecc)
1082                 decode_dram_ecc(node_id, m);
1083             return;
1084         }
1085         break;
1086 
1087     case 0xf:
1088         if (TLB_ERROR(ec))
1089             pr_cont("GART Table Walk data error.\n");
1090         else if (BUS_ERROR(ec))
1091             pr_cont("DMA Exclusion Vector Table Walk error.\n");
1092         else
1093             goto wrong_mc4_mce;
1094         return;
1095 
1096     case 0x19:
1097         if (fam == 0x15 || fam == 0x16)
1098             pr_cont("Compute Unit Data Error.\n");
1099         else
1100             goto wrong_mc4_mce;
1101         return;
1102 
1103     case 0x1c ... 0x1f:
1104         offset = 13;
1105         break;
1106 
1107     default:
1108         goto wrong_mc4_mce;
1109     }
1110 
1111     pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
1112     return;
1113 
1114  wrong_mc4_mce:
1115     pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
1116 }
1117 
1118 static void decode_mc5_mce(struct mce *m)
1119 {
1120     unsigned int fam = x86_family(m->cpuid);
1121     u16 ec = EC(m->status);
1122     u8 xec = XEC(m->status, xec_mask);
1123 
1124     if (fam == 0xf || fam == 0x11)
1125         goto wrong_mc5_mce;
1126 
1127     pr_emerg(HW_ERR "MC5 Error: ");
1128 
1129     if (INT_ERROR(ec)) {
1130         if (xec <= 0x1f) {
1131             pr_cont("Hardware Assert.\n");
1132             return;
1133         } else
1134             goto wrong_mc5_mce;
1135     }
1136 
1137     if (xec == 0x0 || xec == 0xc)
1138         pr_cont("%s.\n", mc5_mce_desc[xec]);
1139     else if (xec <= 0xd)
1140         pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
1141     else
1142         goto wrong_mc5_mce;
1143 
1144     return;
1145 
1146  wrong_mc5_mce:
1147     pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
1148 }
1149 
1150 static void decode_mc6_mce(struct mce *m)
1151 {
1152     u8 xec = XEC(m->status, xec_mask);
1153 
1154     pr_emerg(HW_ERR "MC6 Error: ");
1155 
1156     if (xec > 0x5)
1157         goto wrong_mc6_mce;
1158 
1159     pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
1160     return;
1161 
1162  wrong_mc6_mce:
1163     pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
1164 }
1165 
1166 /* Decode errors according to Scalable MCA specification */
1167 static void decode_smca_error(struct mce *m)
1168 {
1169     enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
1170     const char *ip_name;
1171     u8 xec = XEC(m->status, xec_mask);
1172 
1173     if (bank_type >= N_SMCA_BANK_TYPES)
1174         return;
1175 
1176     if (bank_type == SMCA_RESERVED) {
1177         pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);
1178         return;
1179     }
1180 
1181     ip_name = smca_get_long_name(bank_type);
1182 
1183     pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);
1184 
1185     /* Only print the decode of valid error codes */
1186     if (xec < smca_mce_descs[bank_type].num_descs)
1187         pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);
1188 
1189     if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
1190         decode_dram_ecc(topology_die_id(m->extcpu), m);
1191 }
1192 
1193 static inline void amd_decode_err_code(u16 ec)
1194 {
1195     if (INT_ERROR(ec)) {
1196         pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
1197         return;
1198     }
1199 
1200     pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
1201 
1202     if (BUS_ERROR(ec))
1203         pr_cont(", mem/io: %s", II_MSG(ec));
1204     else
1205         pr_cont(", tx: %s", TT_MSG(ec));
1206 
1207     if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
1208         pr_cont(", mem-tx: %s", R4_MSG(ec));
1209 
1210         if (BUS_ERROR(ec))
1211             pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
1212     }
1213 
1214     pr_cont("\n");
1215 }
1216 
1217 static const char *decode_error_status(struct mce *m)
1218 {
1219     if (m->status & MCI_STATUS_UC) {
1220         if (m->status & MCI_STATUS_PCC)
1221             return "System Fatal error.";
1222         if (m->mcgstatus & MCG_STATUS_RIPV)
1223             return "Uncorrected, software restartable error.";
1224         return "Uncorrected, software containable error.";
1225     }
1226 
1227     if (m->status & MCI_STATUS_DEFERRED)
1228         return "Deferred error, no action required.";
1229 
1230     return "Corrected error, no action required.";
1231 }
1232 
1233 static int
1234 amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
1235 {
1236     struct mce *m = (struct mce *)data;
1237     unsigned int fam = x86_family(m->cpuid);
1238     int ecc;
1239 
1240     if (m->kflags & MCE_HANDLED_CEC)
1241         return NOTIFY_DONE;
1242 
1243     pr_emerg(HW_ERR "%s\n", decode_error_status(m));
1244 
1245     pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
1246         m->extcpu,
1247         fam, x86_model(m->cpuid), x86_stepping(m->cpuid),
1248         m->bank,
1249         ((m->status & MCI_STATUS_OVER)  ? "Over"  : "-"),
1250         ((m->status & MCI_STATUS_UC)    ? "UE"    :
1251          (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),
1252         ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
1253         ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"),
1254         ((m->status & MCI_STATUS_PCC)   ? "PCC"   : "-"));
1255 
1256     if (boot_cpu_has(X86_FEATURE_SMCA)) {
1257         u32 low, high;
1258         u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
1259 
1260         if (!rdmsr_safe(addr, &low, &high) &&
1261             (low & MCI_CONFIG_MCAX))
1262             pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
1263 
1264         pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
1265     }
1266 
1267     /* do the two bits[14:13] together */
1268     ecc = (m->status >> 45) & 0x3;
1269     if (ecc)
1270         pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
1271 
1272     if (fam >= 0x15) {
1273         pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
1274 
1275         /* F15h, bank4, bit 43 is part of McaStatSubCache. */
1276         if (fam != 0x15 || m->bank != 4)
1277             pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
1278     }
1279 
1280     if (fam >= 0x17)
1281         pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));
1282 
1283     pr_cont("]: 0x%016llx\n", m->status);
1284 
1285     if (m->status & MCI_STATUS_ADDRV)
1286         pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
1287 
1288     if (m->ppin)
1289         pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin);
1290 
1291     if (boot_cpu_has(X86_FEATURE_SMCA)) {
1292         pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);
1293 
1294         if (m->status & MCI_STATUS_SYNDV)
1295             pr_cont(", Syndrome: 0x%016llx", m->synd);
1296 
1297         pr_cont("\n");
1298 
1299         decode_smca_error(m);
1300         goto err_code;
1301     }
1302 
1303     if (m->tsc)
1304         pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);
1305 
1306     /* Doesn't matter which member to test. */
1307     if (!fam_ops.mc0_mce)
1308         goto err_code;
1309 
1310     switch (m->bank) {
1311     case 0:
1312         decode_mc0_mce(m);
1313         break;
1314 
1315     case 1:
1316         decode_mc1_mce(m);
1317         break;
1318 
1319     case 2:
1320         decode_mc2_mce(m);
1321         break;
1322 
1323     case 3:
1324         decode_mc3_mce(m);
1325         break;
1326 
1327     case 4:
1328         decode_mc4_mce(m);
1329         break;
1330 
1331     case 5:
1332         decode_mc5_mce(m);
1333         break;
1334 
1335     case 6:
1336         decode_mc6_mce(m);
1337         break;
1338 
1339     default:
1340         break;
1341     }
1342 
1343  err_code:
1344     amd_decode_err_code(m->status & 0xffff);
1345 
1346     m->kflags |= MCE_HANDLED_EDAC;
1347     return NOTIFY_OK;
1348 }
1349 
1350 static struct notifier_block amd_mce_dec_nb = {
1351     .notifier_call  = amd_decode_mce,
1352     .priority   = MCE_PRIO_EDAC,
1353 };
1354 
1355 static int __init mce_amd_init(void)
1356 {
1357     struct cpuinfo_x86 *c = &boot_cpu_data;
1358 
1359     if (c->x86_vendor != X86_VENDOR_AMD &&
1360         c->x86_vendor != X86_VENDOR_HYGON)
1361         return -ENODEV;
1362 
1363     if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
1364         return -ENODEV;
1365 
1366     if (boot_cpu_has(X86_FEATURE_SMCA)) {
1367         xec_mask = 0x3f;
1368         goto out;
1369     }
1370 
1371     switch (c->x86) {
1372     case 0xf:
1373         fam_ops.mc0_mce = k8_mc0_mce;
1374         fam_ops.mc1_mce = k8_mc1_mce;
1375         fam_ops.mc2_mce = k8_mc2_mce;
1376         break;
1377 
1378     case 0x10:
1379         fam_ops.mc0_mce = f10h_mc0_mce;
1380         fam_ops.mc1_mce = k8_mc1_mce;
1381         fam_ops.mc2_mce = k8_mc2_mce;
1382         break;
1383 
1384     case 0x11:
1385         fam_ops.mc0_mce = k8_mc0_mce;
1386         fam_ops.mc1_mce = k8_mc1_mce;
1387         fam_ops.mc2_mce = k8_mc2_mce;
1388         break;
1389 
1390     case 0x12:
1391         fam_ops.mc0_mce = f12h_mc0_mce;
1392         fam_ops.mc1_mce = k8_mc1_mce;
1393         fam_ops.mc2_mce = k8_mc2_mce;
1394         break;
1395 
1396     case 0x14:
1397         fam_ops.mc0_mce = cat_mc0_mce;
1398         fam_ops.mc1_mce = cat_mc1_mce;
1399         fam_ops.mc2_mce = k8_mc2_mce;
1400         break;
1401 
1402     case 0x15:
1403         xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;
1404 
1405         fam_ops.mc0_mce = f15h_mc0_mce;
1406         fam_ops.mc1_mce = f15h_mc1_mce;
1407         fam_ops.mc2_mce = f15h_mc2_mce;
1408         break;
1409 
1410     case 0x16:
1411         xec_mask = 0x1f;
1412         fam_ops.mc0_mce = cat_mc0_mce;
1413         fam_ops.mc1_mce = cat_mc1_mce;
1414         fam_ops.mc2_mce = f16h_mc2_mce;
1415         break;
1416 
1417     case 0x17:
1418     case 0x18:
1419         pr_warn_once("Decoding supported only on Scalable MCA processors.\n");
1420         return -EINVAL;
1421 
1422     default:
1423         printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
1424         return -EINVAL;
1425     }
1426 
1427 out:
1428     pr_info("MCE: In-kernel MCE decoding enabled.\n");
1429 
1430     mce_register_decode_chain(&amd_mce_dec_nb);
1431 
1432     return 0;
1433 }
1434 early_initcall(mce_amd_init);
1435 
1436 #ifdef MODULE
1437 static void __exit mce_amd_exit(void)
1438 {
1439     mce_unregister_decode_chain(&amd_mce_dec_nb);
1440 }
1441 
1442 MODULE_DESCRIPTION("AMD MCE decoder");
1443 MODULE_ALIAS("edac-mce-amd");
1444 MODULE_LICENSE("GPL");
1445 module_exit(mce_amd_exit);
1446 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!