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0001 /*
0002  * Intel 82975X Memory Controller kernel module
0003  * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
0004  * (C) 2007 jetzbroadband (http://jetzbroadband.com)
0005  * This file may be distributed under the terms of the
0006  * GNU General Public License.
0007  *
0008  * Written by Arvind R.
0009  *   Copied from i82875p_edac.c source:
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/pci.h>
0015 #include <linux/pci_ids.h>
0016 #include <linux/edac.h>
0017 #include "edac_module.h"
0018 
0019 #define EDAC_MOD_STR        "i82975x_edac"
0020 
0021 #define i82975x_printk(level, fmt, arg...) \
0022     edac_printk(level, "i82975x", fmt, ##arg)
0023 
0024 #define i82975x_mc_printk(mci, level, fmt, arg...) \
0025     edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg)
0026 
0027 #ifndef PCI_DEVICE_ID_INTEL_82975_0
0028 #define PCI_DEVICE_ID_INTEL_82975_0 0x277c
0029 #endif              /* PCI_DEVICE_ID_INTEL_82975_0 */
0030 
0031 #define I82975X_NR_DIMMS        8
0032 #define I82975X_NR_CSROWS(nr_chans) (I82975X_NR_DIMMS / (nr_chans))
0033 
0034 /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */
0035 #define I82975X_EAP     0x58    /* Dram Error Address Pointer (32b)
0036                      *
0037                      * 31:7  128 byte cache-line address
0038                      * 6:1   reserved
0039                      * 0     0: CH0; 1: CH1
0040                      */
0041 
0042 #define I82975X_DERRSYN     0x5c    /* Dram Error SYNdrome (8b)
0043                      *
0044                      *  7:0  DRAM ECC Syndrome
0045                      */
0046 
0047 #define I82975X_DES     0x5d    /* Dram ERRor DeSTination (8b)
0048                      * 0h:    Processor Memory Reads
0049                      * 1h:7h  reserved
0050                      * More - See Page 65 of Intel DocSheet.
0051                      */
0052 
0053 #define I82975X_ERRSTS      0xc8    /* Error Status Register (16b)
0054                      *
0055                      * 15:12 reserved
0056                      * 11    Thermal Sensor Event
0057                      * 10    reserved
0058                      *  9    non-DRAM lock error (ndlock)
0059                      *  8    Refresh Timeout
0060                      *  7:2  reserved
0061                      *  1    ECC UE (multibit DRAM error)
0062                      *  0    ECC CE (singlebit DRAM error)
0063                      */
0064 
0065 /* Error Reporting is supported by 3 mechanisms:
0066   1. DMI SERR generation  ( ERRCMD )
0067   2. SMI DMI  generation  ( SMICMD )
0068   3. SCI DMI  generation  ( SCICMD )
0069 NOTE: Only ONE of the three must be enabled
0070 */
0071 #define I82975X_ERRCMD      0xca    /* Error Command (16b)
0072                      *
0073                      * 15:12 reserved
0074                      * 11    Thermal Sensor Event
0075                      * 10    reserved
0076                      *  9    non-DRAM lock error (ndlock)
0077                      *  8    Refresh Timeout
0078                      *  7:2  reserved
0079                      *  1    ECC UE (multibit DRAM error)
0080                      *  0    ECC CE (singlebit DRAM error)
0081                      */
0082 
0083 #define I82975X_SMICMD      0xcc    /* Error Command (16b)
0084                      *
0085                      * 15:2  reserved
0086                      *  1    ECC UE (multibit DRAM error)
0087                      *  0    ECC CE (singlebit DRAM error)
0088                      */
0089 
0090 #define I82975X_SCICMD      0xce    /* Error Command (16b)
0091                      *
0092                      * 15:2  reserved
0093                      *  1    ECC UE (multibit DRAM error)
0094                      *  0    ECC CE (singlebit DRAM error)
0095                      */
0096 
0097 #define I82975X_XEAP    0xfc    /* Extended Dram Error Address Pointer (8b)
0098                      *
0099                      * 7:1   reserved
0100                      * 0     Bit32 of the Dram Error Address
0101                      */
0102 
0103 #define I82975X_MCHBAR      0x44    /*
0104                      *
0105                      * 31:14 Base Addr of 16K memory-mapped
0106                      *  configuration space
0107                      * 13:1  reserved
0108                      *  0    mem-mapped config space enable
0109                      */
0110 
0111 /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */
0112 /* Intel 82975x memory mapped register space */
0113 
0114 #define I82975X_DRB_SHIFT 25    /* fixed 32MiB grain */
0115 
0116 #define I82975X_DRB     0x100   /* DRAM Row Boundary (8b x 8)
0117                      *
0118                      * 7   set to 1 in highest DRB of
0119                      *  channel if 4GB in ch.
0120                      * 6:2 upper boundary of rank in
0121                      *  32MB grains
0122                      * 1:0 set to 0
0123                      */
0124 #define I82975X_DRB_CH0R0       0x100
0125 #define I82975X_DRB_CH0R1       0x101
0126 #define I82975X_DRB_CH0R2       0x102
0127 #define I82975X_DRB_CH0R3       0x103
0128 #define I82975X_DRB_CH1R0       0x180
0129 #define I82975X_DRB_CH1R1       0x181
0130 #define I82975X_DRB_CH1R2       0x182
0131 #define I82975X_DRB_CH1R3       0x183
0132 
0133 
0134 #define I82975X_DRA     0x108   /* DRAM Row Attribute (4b x 8)
0135                      *  defines the PAGE SIZE to be used
0136                      *  for the rank
0137                      *  7    reserved
0138                      *  6:4  row attr of odd rank, i.e. 1
0139                      *  3    reserved
0140                      *  2:0  row attr of even rank, i.e. 0
0141                      *
0142                      * 000 = unpopulated
0143                      * 001 = reserved
0144                      * 010 = 4KiB
0145                      * 011 = 8KiB
0146                      * 100 = 16KiB
0147                      * others = reserved
0148                      */
0149 #define I82975X_DRA_CH0R01      0x108
0150 #define I82975X_DRA_CH0R23      0x109
0151 #define I82975X_DRA_CH1R01      0x188
0152 #define I82975X_DRA_CH1R23      0x189
0153 
0154 
0155 #define I82975X_BNKARC  0x10e /* Type of device in each rank - Bank Arch (16b)
0156                      *
0157                      * 15:8  reserved
0158                      * 7:6  Rank 3 architecture
0159                      * 5:4  Rank 2 architecture
0160                      * 3:2  Rank 1 architecture
0161                      * 1:0  Rank 0 architecture
0162                      *
0163                      * 00 => 4 banks
0164                      * 01 => 8 banks
0165                      */
0166 #define I82975X_C0BNKARC    0x10e
0167 #define I82975X_C1BNKARC    0x18e
0168 
0169 
0170 
0171 #define I82975X_DRC     0x120 /* DRAM Controller Mode0 (32b)
0172                      *
0173                      * 31:30 reserved
0174                      * 29    init complete
0175                      * 28:11 reserved, according to Intel
0176                      *    22:21 number of channels
0177                      *      00=1 01=2 in 82875
0178                      *      seems to be ECC mode
0179                      *      bits in 82975 in Asus
0180                      *      P5W
0181                      *   19:18 Data Integ Mode
0182                      *      00=none 01=ECC in 82875
0183                      * 10:8  refresh mode
0184                      *  7    reserved
0185                      *  6:4  mode select
0186                      *  3:2  reserved
0187                      *  1:0  DRAM type 10=Second Revision
0188                      *      DDR2 SDRAM
0189                      *         00, 01, 11 reserved
0190                      */
0191 #define I82975X_DRC_CH0M0       0x120
0192 #define I82975X_DRC_CH1M0       0x1A0
0193 
0194 
0195 #define I82975X_DRC_M1  0x124 /* DRAM Controller Mode1 (32b)
0196                      * 31   0=Standard Address Map
0197                      *  1=Enhanced Address Map
0198                      * 30:0 reserved
0199                      */
0200 
0201 #define I82975X_DRC_CH0M1       0x124
0202 #define I82975X_DRC_CH1M1       0x1A4
0203 
0204 enum i82975x_chips {
0205     I82975X = 0,
0206 };
0207 
0208 struct i82975x_pvt {
0209     void __iomem *mch_window;
0210 };
0211 
0212 struct i82975x_dev_info {
0213     const char *ctl_name;
0214 };
0215 
0216 struct i82975x_error_info {
0217     u16 errsts;
0218     u32 eap;
0219     u8 des;
0220     u8 derrsyn;
0221     u16 errsts2;
0222     u8 chan;        /* the channel is bit 0 of EAP */
0223     u8 xeap;        /* extended eap bit */
0224 };
0225 
0226 static const struct i82975x_dev_info i82975x_devs[] = {
0227     [I82975X] = {
0228         .ctl_name = "i82975x"
0229     },
0230 };
0231 
0232 static struct pci_dev *mci_pdev;    /* init dev: in case that AGP code has
0233                      * already registered driver
0234                      */
0235 
0236 static int i82975x_registered = 1;
0237 
0238 static void i82975x_get_error_info(struct mem_ctl_info *mci,
0239         struct i82975x_error_info *info)
0240 {
0241     struct pci_dev *pdev;
0242 
0243     pdev = to_pci_dev(mci->pdev);
0244 
0245     /*
0246      * This is a mess because there is no atomic way to read all the
0247      * registers at once and the registers can transition from CE being
0248      * overwritten by UE.
0249      */
0250     pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts);
0251     pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
0252     pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
0253     pci_read_config_byte(pdev, I82975X_DES, &info->des);
0254     pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn);
0255     pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2);
0256 
0257     pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003);
0258 
0259     /*
0260      * If the error is the same then we can for both reads then
0261      * the first set of reads is valid.  If there is a change then
0262      * there is a CE no info and the second set of reads is valid
0263      * and should be UE info.
0264      */
0265     if (!(info->errsts2 & 0x0003))
0266         return;
0267 
0268     if ((info->errsts ^ info->errsts2) & 0x0003) {
0269         pci_read_config_dword(pdev, I82975X_EAP, &info->eap);
0270         pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap);
0271         pci_read_config_byte(pdev, I82975X_DES, &info->des);
0272         pci_read_config_byte(pdev, I82975X_DERRSYN,
0273                 &info->derrsyn);
0274     }
0275 }
0276 
0277 static int i82975x_process_error_info(struct mem_ctl_info *mci,
0278         struct i82975x_error_info *info, int handle_errors)
0279 {
0280     int row, chan;
0281     unsigned long offst, page;
0282 
0283     if (!(info->errsts2 & 0x0003))
0284         return 0;
0285 
0286     if (!handle_errors)
0287         return 1;
0288 
0289     if ((info->errsts ^ info->errsts2) & 0x0003) {
0290         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0291                      -1, -1, -1, "UE overwrote CE", "");
0292         info->errsts = info->errsts2;
0293     }
0294 
0295     page = (unsigned long) info->eap;
0296     page >>= 1;
0297     if (info->xeap & 1)
0298         page |= 0x80000000;
0299     page >>= (PAGE_SHIFT - 1);
0300     row = edac_mc_find_csrow_by_page(mci, page);
0301 
0302     if (row == -1)  {
0303         i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n"
0304             "\tXEAP=%u\n"
0305             "\t EAP=0x%08x\n"
0306             "\tPAGE=0x%08x\n",
0307             (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
0308         return 0;
0309     }
0310     chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1;
0311     offst = info->eap
0312             & ((1 << PAGE_SHIFT) -
0313                (1 << mci->csrows[row]->channels[chan]->dimm->grain));
0314 
0315     if (info->errsts & 0x0002)
0316         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0317                      page, offst, 0,
0318                      row, -1, -1,
0319                      "i82975x UE", "");
0320     else
0321         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0322                      page, offst, info->derrsyn,
0323                      row, chan ? chan : 0, -1,
0324                      "i82975x CE", "");
0325 
0326     return 1;
0327 }
0328 
0329 static void i82975x_check(struct mem_ctl_info *mci)
0330 {
0331     struct i82975x_error_info info;
0332 
0333     i82975x_get_error_info(mci, &info);
0334     i82975x_process_error_info(mci, &info, 1);
0335 }
0336 
0337 /* Return 1 if dual channel mode is active.  Else return 0. */
0338 static int dual_channel_active(void __iomem *mch_window)
0339 {
0340     /*
0341      * We treat interleaved-symmetric configuration as dual-channel - EAP's
0342      * bit-0 giving the channel of the error location.
0343      *
0344      * All other configurations are treated as single channel - the EAP's
0345      * bit-0 will resolve ok in symmetric area of mixed
0346      * (symmetric/asymmetric) configurations
0347      */
0348     u8  drb[4][2];
0349     int row;
0350     int    dualch;
0351 
0352     for (dualch = 1, row = 0; dualch && (row < 4); row++) {
0353         drb[row][0] = readb(mch_window + I82975X_DRB + row);
0354         drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80);
0355         dualch = dualch && (drb[row][0] == drb[row][1]);
0356     }
0357     return dualch;
0358 }
0359 
0360 static void i82975x_init_csrows(struct mem_ctl_info *mci,
0361         struct pci_dev *pdev, void __iomem *mch_window)
0362 {
0363     struct csrow_info *csrow;
0364     unsigned long last_cumul_size;
0365     u8 value;
0366     u32 cumul_size, nr_pages;
0367     int index, chan;
0368     struct dimm_info *dimm;
0369 
0370     last_cumul_size = 0;
0371 
0372     /*
0373      * 82875 comment:
0374      * The dram row boundary (DRB) reg values are boundary address
0375      * for each DRAM row with a granularity of 32 or 64MB (single/dual
0376      * channel operation).  DRB regs are cumulative; therefore DRB7 will
0377      * contain the total memory contained in all rows.
0378      *
0379      */
0380 
0381     for (index = 0; index < mci->nr_csrows; index++) {
0382         csrow = mci->csrows[index];
0383 
0384         value = readb(mch_window + I82975X_DRB + index +
0385                     ((index >= 4) ? 0x80 : 0));
0386         cumul_size = value;
0387         cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT);
0388         /*
0389          * Adjust cumul_size w.r.t number of channels
0390          *
0391          */
0392         if (csrow->nr_channels > 1)
0393             cumul_size <<= 1;
0394         edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
0395 
0396         nr_pages = cumul_size - last_cumul_size;
0397         if (!nr_pages)
0398             continue;
0399 
0400         /*
0401          * Initialise dram labels
0402          * index values:
0403          *   [0-7] for single-channel; i.e. csrow->nr_channels = 1
0404          *   [0-3] for dual-channel; i.e. csrow->nr_channels = 2
0405          */
0406         for (chan = 0; chan < csrow->nr_channels; chan++) {
0407             dimm = mci->csrows[index]->channels[chan]->dimm;
0408 
0409             dimm->nr_pages = nr_pages / csrow->nr_channels;
0410 
0411             snprintf(csrow->channels[chan]->dimm->label, EDAC_MC_LABEL_LEN, "DIMM %c%d",
0412                  (chan == 0) ? 'A' : 'B',
0413                  index);
0414             dimm->grain = 1 << 7;   /* 128Byte cache-line resolution */
0415 
0416             /* ECC is possible on i92975x ONLY with DEV_X8.  */
0417             dimm->dtype = DEV_X8;
0418 
0419             dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
0420             dimm->edac_mode = EDAC_SECDED; /* only supported */
0421         }
0422 
0423         csrow->first_page = last_cumul_size;
0424         csrow->last_page = cumul_size - 1;
0425         last_cumul_size = cumul_size;
0426     }
0427 }
0428 
0429 /* #define  i82975x_DEBUG_IOMEM */
0430 
0431 #ifdef i82975x_DEBUG_IOMEM
0432 static void i82975x_print_dram_timings(void __iomem *mch_window)
0433 {
0434     /*
0435      * The register meanings are from Intel specs;
0436      * (shows 13-5-5-5 for 800-DDR2)
0437      * Asus P5W Bios reports 15-5-4-4
0438      * What's your religion?
0439      */
0440     static const int caslats[4] = { 5, 4, 3, 6 };
0441     u32 dtreg[2];
0442 
0443     dtreg[0] = readl(mch_window + 0x114);
0444     dtreg[1] = readl(mch_window + 0x194);
0445     i82975x_printk(KERN_INFO, "DRAM Timings :     Ch0    Ch1\n"
0446         "                RAS Active Min = %d     %d\n"
0447         "                CAS latency    =  %d      %d\n"
0448         "                RAS to CAS     =  %d      %d\n"
0449         "                RAS precharge  =  %d      %d\n",
0450         (dtreg[0] >> 19 ) & 0x0f,
0451             (dtreg[1] >> 19) & 0x0f,
0452         caslats[(dtreg[0] >> 8) & 0x03],
0453             caslats[(dtreg[1] >> 8) & 0x03],
0454         ((dtreg[0] >> 4) & 0x07) + 2,
0455             ((dtreg[1] >> 4) & 0x07) + 2,
0456         (dtreg[0] & 0x07) + 2,
0457             (dtreg[1] & 0x07) + 2
0458     );
0459 
0460 }
0461 #endif
0462 
0463 static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
0464 {
0465     int rc = -ENODEV;
0466     struct mem_ctl_info *mci;
0467     struct edac_mc_layer layers[2];
0468     struct i82975x_pvt *pvt;
0469     void __iomem *mch_window;
0470     u32 mchbar;
0471     u32 drc[2];
0472     struct i82975x_error_info discard;
0473     int chans;
0474 #ifdef i82975x_DEBUG_IOMEM
0475     u8 c0drb[4];
0476     u8 c1drb[4];
0477 #endif
0478 
0479     edac_dbg(0, "\n");
0480 
0481     pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
0482     if (!(mchbar & 1)) {
0483         edac_dbg(3, "failed, MCHBAR disabled!\n");
0484         goto fail0;
0485     }
0486     mchbar &= 0xffffc000;   /* bits 31:14 used for 16K window */
0487     mch_window = ioremap(mchbar, 0x1000);
0488     if (!mch_window) {
0489         edac_dbg(3, "error ioremapping MCHBAR!\n");
0490         goto fail0;
0491     }
0492 
0493 #ifdef i82975x_DEBUG_IOMEM
0494     i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n",
0495                     mchbar, mch_window);
0496 
0497     c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0);
0498     c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1);
0499     c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2);
0500     c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3);
0501     c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0);
0502     c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1);
0503     c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2);
0504     c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3);
0505     i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]);
0506     i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]);
0507     i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]);
0508     i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]);
0509     i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]);
0510     i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]);
0511     i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]);
0512     i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]);
0513 #endif
0514 
0515     drc[0] = readl(mch_window + I82975X_DRC_CH0M0);
0516     drc[1] = readl(mch_window + I82975X_DRC_CH1M0);
0517 #ifdef i82975x_DEBUG_IOMEM
0518     i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0],
0519             ((drc[0] >> 21) & 3) == 1 ?
0520                 "ECC enabled" : "ECC disabled");
0521     i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1],
0522             ((drc[1] >> 21) & 3) == 1 ?
0523                 "ECC enabled" : "ECC disabled");
0524 
0525     i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n",
0526         readw(mch_window + I82975X_C0BNKARC));
0527     i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n",
0528         readw(mch_window + I82975X_C1BNKARC));
0529     i82975x_print_dram_timings(mch_window);
0530     goto fail1;
0531 #endif
0532     if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) {
0533         i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n");
0534         goto fail1;
0535     }
0536 
0537     chans = dual_channel_active(mch_window) + 1;
0538 
0539     /* assuming only one controller, index thus is 0 */
0540     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0541     layers[0].size = I82975X_NR_DIMMS;
0542     layers[0].is_virt_csrow = true;
0543     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0544     layers[1].size = I82975X_NR_CSROWS(chans);
0545     layers[1].is_virt_csrow = false;
0546     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
0547     if (!mci) {
0548         rc = -ENOMEM;
0549         goto fail1;
0550     }
0551 
0552     edac_dbg(3, "init mci\n");
0553     mci->pdev = &pdev->dev;
0554     mci->mtype_cap = MEM_FLAG_DDR2;
0555     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
0556     mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
0557     mci->mod_name = EDAC_MOD_STR;
0558     mci->ctl_name = i82975x_devs[dev_idx].ctl_name;
0559     mci->dev_name = pci_name(pdev);
0560     mci->edac_check = i82975x_check;
0561     mci->ctl_page_to_phys = NULL;
0562     edac_dbg(3, "init pvt\n");
0563     pvt = (struct i82975x_pvt *) mci->pvt_info;
0564     pvt->mch_window = mch_window;
0565     i82975x_init_csrows(mci, pdev, mch_window);
0566     mci->scrub_mode = SCRUB_HW_SRC;
0567     i82975x_get_error_info(mci, &discard);  /* clear counters */
0568 
0569     /* finalize this instance of memory controller with edac core */
0570     if (edac_mc_add_mc(mci)) {
0571         edac_dbg(3, "failed edac_mc_add_mc()\n");
0572         goto fail2;
0573     }
0574 
0575     /* get this far and it's successful */
0576     edac_dbg(3, "success\n");
0577     return 0;
0578 
0579 fail2:
0580     edac_mc_free(mci);
0581 
0582 fail1:
0583     iounmap(mch_window);
0584 fail0:
0585     return rc;
0586 }
0587 
0588 /* returns count (>= 0), or negative on error */
0589 static int i82975x_init_one(struct pci_dev *pdev,
0590                 const struct pci_device_id *ent)
0591 {
0592     int rc;
0593 
0594     edac_dbg(0, "\n");
0595 
0596     if (pci_enable_device(pdev) < 0)
0597         return -EIO;
0598 
0599     rc = i82975x_probe1(pdev, ent->driver_data);
0600 
0601     if (mci_pdev == NULL)
0602         mci_pdev = pci_dev_get(pdev);
0603 
0604     return rc;
0605 }
0606 
0607 static void i82975x_remove_one(struct pci_dev *pdev)
0608 {
0609     struct mem_ctl_info *mci;
0610     struct i82975x_pvt *pvt;
0611 
0612     edac_dbg(0, "\n");
0613 
0614     mci = edac_mc_del_mc(&pdev->dev);
0615     if (mci  == NULL)
0616         return;
0617 
0618     pvt = mci->pvt_info;
0619     if (pvt->mch_window)
0620         iounmap( pvt->mch_window );
0621 
0622     edac_mc_free(mci);
0623 }
0624 
0625 static const struct pci_device_id i82975x_pci_tbl[] = {
0626     {
0627         PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0628         I82975X
0629     },
0630     {
0631         0,
0632     }   /* 0 terminated list. */
0633 };
0634 
0635 MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl);
0636 
0637 static struct pci_driver i82975x_driver = {
0638     .name = EDAC_MOD_STR,
0639     .probe = i82975x_init_one,
0640     .remove = i82975x_remove_one,
0641     .id_table = i82975x_pci_tbl,
0642 };
0643 
0644 static int __init i82975x_init(void)
0645 {
0646     int pci_rc;
0647 
0648     edac_dbg(3, "\n");
0649 
0650     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0651     opstate_init();
0652 
0653     pci_rc = pci_register_driver(&i82975x_driver);
0654     if (pci_rc < 0)
0655         goto fail0;
0656 
0657     if (mci_pdev == NULL) {
0658         mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0659                 PCI_DEVICE_ID_INTEL_82975_0, NULL);
0660 
0661         if (!mci_pdev) {
0662             edac_dbg(0, "i82975x pci_get_device fail\n");
0663             pci_rc = -ENODEV;
0664             goto fail1;
0665         }
0666 
0667         pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
0668 
0669         if (pci_rc < 0) {
0670             edac_dbg(0, "i82975x init fail\n");
0671             pci_rc = -ENODEV;
0672             goto fail1;
0673         }
0674     }
0675 
0676     return 0;
0677 
0678 fail1:
0679     pci_unregister_driver(&i82975x_driver);
0680 
0681 fail0:
0682     pci_dev_put(mci_pdev);
0683     return pci_rc;
0684 }
0685 
0686 static void __exit i82975x_exit(void)
0687 {
0688     edac_dbg(3, "\n");
0689 
0690     pci_unregister_driver(&i82975x_driver);
0691 
0692     if (!i82975x_registered) {
0693         i82975x_remove_one(mci_pdev);
0694         pci_dev_put(mci_pdev);
0695     }
0696 }
0697 
0698 module_init(i82975x_init);
0699 module_exit(i82975x_exit);
0700 
0701 MODULE_LICENSE("GPL");
0702 MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>");
0703 MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers");
0704 
0705 module_param(edac_op_state, int, 0444);
0706 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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