drivers/edac/i82860_edac.c

0001 /*
0002  * Intel 82860 Memory Controller kernel module
0003  * (C) 2005 Red Hat (http://www.redhat.com)
0004  * This file may be distributed under the terms of the
0005  * GNU General Public License.
0006  *
0007  * Written by Ben Woodard <woodard@redhat.com>
0008  * shamelessly copied from and based upon the edac_i82875 driver
0009  * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/pci.h>
0015 #include <linux/pci_ids.h>
0016 #include <linux/edac.h>
0017 #include "edac_module.h"
0018
0019 #define EDAC_MOD_STR    "i82860_edac"
0020
0021 #define i82860_printk(level, fmt, arg...) \
0022     edac_printk(level, "i82860", fmt, ##arg)
0023
0024 #define i82860_mc_printk(mci, level, fmt, arg...) \
0025     edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
0026
0027 #ifndef PCI_DEVICE_ID_INTEL_82860_0
0028 #define PCI_DEVICE_ID_INTEL_82860_0 0x2531
0029 #endif              /* PCI_DEVICE_ID_INTEL_82860_0 */
0030
0031 #define I82860_MCHCFG 0x50
0032 #define I82860_GBA 0x60
0033 #define I82860_GBA_MASK 0x7FF
0034 #define I82860_GBA_SHIFT 24
0035 #define I82860_ERRSTS 0xC8
0036 #define I82860_EAP 0xE4
0037 #define I82860_DERRCTL_STS 0xE2
0038
0039 enum i82860_chips {
0040     I82860 = 0,
0041 };
0042
0043 struct i82860_dev_info {
0044     const char *ctl_name;
0045 };
0046
0047 struct i82860_error_info {
0048     u16 errsts;
0049     u32 eap;
0050     u16 derrsyn;
0051     u16 errsts2;
0052 };
0053
0054 static const struct i82860_dev_info i82860_devs[] = {
0055     [I82860] = {
0056         .ctl_name = "i82860"},
0057 };
0058
0059 static struct pci_dev *mci_pdev;    /* init dev: in case that AGP code
0060                      * has already registered driver
0061                      */
0062 static struct edac_pci_ctl_info *i82860_pci;
0063
0064 static void i82860_get_error_info(struct mem_ctl_info *mci,
0065                 struct i82860_error_info *info)
0066 {
0067     struct pci_dev *pdev;
0068
0069     pdev = to_pci_dev(mci->pdev);
0070
0071     /*
0072      * This is a mess because there is no atomic way to read all the
0073      * registers at once and the registers can transition from CE being
0074      * overwritten by UE.
0075      */
0076     pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
0077     pci_read_config_dword(pdev, I82860_EAP, &info->eap);
0078     pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
0079     pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
0080
0081     pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
0082
0083     /*
0084      * If the error is the same for both reads then the first set of reads
0085      * is valid.  If there is a change then there is a CE no info and the
0086      * second set of reads is valid and should be UE info.
0087      */
0088     if (!(info->errsts2 & 0x0003))
0089         return;
0090
0091     if ((info->errsts ^ info->errsts2) & 0x0003) {
0092         pci_read_config_dword(pdev, I82860_EAP, &info->eap);
0093         pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
0094     }
0095 }
0096
0097 static int i82860_process_error_info(struct mem_ctl_info *mci,
0098                 struct i82860_error_info *info,
0099                 int handle_errors)
0100 {
0101     struct dimm_info *dimm;
0102     int row;
0103
0104     if (!(info->errsts2 & 0x0003))
0105         return 0;
0106
0107     if (!handle_errors)
0108         return 1;
0109
0110     if ((info->errsts ^ info->errsts2) & 0x0003) {
0111         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0112                      -1, -1, -1, "UE overwrote CE", "");
0113         info->errsts = info->errsts2;
0114     }
0115
0116     info->eap >>= PAGE_SHIFT;
0117     row = edac_mc_find_csrow_by_page(mci, info->eap);
0118     dimm = mci->csrows[row]->channels[0]->dimm;
0119
0120     if (info->errsts & 0x0002)
0121         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0122                      info->eap, 0, 0,
0123                      dimm->location[0], dimm->location[1], -1,
0124                      "i82860 UE", "");
0125     else
0126         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0127                      info->eap, 0, info->derrsyn,
0128                      dimm->location[0], dimm->location[1], -1,
0129                      "i82860 CE", "");
0130
0131     return 1;
0132 }
0133
0134 static void i82860_check(struct mem_ctl_info *mci)
0135 {
0136     struct i82860_error_info info;
0137
0138     i82860_get_error_info(mci, &info);
0139     i82860_process_error_info(mci, &info, 1);
0140 }
0141
0142 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
0143 {
0144     unsigned long last_cumul_size;
0145     u16 mchcfg_ddim;    /* DRAM Data Integrity Mode 0=none, 2=edac */
0146     u16 value;
0147     u32 cumul_size;
0148     struct csrow_info *csrow;
0149     struct dimm_info *dimm;
0150     int index;
0151
0152     pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
0153     mchcfg_ddim = mchcfg_ddim & 0x180;
0154     last_cumul_size = 0;
0155
0156     /* The group row boundary (GRA) reg values are boundary address
0157      * for each DRAM row with a granularity of 16MB.  GRA regs are
0158      * cumulative; therefore GRA15 will contain the total memory contained
0159      * in all eight rows.
0160      */
0161     for (index = 0; index < mci->nr_csrows; index++) {
0162         csrow = mci->csrows[index];
0163         dimm = csrow->channels[0]->dimm;
0164
0165         pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
0166         cumul_size = (value & I82860_GBA_MASK) <<
0167             (I82860_GBA_SHIFT - PAGE_SHIFT);
0168         edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
0169
0170         if (cumul_size == last_cumul_size)
0171             continue;   /* not populated */
0172
0173         csrow->first_page = last_cumul_size;
0174         csrow->last_page = cumul_size - 1;
0175         dimm->nr_pages = cumul_size - last_cumul_size;
0176         last_cumul_size = cumul_size;
0177         dimm->grain = 1 << 12;  /* I82860_EAP has 4KiB reolution */
0178         dimm->mtype = MEM_RMBS;
0179         dimm->dtype = DEV_UNKNOWN;
0180         dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
0181     }
0182 }
0183
0184 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
0185 {
0186     struct mem_ctl_info *mci;
0187     struct edac_mc_layer layers[2];
0188     struct i82860_error_info discard;
0189
0190     /*
0191      * RDRAM has channels but these don't map onto the csrow abstraction.
0192      * According with the datasheet, there are 2 Rambus channels, supporting
0193      * up to 16 direct RDRAM devices.
0194      * The device groups from the GRA registers seem to map reasonably
0195      * well onto the notion of a chip select row.
0196      * There are 16 GRA registers and since the name is associated with
0197      * the channel and the GRA registers map to physical devices so we are
0198      * going to make 1 channel for group.
0199      */
0200     layers[0].type = EDAC_MC_LAYER_CHANNEL;
0201     layers[0].size = 2;
0202     layers[0].is_virt_csrow = true;
0203     layers[1].type = EDAC_MC_LAYER_SLOT;
0204     layers[1].size = 8;
0205     layers[1].is_virt_csrow = true;
0206     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
0207     if (!mci)
0208         return -ENOMEM;
0209
0210     edac_dbg(3, "init mci\n");
0211     mci->pdev = &pdev->dev;
0212     mci->mtype_cap = MEM_FLAG_DDR;
0213     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
0214     /* I"m not sure about this but I think that all RDRAM is SECDED */
0215     mci->edac_cap = EDAC_FLAG_SECDED;
0216     mci->mod_name = EDAC_MOD_STR;
0217     mci->ctl_name = i82860_devs[dev_idx].ctl_name;
0218     mci->dev_name = pci_name(pdev);
0219     mci->edac_check = i82860_check;
0220     mci->ctl_page_to_phys = NULL;
0221     i82860_init_csrows(mci, pdev);
0222     i82860_get_error_info(mci, &discard);   /* clear counters */
0223
0224     /* Here we assume that we will never see multiple instances of this
0225      * type of memory controller.  The ID is therefore hardcoded to 0.
0226      */
0227     if (edac_mc_add_mc(mci)) {
0228         edac_dbg(3, "failed edac_mc_add_mc()\n");
0229         goto fail;
0230     }
0231
0232     /* allocating generic PCI control info */
0233     i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
0234     if (!i82860_pci) {
0235         printk(KERN_WARNING
0236             "%s(): Unable to create PCI control\n",
0237             __func__);
0238         printk(KERN_WARNING
0239             "%s(): PCI error report via EDAC not setup\n",
0240             __func__);
0241     }
0242
0243     /* get this far and it's successful */
0244     edac_dbg(3, "success\n");
0245
0246     return 0;
0247
0248 fail:
0249     edac_mc_free(mci);
0250     return -ENODEV;
0251 }
0252
0253 /* returns count (>= 0), or negative on error */
0254 static int i82860_init_one(struct pci_dev *pdev,
0255                const struct pci_device_id *ent)
0256 {
0257     int rc;
0258
0259     edac_dbg(0, "\n");
0260     i82860_printk(KERN_INFO, "i82860 init one\n");
0261
0262     if (pci_enable_device(pdev) < 0)
0263         return -EIO;
0264
0265     rc = i82860_probe1(pdev, ent->driver_data);
0266
0267     if (rc == 0)
0268         mci_pdev = pci_dev_get(pdev);
0269
0270     return rc;
0271 }
0272
0273 static void i82860_remove_one(struct pci_dev *pdev)
0274 {
0275     struct mem_ctl_info *mci;
0276
0277     edac_dbg(0, "\n");
0278
0279     if (i82860_pci)
0280         edac_pci_release_generic_ctl(i82860_pci);
0281
0282     if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0283         return;
0284
0285     edac_mc_free(mci);
0286 }
0287
0288 static const struct pci_device_id i82860_pci_tbl[] = {
0289     {
0290      PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0291      I82860},
0292     {
0293      0,
0294      }          /* 0 terminated list. */
0295 };
0296
0297 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
0298
0299 static struct pci_driver i82860_driver = {
0300     .name = EDAC_MOD_STR,
0301     .probe = i82860_init_one,
0302     .remove = i82860_remove_one,
0303     .id_table = i82860_pci_tbl,
0304 };
0305
0306 static int __init i82860_init(void)
0307 {
0308     int pci_rc;
0309
0310     edac_dbg(3, "\n");
0311
0312        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0313        opstate_init();
0314
0315     if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
0316         goto fail0;
0317
0318     if (!mci_pdev) {
0319         mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0320                     PCI_DEVICE_ID_INTEL_82860_0, NULL);
0321
0322         if (mci_pdev == NULL) {
0323             edac_dbg(0, "860 pci_get_device fail\n");
0324             pci_rc = -ENODEV;
0325             goto fail1;
0326         }
0327
0328         pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
0329
0330         if (pci_rc < 0) {
0331             edac_dbg(0, "860 init fail\n");
0332             pci_rc = -ENODEV;
0333             goto fail1;
0334         }
0335     }
0336
0337     return 0;
0338
0339 fail1:
0340     pci_unregister_driver(&i82860_driver);
0341
0342 fail0:
0343     pci_dev_put(mci_pdev);
0344     return pci_rc;
0345 }
0346
0347 static void __exit i82860_exit(void)
0348 {
0349     edac_dbg(3, "\n");
0350     pci_unregister_driver(&i82860_driver);
0351     pci_dev_put(mci_pdev);
0352 }
0353
0354 module_init(i82860_init);
0355 module_exit(i82860_exit);
0356
0357 MODULE_LICENSE("GPL");
0358 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
0359         "Ben Woodard <woodard@redhat.com>");
0360 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
0361
0362 module_param(edac_op_state, int, 0444);
0363 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");