drivers/edac/i82443bxgx_edac.c

0001 /*
0002  * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
0003  * module (C) 2006 Tim Small
0004  *
0005  * This file may be distributed under the terms of the GNU General
0006  * Public License.
0007  *
0008  * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
0009  * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
0010  * others.
0011  *
0012  * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
0013  *
0014  * Written with reference to 82443BX Host Bridge Datasheet:
0015  * http://download.intel.com/design/chipsets/datashts/29063301.pdf
0016  * references to this document given in [].
0017  *
0018  * This module doesn't support the 440LX, but it may be possible to
0019  * make it do so (the 440LX's register definitions are different, but
0020  * not completely so - I haven't studied them in enough detail to know
0021  * how easy this would be).
0022  */
0023
0024 #include <linux/module.h>
0025 #include <linux/init.h>
0026
0027 #include <linux/pci.h>
0028 #include <linux/pci_ids.h>
0029
0030
0031 #include <linux/edac.h>
0032 #include "edac_module.h"
0033
0034 #define EDAC_MOD_STR    "i82443bxgx_edac"
0035
0036 /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
0037  * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
0038  * rows" "The 82443BX supports multiple-bit error detection and
0039  * single-bit error correction when ECC mode is enabled and
0040  * single/multi-bit error detection when correction is disabled.
0041  * During writes to the DRAM, the 82443BX generates ECC for the data
0042  * on a QWord basis. Partial QWord writes require a read-modify-write
0043  * cycle when ECC is enabled."
0044 */
0045
0046 /* "Additionally, the 82443BX ensures that the data is corrected in
0047  * main memory so that accumulation of errors is prevented. Another
0048  * error within the same QWord would result in a double-bit error
0049  * which is unrecoverable. This is known as hardware scrubbing since
0050  * it requires no software intervention to correct the data in memory."
0051  */
0052
0053 /* [Also see page 100 (section 4.3), "DRAM Interface"]
0054  * [Also see page 112 (section 4.6.1.4), ECC]
0055  */
0056
0057 #define I82443BXGX_NR_CSROWS 8
0058 #define I82443BXGX_NR_CHANS  1
0059 #define I82443BXGX_NR_DIMMS  4
0060
0061 /* 82443 PCI Device 0 */
0062 #define I82443BXGX_NBXCFG 0x50  /* 32bit register starting at this PCI
0063                  * config space offset */
0064 #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24  /* Array of bits, zero if
0065                          * row is non-ECC */
0066 #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12   /* 2 bits,00=100MHz,10=66 MHz */
0067
0068 #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7   /* 2 bits:       */
0069 #define I82443BXGX_NBXCFG_INTEGRITY_NONE   0x0  /* 00 = Non-ECC */
0070 #define I82443BXGX_NBXCFG_INTEGRITY_EC     0x1  /* 01 = EC (only) */
0071 #define I82443BXGX_NBXCFG_INTEGRITY_ECC    0x2  /* 10 = ECC */
0072 #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB  0x3  /* 11 = ECC + HW Scrub */
0073
0074 #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE  6
0075
0076 /* 82443 PCI Device 0 */
0077 #define I82443BXGX_EAP   0x80   /* 32bit register starting at this PCI
0078                  * config space offset, Error Address
0079                  * Pointer Register */
0080 #define I82443BXGX_EAP_OFFSET_EAP  12   /* High 20 bits of error address */
0081 #define I82443BXGX_EAP_OFFSET_MBE  BIT(1)   /* Err at EAP was multi-bit (W1TC) */
0082 #define I82443BXGX_EAP_OFFSET_SBE  BIT(0)   /* Err at EAP was single-bit (W1TC) */
0083
0084 #define I82443BXGX_ERRCMD  0x90 /* 8bit register starting at this PCI
0085                  * config space offset. */
0086 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
0087 #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
0088
0089 #define I82443BXGX_ERRSTS  0x91 /* 16bit register starting at this PCI
0090                  * config space offset. */
0091 #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5    /* 3 bits - first err row multibit */
0092 #define I82443BXGX_ERRSTS_OFFSET_MEF   BIT(4)   /* 1 = MBE occurred */
0093 #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1    /* 3 bits - first err row singlebit */
0094 #define I82443BXGX_ERRSTS_OFFSET_SEF   BIT(0)   /* 1 = SBE occurred */
0095
0096 #define I82443BXGX_DRAMC 0x57   /* 8bit register starting at this PCI
0097                  * config space offset. */
0098 #define I82443BXGX_DRAMC_OFFSET_DT 3    /* 2 bits, DRAM Type */
0099 #define I82443BXGX_DRAMC_DRAM_IS_EDO 0  /* 00 = EDO */
0100 #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1    /* 01 = SDRAM */
0101 #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2   /* 10 = Registered SDRAM */
0102
0103 #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
0104                  * config space offset. */
0105
0106 /* FIXME - don't poll when ECC disabled? */
0107
0108 struct i82443bxgx_edacmc_error_info {
0109     u32 eap;
0110 };
0111
0112 static struct edac_pci_ctl_info *i82443bxgx_pci;
0113
0114 static struct pci_dev *mci_pdev;    /* init dev: in case that AGP code has
0115                      * already registered driver
0116                      */
0117
0118 static int i82443bxgx_registered = 1;
0119
0120 static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
0121                 struct i82443bxgx_edacmc_error_info
0122                 *info)
0123 {
0124     struct pci_dev *pdev;
0125     pdev = to_pci_dev(mci->pdev);
0126     pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
0127     if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
0128         /* Clear error to allow next error to be reported [p.61] */
0129         pci_write_bits32(pdev, I82443BXGX_EAP,
0130                  I82443BXGX_EAP_OFFSET_SBE,
0131                  I82443BXGX_EAP_OFFSET_SBE);
0132
0133     if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
0134         /* Clear error to allow next error to be reported [p.61] */
0135         pci_write_bits32(pdev, I82443BXGX_EAP,
0136                  I82443BXGX_EAP_OFFSET_MBE,
0137                  I82443BXGX_EAP_OFFSET_MBE);
0138 }
0139
0140 static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
0141                         struct
0142                         i82443bxgx_edacmc_error_info
0143                         *info, int handle_errors)
0144 {
0145     int error_found = 0;
0146     u32 eapaddr, page, pageoffset;
0147
0148     /* bits 30:12 hold the 4kb block in which the error occurred
0149      * [p.61] */
0150     eapaddr = (info->eap & 0xfffff000);
0151     page = eapaddr >> PAGE_SHIFT;
0152     pageoffset = eapaddr - (page << PAGE_SHIFT);
0153
0154     if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
0155         error_found = 1;
0156         if (handle_errors)
0157             edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0158                          page, pageoffset, 0,
0159                          edac_mc_find_csrow_by_page(mci, page),
0160                          0, -1, mci->ctl_name, "");
0161     }
0162
0163     if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
0164         error_found = 1;
0165         if (handle_errors)
0166             edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0167                          page, pageoffset, 0,
0168                          edac_mc_find_csrow_by_page(mci, page),
0169                          0, -1, mci->ctl_name, "");
0170     }
0171
0172     return error_found;
0173 }
0174
0175 static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
0176 {
0177     struct i82443bxgx_edacmc_error_info info;
0178
0179     i82443bxgx_edacmc_get_error_info(mci, &info);
0180     i82443bxgx_edacmc_process_error_info(mci, &info, 1);
0181 }
0182
0183 static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
0184                 struct pci_dev *pdev,
0185                 enum edac_type edac_mode,
0186                 enum mem_type mtype)
0187 {
0188     struct csrow_info *csrow;
0189     struct dimm_info *dimm;
0190     int index;
0191     u8 drbar, dramc;
0192     u32 row_base, row_high_limit, row_high_limit_last;
0193
0194     pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
0195     row_high_limit_last = 0;
0196     for (index = 0; index < mci->nr_csrows; index++) {
0197         csrow = mci->csrows[index];
0198         dimm = csrow->channels[0]->dimm;
0199
0200         pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
0201         edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
0202              mci->mc_idx, index, drbar);
0203         row_high_limit = ((u32) drbar << 23);
0204         /* find the DRAM Chip Select Base address and mask */
0205         edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
0206              mci->mc_idx, index, row_high_limit,
0207              row_high_limit_last);
0208
0209         /* 440GX goes to 2GB, represented with a DRB of 0. */
0210         if (row_high_limit_last && !row_high_limit)
0211             row_high_limit = 1UL << 31;
0212
0213         /* This row is empty [p.49] */
0214         if (row_high_limit == row_high_limit_last)
0215             continue;
0216         row_base = row_high_limit_last;
0217         csrow->first_page = row_base >> PAGE_SHIFT;
0218         csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
0219         dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
0220         /* EAP reports in 4kilobyte granularity [61] */
0221         dimm->grain = 1 << 12;
0222         dimm->mtype = mtype;
0223         /* I don't think 440BX can tell you device type? FIXME? */
0224         dimm->dtype = DEV_UNKNOWN;
0225         /* Mode is global to all rows on 440BX */
0226         dimm->edac_mode = edac_mode;
0227         row_high_limit_last = row_high_limit;
0228     }
0229 }
0230
0231 static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
0232 {
0233     struct mem_ctl_info *mci;
0234     struct edac_mc_layer layers[2];
0235     u8 dramc;
0236     u32 nbxcfg, ecc_mode;
0237     enum mem_type mtype;
0238     enum edac_type edac_mode;
0239
0240     edac_dbg(0, "MC:\n");
0241
0242     /* Something is really hosed if PCI config space reads from
0243      * the MC aren't working.
0244      */
0245     if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
0246         return -EIO;
0247
0248     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0249     layers[0].size = I82443BXGX_NR_CSROWS;
0250     layers[0].is_virt_csrow = true;
0251     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0252     layers[1].size = I82443BXGX_NR_CHANS;
0253     layers[1].is_virt_csrow = false;
0254     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
0255     if (mci == NULL)
0256         return -ENOMEM;
0257
0258     edac_dbg(0, "MC: mci = %p\n", mci);
0259     mci->pdev = &pdev->dev;
0260     mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
0261     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
0262     pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
0263     switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
0264     case I82443BXGX_DRAMC_DRAM_IS_EDO:
0265         mtype = MEM_EDO;
0266         break;
0267     case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
0268         mtype = MEM_SDR;
0269         break;
0270     case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
0271         mtype = MEM_RDR;
0272         break;
0273     default:
0274         edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
0275         mtype = -MEM_UNKNOWN;
0276     }
0277
0278     if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
0279         mci->edac_cap = mci->edac_ctl_cap;
0280     else
0281         mci->edac_cap = EDAC_FLAG_NONE;
0282
0283     mci->scrub_cap = SCRUB_FLAG_HW_SRC;
0284     pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
0285     ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
0286         (BIT(0) | BIT(1)));
0287
0288     mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
0289         ? SCRUB_HW_SRC : SCRUB_NONE;
0290
0291     switch (ecc_mode) {
0292     case I82443BXGX_NBXCFG_INTEGRITY_NONE:
0293         edac_mode = EDAC_NONE;
0294         break;
0295     case I82443BXGX_NBXCFG_INTEGRITY_EC:
0296         edac_mode = EDAC_EC;
0297         break;
0298     case I82443BXGX_NBXCFG_INTEGRITY_ECC:
0299     case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
0300         edac_mode = EDAC_SECDED;
0301         break;
0302     default:
0303         edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
0304         edac_mode = EDAC_UNKNOWN;
0305         break;
0306     }
0307
0308     i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
0309
0310     /* Many BIOSes don't clear error flags on boot, so do this
0311      * here, or we get "phantom" errors occurring at module-load
0312      * time. */
0313     pci_write_bits32(pdev, I82443BXGX_EAP,
0314             (I82443BXGX_EAP_OFFSET_SBE |
0315                 I82443BXGX_EAP_OFFSET_MBE),
0316             (I82443BXGX_EAP_OFFSET_SBE |
0317                 I82443BXGX_EAP_OFFSET_MBE));
0318
0319     mci->mod_name = EDAC_MOD_STR;
0320     mci->ctl_name = "I82443BXGX";
0321     mci->dev_name = pci_name(pdev);
0322     mci->edac_check = i82443bxgx_edacmc_check;
0323     mci->ctl_page_to_phys = NULL;
0324
0325     if (edac_mc_add_mc(mci)) {
0326         edac_dbg(3, "failed edac_mc_add_mc()\n");
0327         goto fail;
0328     }
0329
0330     /* allocating generic PCI control info */
0331     i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
0332     if (!i82443bxgx_pci) {
0333         printk(KERN_WARNING
0334             "%s(): Unable to create PCI control\n",
0335             __func__);
0336         printk(KERN_WARNING
0337             "%s(): PCI error report via EDAC not setup\n",
0338             __func__);
0339     }
0340
0341     edac_dbg(3, "MC: success\n");
0342     return 0;
0343
0344 fail:
0345     edac_mc_free(mci);
0346     return -ENODEV;
0347 }
0348
0349 /* returns count (>= 0), or negative on error */
0350 static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
0351                       const struct pci_device_id *ent)
0352 {
0353     int rc;
0354
0355     edac_dbg(0, "MC:\n");
0356
0357     /* don't need to call pci_enable_device() */
0358     rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
0359
0360     if (mci_pdev == NULL)
0361         mci_pdev = pci_dev_get(pdev);
0362
0363     return rc;
0364 }
0365
0366 static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
0367 {
0368     struct mem_ctl_info *mci;
0369
0370     edac_dbg(0, "\n");
0371
0372     if (i82443bxgx_pci)
0373         edac_pci_release_generic_ctl(i82443bxgx_pci);
0374
0375     if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0376         return;
0377
0378     edac_mc_free(mci);
0379 }
0380
0381 static const struct pci_device_id i82443bxgx_pci_tbl[] = {
0382     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
0383     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
0384     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
0385     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
0386     {0,}            /* 0 terminated list. */
0387 };
0388
0389 MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
0390
0391 static struct pci_driver i82443bxgx_edacmc_driver = {
0392     .name = EDAC_MOD_STR,
0393     .probe = i82443bxgx_edacmc_init_one,
0394     .remove = i82443bxgx_edacmc_remove_one,
0395     .id_table = i82443bxgx_pci_tbl,
0396 };
0397
0398 static int __init i82443bxgx_edacmc_init(void)
0399 {
0400     int pci_rc;
0401        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0402        opstate_init();
0403
0404     pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
0405     if (pci_rc < 0)
0406         goto fail0;
0407
0408     if (mci_pdev == NULL) {
0409         const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
0410         int i = 0;
0411         i82443bxgx_registered = 0;
0412
0413         while (mci_pdev == NULL && id->vendor != 0) {
0414             mci_pdev = pci_get_device(id->vendor,
0415                     id->device, NULL);
0416             i++;
0417             id = &i82443bxgx_pci_tbl[i];
0418         }
0419         if (!mci_pdev) {
0420             edac_dbg(0, "i82443bxgx pci_get_device fail\n");
0421             pci_rc = -ENODEV;
0422             goto fail1;
0423         }
0424
0425         pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
0426
0427         if (pci_rc < 0) {
0428             edac_dbg(0, "i82443bxgx init fail\n");
0429             pci_rc = -ENODEV;
0430             goto fail1;
0431         }
0432     }
0433
0434     return 0;
0435
0436 fail1:
0437     pci_unregister_driver(&i82443bxgx_edacmc_driver);
0438
0439 fail0:
0440     pci_dev_put(mci_pdev);
0441     return pci_rc;
0442 }
0443
0444 static void __exit i82443bxgx_edacmc_exit(void)
0445 {
0446     pci_unregister_driver(&i82443bxgx_edacmc_driver);
0447
0448     if (!i82443bxgx_registered)
0449         i82443bxgx_edacmc_remove_one(mci_pdev);
0450
0451     pci_dev_put(mci_pdev);
0452 }
0453
0454 module_init(i82443bxgx_edacmc_init);
0455 module_exit(i82443bxgx_edacmc_exit);
0456
0457 MODULE_LICENSE("GPL");
0458 MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
0459 MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
0460
0461 module_param(edac_op_state, int, 0444);
0462 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");