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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel 7300 class Memory Controllers kernel module (Clarksboro)
0004  *
0005  * Copyright (c) 2010 by:
0006  *   Mauro Carvalho Chehab
0007  *
0008  * Red Hat Inc. https://www.redhat.com
0009  *
0010  * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
0011  *  http://www.intel.com/Assets/PDF/datasheet/318082.pdf
0012  *
0013  * TODO: The chipset allow checking for PCI Express errors also. Currently,
0014  *   the driver covers only memory error errors
0015  *
0016  * This driver uses "csrows" EDAC attribute to represent DIMM slot#
0017  */
0018 
0019 #include <linux/module.h>
0020 #include <linux/init.h>
0021 #include <linux/pci.h>
0022 #include <linux/pci_ids.h>
0023 #include <linux/slab.h>
0024 #include <linux/edac.h>
0025 #include <linux/mmzone.h>
0026 
0027 #include "edac_module.h"
0028 
0029 /*
0030  * Alter this version for the I7300 module when modifications are made
0031  */
0032 #define I7300_REVISION    " Ver: 1.0.0"
0033 
0034 #define EDAC_MOD_STR      "i7300_edac"
0035 
0036 #define i7300_printk(level, fmt, arg...) \
0037     edac_printk(level, "i7300", fmt, ##arg)
0038 
0039 #define i7300_mc_printk(mci, level, fmt, arg...) \
0040     edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
0041 
0042 /***********************************************
0043  * i7300 Limit constants Structs and static vars
0044  ***********************************************/
0045 
0046 /*
0047  * Memory topology is organized as:
0048  *  Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
0049  *  Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
0050  * Each channel can have to 8 DIMM sets (called as SLOTS)
0051  * Slots should generally be filled in pairs
0052  *  Except on Single Channel mode of operation
0053  *      just slot 0/channel0 filled on this mode
0054  *  On normal operation mode, the two channels on a branch should be
0055  *      filled together for the same SLOT#
0056  * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
0057  *      channels on both branches should be filled
0058  */
0059 
0060 /* Limits for i7300 */
0061 #define MAX_SLOTS       8
0062 #define MAX_BRANCHES        2
0063 #define MAX_CH_PER_BRANCH   2
0064 #define MAX_CHANNELS        (MAX_CH_PER_BRANCH * MAX_BRANCHES)
0065 #define MAX_MIR         3
0066 
0067 #define to_channel(ch, branch)  ((((branch)) << 1) | (ch))
0068 
0069 #define to_csrow(slot, ch, branch)                  \
0070         (to_channel(ch, branch) | ((slot) << 2))
0071 
0072 /* Device name and register DID (Device ID) */
0073 struct i7300_dev_info {
0074     const char *ctl_name;   /* name for this device */
0075     u16 fsb_mapping_errors; /* DID for the branchmap,control */
0076 };
0077 
0078 /* Table of devices attributes supported by this driver */
0079 static const struct i7300_dev_info i7300_devs[] = {
0080     {
0081         .ctl_name = "I7300",
0082         .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
0083     },
0084 };
0085 
0086 struct i7300_dimm_info {
0087     int megabytes;      /* size, 0 means not present  */
0088 };
0089 
0090 /* driver private data structure */
0091 struct i7300_pvt {
0092     struct pci_dev *pci_dev_16_0_fsb_ctlr;      /* 16.0 */
0093     struct pci_dev *pci_dev_16_1_fsb_addr_map;  /* 16.1 */
0094     struct pci_dev *pci_dev_16_2_fsb_err_regs;  /* 16.2 */
0095     struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES];  /* 21.0  and 22.0 */
0096 
0097     u16 tolm;               /* top of low memory */
0098     u64 ambase;             /* AMB BAR */
0099 
0100     u32 mc_settings;            /* Report several settings */
0101     u32 mc_settings_a;
0102 
0103     u16 mir[MAX_MIR];           /* Memory Interleave Reg*/
0104 
0105     u16 mtr[MAX_SLOTS][MAX_BRANCHES];   /* Memory Technlogy Reg */
0106     u16 ambpresent[MAX_CHANNELS];       /* AMB present regs */
0107 
0108     /* DIMM information matrix, allocating architecture maximums */
0109     struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
0110 
0111     /* Temporary buffer for use when preparing error messages */
0112     char *tmp_prt_buffer;
0113 };
0114 
0115 /* FIXME: Why do we need to have this static? */
0116 static struct edac_pci_ctl_info *i7300_pci;
0117 
0118 /***************************************************
0119  * i7300 Register definitions for memory enumeration
0120  ***************************************************/
0121 
0122 /*
0123  * Device 16,
0124  * Function 0: System Address (not documented)
0125  * Function 1: Memory Branch Map, Control, Errors Register
0126  */
0127 
0128     /* OFFSETS for Function 0 */
0129 #define AMBASE          0x48 /* AMB Mem Mapped Reg Region Base */
0130 #define MAXCH           0x56 /* Max Channel Number */
0131 #define MAXDIMMPERCH        0x57 /* Max DIMM PER Channel Number */
0132 
0133     /* OFFSETS for Function 1 */
0134 #define MC_SETTINGS     0x40
0135   #define IS_MIRRORED(mc)       ((mc) & (1 << 16))
0136   #define IS_ECC_ENABLED(mc)        ((mc) & (1 << 5))
0137   #define IS_RETRY_ENABLED(mc)      ((mc) & (1 << 31))
0138   #define IS_SCRBALGO_ENHANCED(mc)  ((mc) & (1 << 8))
0139 
0140 #define MC_SETTINGS_A       0x58
0141   #define IS_SINGLE_MODE(mca)       ((mca) & (1 << 14))
0142 
0143 #define TOLM            0x6C
0144 
0145 #define MIR0            0x80
0146 #define MIR1            0x84
0147 #define MIR2            0x88
0148 
0149 /*
0150  * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
0151  * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
0152  * seems that we cannot use this information directly for the same usage.
0153  * Each memory slot may have up to 2 AMB interfaces, one for income and another
0154  * for outcome interface to the next slot.
0155  * For now, the driver just stores the AMB present registers, but rely only at
0156  * the MTR info to detect memory.
0157  * Datasheet is also not clear about how to map each AMBPRESENT registers to
0158  * one of the 4 available channels.
0159  */
0160 #define AMBPRESENT_0    0x64
0161 #define AMBPRESENT_1    0x66
0162 
0163 static const u16 mtr_regs[MAX_SLOTS] = {
0164     0x80, 0x84, 0x88, 0x8c,
0165     0x82, 0x86, 0x8a, 0x8e
0166 };
0167 
0168 /*
0169  * Defines to extract the vaious fields from the
0170  *  MTRx - Memory Technology Registers
0171  */
0172 #define MTR_DIMMS_PRESENT(mtr)      ((mtr) & (1 << 8))
0173 #define MTR_DIMMS_ETHROTTLE(mtr)    ((mtr) & (1 << 7))
0174 #define MTR_DRAM_WIDTH(mtr)     (((mtr) & (1 << 6)) ? 8 : 4)
0175 #define MTR_DRAM_BANKS(mtr)     (((mtr) & (1 << 5)) ? 8 : 4)
0176 #define MTR_DIMM_RANKS(mtr)     (((mtr) & (1 << 4)) ? 1 : 0)
0177 #define MTR_DIMM_ROWS(mtr)      (((mtr) >> 2) & 0x3)
0178 #define MTR_DRAM_BANKS_ADDR_BITS    2
0179 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
0180 #define MTR_DIMM_COLS(mtr)      ((mtr) & 0x3)
0181 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
0182 
0183 /************************************************
0184  * i7300 Register definitions for error detection
0185  ************************************************/
0186 
0187 /*
0188  * Device 16.1: FBD Error Registers
0189  */
0190 #define FERR_FAT_FBD    0x98
0191 static const char *ferr_fat_fbd_name[] = {
0192     [22] = "Non-Redundant Fast Reset Timeout",
0193     [2]  = ">Tmid Thermal event with intelligent throttling disabled",
0194     [1]  = "Memory or FBD configuration CRC read error",
0195     [0]  = "Memory Write error on non-redundant retry or "
0196            "FBD configuration Write error on retry",
0197 };
0198 #define GET_FBD_FAT_IDX(fbderr) (((fbderr) >> 28) & 3)
0199 #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22))
0200 
0201 #define FERR_NF_FBD 0xa0
0202 static const char *ferr_nf_fbd_name[] = {
0203     [24] = "DIMM-Spare Copy Completed",
0204     [23] = "DIMM-Spare Copy Initiated",
0205     [22] = "Redundant Fast Reset Timeout",
0206     [21] = "Memory Write error on redundant retry",
0207     [18] = "SPD protocol Error",
0208     [17] = "FBD Northbound parity error on FBD Sync Status",
0209     [16] = "Correctable Patrol Data ECC",
0210     [15] = "Correctable Resilver- or Spare-Copy Data ECC",
0211     [14] = "Correctable Mirrored Demand Data ECC",
0212     [13] = "Correctable Non-Mirrored Demand Data ECC",
0213     [11] = "Memory or FBD configuration CRC read error",
0214     [10] = "FBD Configuration Write error on first attempt",
0215     [9]  = "Memory Write error on first attempt",
0216     [8]  = "Non-Aliased Uncorrectable Patrol Data ECC",
0217     [7]  = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
0218     [6]  = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
0219     [5]  = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
0220     [4]  = "Aliased Uncorrectable Patrol Data ECC",
0221     [3]  = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
0222     [2]  = "Aliased Uncorrectable Mirrored Demand Data ECC",
0223     [1]  = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
0224     [0]  = "Uncorrectable Data ECC on Replay",
0225 };
0226 #define GET_FBD_NF_IDX(fbderr)  (((fbderr) >> 28) & 3)
0227 #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
0228                   (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
0229                   (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
0230                   (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
0231                   (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
0232                   (1 << 1)  | (1 << 0))
0233 
0234 #define EMASK_FBD   0xa8
0235 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
0236                 (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
0237                 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
0238                 (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
0239                 (1 << 9)  | (1 << 8)  | (1 << 7)  | (1 << 6)  |\
0240                 (1 << 5)  | (1 << 4)  | (1 << 3)  | (1 << 2)  |\
0241                 (1 << 1)  | (1 << 0))
0242 
0243 /*
0244  * Device 16.2: Global Error Registers
0245  */
0246 
0247 #define FERR_GLOBAL_HI  0x48
0248 static const char *ferr_global_hi_name[] = {
0249     [3] = "FSB 3 Fatal Error",
0250     [2] = "FSB 2 Fatal Error",
0251     [1] = "FSB 1 Fatal Error",
0252     [0] = "FSB 0 Fatal Error",
0253 };
0254 #define ferr_global_hi_is_fatal(errno)  1
0255 
0256 #define FERR_GLOBAL_LO  0x40
0257 static const char *ferr_global_lo_name[] = {
0258     [31] = "Internal MCH Fatal Error",
0259     [30] = "Intel QuickData Technology Device Fatal Error",
0260     [29] = "FSB1 Fatal Error",
0261     [28] = "FSB0 Fatal Error",
0262     [27] = "FBD Channel 3 Fatal Error",
0263     [26] = "FBD Channel 2 Fatal Error",
0264     [25] = "FBD Channel 1 Fatal Error",
0265     [24] = "FBD Channel 0 Fatal Error",
0266     [23] = "PCI Express Device 7Fatal Error",
0267     [22] = "PCI Express Device 6 Fatal Error",
0268     [21] = "PCI Express Device 5 Fatal Error",
0269     [20] = "PCI Express Device 4 Fatal Error",
0270     [19] = "PCI Express Device 3 Fatal Error",
0271     [18] = "PCI Express Device 2 Fatal Error",
0272     [17] = "PCI Express Device 1 Fatal Error",
0273     [16] = "ESI Fatal Error",
0274     [15] = "Internal MCH Non-Fatal Error",
0275     [14] = "Intel QuickData Technology Device Non Fatal Error",
0276     [13] = "FSB1 Non-Fatal Error",
0277     [12] = "FSB 0 Non-Fatal Error",
0278     [11] = "FBD Channel 3 Non-Fatal Error",
0279     [10] = "FBD Channel 2 Non-Fatal Error",
0280     [9]  = "FBD Channel 1 Non-Fatal Error",
0281     [8]  = "FBD Channel 0 Non-Fatal Error",
0282     [7]  = "PCI Express Device 7 Non-Fatal Error",
0283     [6]  = "PCI Express Device 6 Non-Fatal Error",
0284     [5]  = "PCI Express Device 5 Non-Fatal Error",
0285     [4]  = "PCI Express Device 4 Non-Fatal Error",
0286     [3]  = "PCI Express Device 3 Non-Fatal Error",
0287     [2]  = "PCI Express Device 2 Non-Fatal Error",
0288     [1]  = "PCI Express Device 1 Non-Fatal Error",
0289     [0]  = "ESI Non-Fatal Error",
0290 };
0291 #define ferr_global_lo_is_fatal(errno)  ((errno < 16) ? 0 : 1)
0292 
0293 #define NRECMEMA    0xbe
0294   #define NRECMEMA_BANK(v)  (((v) >> 12) & 7)
0295   #define NRECMEMA_RANK(v)  (((v) >> 8) & 15)
0296 
0297 #define NRECMEMB    0xc0
0298   #define NRECMEMB_IS_WR(v) ((v) & (1 << 31))
0299   #define NRECMEMB_CAS(v)   (((v) >> 16) & 0x1fff)
0300   #define NRECMEMB_RAS(v)   ((v) & 0xffff)
0301 
0302 #define REDMEMA     0xdc
0303 
0304 #define REDMEMB     0x7c
0305 
0306 #define RECMEMA     0xe0
0307   #define RECMEMA_BANK(v)   (((v) >> 12) & 7)
0308   #define RECMEMA_RANK(v)   (((v) >> 8) & 15)
0309 
0310 #define RECMEMB     0xe4
0311   #define RECMEMB_IS_WR(v)  ((v) & (1 << 31))
0312   #define RECMEMB_CAS(v)    (((v) >> 16) & 0x1fff)
0313   #define RECMEMB_RAS(v)    ((v) & 0xffff)
0314 
0315 /********************************************
0316  * i7300 Functions related to error detection
0317  ********************************************/
0318 
0319 /**
0320  * get_err_from_table() - Gets the error message from a table
0321  * @table:  table name (array of char *)
0322  * @size:   number of elements at the table
0323  * @pos:    position of the element to be returned
0324  *
0325  * This is a small routine that gets the pos-th element of a table. If the
0326  * element doesn't exist (or it is empty), it returns "reserved".
0327  * Instead of calling it directly, the better is to call via the macro
0328  * GET_ERR_FROM_TABLE(), that automatically checks the table size via
0329  * ARRAY_SIZE() macro
0330  */
0331 static const char *get_err_from_table(const char *table[], int size, int pos)
0332 {
0333     if (unlikely(pos >= size))
0334         return "Reserved";
0335 
0336     if (unlikely(!table[pos]))
0337         return "Reserved";
0338 
0339     return table[pos];
0340 }
0341 
0342 #define GET_ERR_FROM_TABLE(table, pos)              \
0343     get_err_from_table(table, ARRAY_SIZE(table), pos)
0344 
0345 /**
0346  * i7300_process_error_global() - Retrieve the hardware error information from
0347  *                the hardware global error registers and
0348  *                sends it to dmesg
0349  * @mci: struct mem_ctl_info pointer
0350  */
0351 static void i7300_process_error_global(struct mem_ctl_info *mci)
0352 {
0353     struct i7300_pvt *pvt;
0354     u32 errnum, error_reg;
0355     unsigned long errors;
0356     const char *specific;
0357     bool is_fatal;
0358 
0359     pvt = mci->pvt_info;
0360 
0361     /* read in the 1st FATAL error register */
0362     pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0363                   FERR_GLOBAL_HI, &error_reg);
0364     if (unlikely(error_reg)) {
0365         errors = error_reg;
0366         errnum = find_first_bit(&errors,
0367                     ARRAY_SIZE(ferr_global_hi_name));
0368         specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
0369         is_fatal = ferr_global_hi_is_fatal(errnum);
0370 
0371         /* Clear the error bit */
0372         pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0373                        FERR_GLOBAL_HI, error_reg);
0374 
0375         goto error_global;
0376     }
0377 
0378     pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0379                   FERR_GLOBAL_LO, &error_reg);
0380     if (unlikely(error_reg)) {
0381         errors = error_reg;
0382         errnum = find_first_bit(&errors,
0383                     ARRAY_SIZE(ferr_global_lo_name));
0384         specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
0385         is_fatal = ferr_global_lo_is_fatal(errnum);
0386 
0387         /* Clear the error bit */
0388         pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0389                        FERR_GLOBAL_LO, error_reg);
0390 
0391         goto error_global;
0392     }
0393     return;
0394 
0395 error_global:
0396     i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
0397             is_fatal ? "Fatal" : "NOT fatal", specific);
0398 }
0399 
0400 /**
0401  * i7300_process_fbd_error() - Retrieve the hardware error information from
0402  *                 the FBD error registers and sends it via
0403  *                 EDAC error API calls
0404  * @mci: struct mem_ctl_info pointer
0405  */
0406 static void i7300_process_fbd_error(struct mem_ctl_info *mci)
0407 {
0408     struct i7300_pvt *pvt;
0409     u32 errnum, value, error_reg;
0410     u16 val16;
0411     unsigned branch, channel, bank, rank, cas, ras;
0412     u32 syndrome;
0413 
0414     unsigned long errors;
0415     const char *specific;
0416     bool is_wr;
0417 
0418     pvt = mci->pvt_info;
0419 
0420     /* read in the 1st FATAL error register */
0421     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0422                   FERR_FAT_FBD, &error_reg);
0423     if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) {
0424         errors = error_reg & FERR_FAT_FBD_ERR_MASK ;
0425         errnum = find_first_bit(&errors,
0426                     ARRAY_SIZE(ferr_fat_fbd_name));
0427         specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
0428         branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0;
0429 
0430         pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
0431                      NRECMEMA, &val16);
0432         bank = NRECMEMA_BANK(val16);
0433         rank = NRECMEMA_RANK(val16);
0434 
0435         pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0436                 NRECMEMB, &value);
0437         is_wr = NRECMEMB_IS_WR(value);
0438         cas = NRECMEMB_CAS(value);
0439         ras = NRECMEMB_RAS(value);
0440 
0441         /* Clean the error register */
0442         pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0443                 FERR_FAT_FBD, error_reg);
0444 
0445         snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
0446              "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))",
0447              bank, ras, cas, errors, specific);
0448 
0449         edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
0450                      branch, -1, rank,
0451                      is_wr ? "Write error" : "Read error",
0452                      pvt->tmp_prt_buffer);
0453 
0454     }
0455 
0456     /* read in the 1st NON-FATAL error register */
0457     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0458                   FERR_NF_FBD, &error_reg);
0459     if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) {
0460         errors = error_reg & FERR_NF_FBD_ERR_MASK;
0461         errnum = find_first_bit(&errors,
0462                     ARRAY_SIZE(ferr_nf_fbd_name));
0463         specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
0464         branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0;
0465 
0466         pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0467             REDMEMA, &syndrome);
0468 
0469         pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
0470                      RECMEMA, &val16);
0471         bank = RECMEMA_BANK(val16);
0472         rank = RECMEMA_RANK(val16);
0473 
0474         pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0475                 RECMEMB, &value);
0476         is_wr = RECMEMB_IS_WR(value);
0477         cas = RECMEMB_CAS(value);
0478         ras = RECMEMB_RAS(value);
0479 
0480         pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0481                      REDMEMB, &value);
0482         channel = (branch << 1);
0483 
0484         /* Second channel ? */
0485         channel += !!(value & BIT(17));
0486 
0487         /* Clear the error bit */
0488         pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0489                 FERR_NF_FBD, error_reg);
0490 
0491         /* Form out message */
0492         snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
0493              "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))",
0494              bank, ras, cas, errors, specific);
0495 
0496         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0,
0497                      syndrome,
0498                      branch >> 1, channel % 2, rank,
0499                      is_wr ? "Write error" : "Read error",
0500                      pvt->tmp_prt_buffer);
0501     }
0502     return;
0503 }
0504 
0505 /**
0506  * i7300_check_error() - Calls the error checking subroutines
0507  * @mci: struct mem_ctl_info pointer
0508  */
0509 static void i7300_check_error(struct mem_ctl_info *mci)
0510 {
0511     i7300_process_error_global(mci);
0512     i7300_process_fbd_error(mci);
0513 };
0514 
0515 /**
0516  * i7300_clear_error() - Clears the error registers
0517  * @mci: struct mem_ctl_info pointer
0518  */
0519 static void i7300_clear_error(struct mem_ctl_info *mci)
0520 {
0521     struct i7300_pvt *pvt = mci->pvt_info;
0522     u32 value;
0523     /*
0524      * All error values are RWC - we need to read and write 1 to the
0525      * bit that we want to cleanup
0526      */
0527 
0528     /* Clear global error registers */
0529     pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0530                   FERR_GLOBAL_HI, &value);
0531     pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0532                   FERR_GLOBAL_HI, value);
0533 
0534     pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0535                   FERR_GLOBAL_LO, &value);
0536     pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
0537                   FERR_GLOBAL_LO, value);
0538 
0539     /* Clear FBD error registers */
0540     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0541                   FERR_FAT_FBD, &value);
0542     pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0543                   FERR_FAT_FBD, value);
0544 
0545     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0546                   FERR_NF_FBD, &value);
0547     pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0548                   FERR_NF_FBD, value);
0549 }
0550 
0551 /**
0552  * i7300_enable_error_reporting() - Enable the memory reporting logic at the
0553  *                  hardware
0554  * @mci: struct mem_ctl_info pointer
0555  */
0556 static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
0557 {
0558     struct i7300_pvt *pvt = mci->pvt_info;
0559     u32 fbd_error_mask;
0560 
0561     /* Read the FBD Error Mask Register */
0562     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0563                   EMASK_FBD, &fbd_error_mask);
0564 
0565     /* Enable with a '0' */
0566     fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);
0567 
0568     pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
0569                    EMASK_FBD, fbd_error_mask);
0570 }
0571 
0572 /************************************************
0573  * i7300 Functions related to memory enumberation
0574  ************************************************/
0575 
0576 /**
0577  * decode_mtr() - Decodes the MTR descriptor, filling the edac structs
0578  * @pvt: pointer to the private data struct used by i7300 driver
0579  * @slot: DIMM slot (0 to 7)
0580  * @ch: Channel number within the branch (0 or 1)
0581  * @branch: Branch number (0 or 1)
0582  * @dinfo: Pointer to DIMM info where dimm size is stored
0583  * @dimm: Pointer to the struct dimm_info that corresponds to that element
0584  */
0585 static int decode_mtr(struct i7300_pvt *pvt,
0586               int slot, int ch, int branch,
0587               struct i7300_dimm_info *dinfo,
0588               struct dimm_info *dimm)
0589 {
0590     int mtr, ans, addrBits, channel;
0591 
0592     channel = to_channel(ch, branch);
0593 
0594     mtr = pvt->mtr[slot][branch];
0595     ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
0596 
0597     edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n",
0598          slot, channel, ans ? "" : "NOT ");
0599 
0600     /* Determine if there is a DIMM present in this DIMM slot */
0601     if (!ans)
0602         return 0;
0603 
0604     /* Start with the number of bits for a Bank
0605     * on the DRAM */
0606     addrBits = MTR_DRAM_BANKS_ADDR_BITS;
0607     /* Add thenumber of ROW bits */
0608     addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
0609     /* add the number of COLUMN bits */
0610     addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
0611     /* add the number of RANK bits */
0612     addrBits += MTR_DIMM_RANKS(mtr);
0613 
0614     addrBits += 6;  /* add 64 bits per DIMM */
0615     addrBits -= 20; /* divide by 2^^20 */
0616     addrBits -= 3;  /* 8 bits per bytes */
0617 
0618     dinfo->megabytes = 1 << addrBits;
0619 
0620     edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
0621 
0622     edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
0623          MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
0624 
0625     edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
0626     edac_dbg(2, "\t\tNUMRANK: %s\n",
0627          MTR_DIMM_RANKS(mtr) ? "double" : "single");
0628     edac_dbg(2, "\t\tNUMROW: %s\n",
0629          MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
0630          MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
0631          MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
0632          "65,536 - 16 rows");
0633     edac_dbg(2, "\t\tNUMCOL: %s\n",
0634          MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
0635          MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
0636          MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
0637          "reserved");
0638     edac_dbg(2, "\t\tSIZE: %d MB\n", dinfo->megabytes);
0639 
0640     /*
0641      * The type of error detection actually depends of the
0642      * mode of operation. When it is just one single memory chip, at
0643      * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
0644      * In normal or mirrored mode, it uses Lockstep mode,
0645      * with the possibility of using an extended algorithm for x8 memories
0646      * See datasheet Sections 7.3.6 to 7.3.8
0647      */
0648 
0649     dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes);
0650     dimm->grain = 8;
0651     dimm->mtype = MEM_FB_DDR2;
0652     if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
0653         dimm->edac_mode = EDAC_SECDED;
0654         edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
0655     } else {
0656         edac_dbg(2, "\t\tECC code is on Lockstep mode\n");
0657         if (MTR_DRAM_WIDTH(mtr) == 8)
0658             dimm->edac_mode = EDAC_S8ECD8ED;
0659         else
0660             dimm->edac_mode = EDAC_S4ECD4ED;
0661     }
0662 
0663     /* ask what device type on this row */
0664     if (MTR_DRAM_WIDTH(mtr) == 8) {
0665         edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode\n",
0666              IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
0667              "enhanced" : "normal");
0668 
0669         dimm->dtype = DEV_X8;
0670     } else
0671         dimm->dtype = DEV_X4;
0672 
0673     return mtr;
0674 }
0675 
0676 /**
0677  * print_dimm_size() - Prints dump of the memory organization
0678  * @pvt: pointer to the private data struct used by i7300 driver
0679  *
0680  * Useful for debug. If debug is disabled, this routine do nothing
0681  */
0682 static void print_dimm_size(struct i7300_pvt *pvt)
0683 {
0684 #ifdef CONFIG_EDAC_DEBUG
0685     struct i7300_dimm_info *dinfo;
0686     char *p;
0687     int space, n;
0688     int channel, slot;
0689 
0690     space = PAGE_SIZE;
0691     p = pvt->tmp_prt_buffer;
0692 
0693     n = snprintf(p, space, "              ");
0694     p += n;
0695     space -= n;
0696     for (channel = 0; channel < MAX_CHANNELS; channel++) {
0697         n = snprintf(p, space, "channel %d | ", channel);
0698         p += n;
0699         space -= n;
0700     }
0701     edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
0702     p = pvt->tmp_prt_buffer;
0703     space = PAGE_SIZE;
0704     n = snprintf(p, space, "-------------------------------"
0705                    "------------------------------");
0706     p += n;
0707     space -= n;
0708     edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
0709     p = pvt->tmp_prt_buffer;
0710     space = PAGE_SIZE;
0711 
0712     for (slot = 0; slot < MAX_SLOTS; slot++) {
0713         n = snprintf(p, space, "csrow/SLOT %d  ", slot);
0714         p += n;
0715         space -= n;
0716 
0717         for (channel = 0; channel < MAX_CHANNELS; channel++) {
0718             dinfo = &pvt->dimm_info[slot][channel];
0719             n = snprintf(p, space, "%4d MB   | ", dinfo->megabytes);
0720             p += n;
0721             space -= n;
0722         }
0723 
0724         edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
0725         p = pvt->tmp_prt_buffer;
0726         space = PAGE_SIZE;
0727     }
0728 
0729     n = snprintf(p, space, "-------------------------------"
0730                    "------------------------------");
0731     p += n;
0732     space -= n;
0733     edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
0734     p = pvt->tmp_prt_buffer;
0735     space = PAGE_SIZE;
0736 #endif
0737 }
0738 
0739 /**
0740  * i7300_init_csrows() - Initialize the 'csrows' table within
0741  *           the mci control structure with the
0742  *           addressing of memory.
0743  * @mci: struct mem_ctl_info pointer
0744  */
0745 static int i7300_init_csrows(struct mem_ctl_info *mci)
0746 {
0747     struct i7300_pvt *pvt;
0748     struct i7300_dimm_info *dinfo;
0749     int rc = -ENODEV;
0750     int mtr;
0751     int ch, branch, slot, channel, max_channel, max_branch;
0752     struct dimm_info *dimm;
0753 
0754     pvt = mci->pvt_info;
0755 
0756     edac_dbg(2, "Memory Technology Registers:\n");
0757 
0758     if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
0759         max_branch = 1;
0760         max_channel = 1;
0761     } else {
0762         max_branch = MAX_BRANCHES;
0763         max_channel = MAX_CH_PER_BRANCH;
0764     }
0765 
0766     /* Get the AMB present registers for the four channels */
0767     for (branch = 0; branch < max_branch; branch++) {
0768         /* Read and dump branch 0's MTRs */
0769         channel = to_channel(0, branch);
0770         pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
0771                      AMBPRESENT_0,
0772                 &pvt->ambpresent[channel]);
0773         edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
0774              channel, pvt->ambpresent[channel]);
0775 
0776         if (max_channel == 1)
0777             continue;
0778 
0779         channel = to_channel(1, branch);
0780         pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
0781                      AMBPRESENT_1,
0782                 &pvt->ambpresent[channel]);
0783         edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
0784              channel, pvt->ambpresent[channel]);
0785     }
0786 
0787     /* Get the set of MTR[0-7] regs by each branch */
0788     for (slot = 0; slot < MAX_SLOTS; slot++) {
0789         int where = mtr_regs[slot];
0790         for (branch = 0; branch < max_branch; branch++) {
0791             pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
0792                     where,
0793                     &pvt->mtr[slot][branch]);
0794             for (ch = 0; ch < max_channel; ch++) {
0795                 int channel = to_channel(ch, branch);
0796 
0797                 dimm = edac_get_dimm(mci, branch, ch, slot);
0798 
0799                 dinfo = &pvt->dimm_info[slot][channel];
0800 
0801                 mtr = decode_mtr(pvt, slot, ch, branch,
0802                          dinfo, dimm);
0803 
0804                 /* if no DIMMS on this row, continue */
0805                 if (!MTR_DIMMS_PRESENT(mtr))
0806                     continue;
0807 
0808                 rc = 0;
0809 
0810             }
0811         }
0812     }
0813 
0814     return rc;
0815 }
0816 
0817 /**
0818  * decode_mir() - Decodes Memory Interleave Register (MIR) info
0819  * @mir_no: number of the MIR register to decode
0820  * @mir: array with the MIR data cached on the driver
0821  */
0822 static void decode_mir(int mir_no, u16 mir[MAX_MIR])
0823 {
0824     if (mir[mir_no] & 3)
0825         edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
0826              mir_no,
0827              (mir[mir_no] >> 4) & 0xfff,
0828              (mir[mir_no] & 1) ? "B0" : "",
0829              (mir[mir_no] & 2) ? "B1" : "");
0830 }
0831 
0832 /**
0833  * i7300_get_mc_regs() - Get the contents of the MC enumeration registers
0834  * @mci: struct mem_ctl_info pointer
0835  *
0836  * Data read is cached internally for its usage when needed
0837  */
0838 static int i7300_get_mc_regs(struct mem_ctl_info *mci)
0839 {
0840     struct i7300_pvt *pvt;
0841     u32 actual_tolm;
0842     int i, rc;
0843 
0844     pvt = mci->pvt_info;
0845 
0846     pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
0847             (u32 *) &pvt->ambase);
0848 
0849     edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
0850 
0851     /* Get the Branch Map regs */
0852     pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
0853     pvt->tolm >>= 12;
0854     edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
0855          pvt->tolm, pvt->tolm);
0856 
0857     actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
0858     edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
0859          actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
0860 
0861     /* Get memory controller settings */
0862     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
0863                  &pvt->mc_settings);
0864     pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
0865                  &pvt->mc_settings_a);
0866 
0867     if (IS_SINGLE_MODE(pvt->mc_settings_a))
0868         edac_dbg(0, "Memory controller operating on single mode\n");
0869     else
0870         edac_dbg(0, "Memory controller operating on %smirrored mode\n",
0871              IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
0872 
0873     edac_dbg(0, "Error detection is %s\n",
0874          IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
0875     edac_dbg(0, "Retry is %s\n",
0876          IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
0877 
0878     /* Get Memory Interleave Range registers */
0879     pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
0880                  &pvt->mir[0]);
0881     pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
0882                  &pvt->mir[1]);
0883     pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
0884                  &pvt->mir[2]);
0885 
0886     /* Decode the MIR regs */
0887     for (i = 0; i < MAX_MIR; i++)
0888         decode_mir(i, pvt->mir);
0889 
0890     rc = i7300_init_csrows(mci);
0891     if (rc < 0)
0892         return rc;
0893 
0894     /* Go and determine the size of each DIMM and place in an
0895      * orderly matrix */
0896     print_dimm_size(pvt);
0897 
0898     return 0;
0899 }
0900 
0901 /*************************************************
0902  * i7300 Functions related to device probe/release
0903  *************************************************/
0904 
0905 /**
0906  * i7300_put_devices() - Release the PCI devices
0907  * @mci: struct mem_ctl_info pointer
0908  */
0909 static void i7300_put_devices(struct mem_ctl_info *mci)
0910 {
0911     struct i7300_pvt *pvt;
0912     int branch;
0913 
0914     pvt = mci->pvt_info;
0915 
0916     /* Decrement usage count for devices */
0917     for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
0918         pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
0919     pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
0920     pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
0921 }
0922 
0923 /**
0924  * i7300_get_devices() - Find and perform 'get' operation on the MCH's
0925  *           device/functions we want to reference for this driver
0926  * @mci: struct mem_ctl_info pointer
0927  *
0928  * Access and prepare the several devices for usage:
0929  * I7300 devices used by this driver:
0930  *    Device 16, functions 0,1 and 2:   PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
0931  *    Device 21 function 0:     PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
0932  *    Device 22 function 0:     PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
0933  */
0934 static int i7300_get_devices(struct mem_ctl_info *mci)
0935 {
0936     struct i7300_pvt *pvt;
0937     struct pci_dev *pdev;
0938 
0939     pvt = mci->pvt_info;
0940 
0941     /* Attempt to 'get' the MCH register we want */
0942     pdev = NULL;
0943     while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0944                       PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
0945                       pdev))) {
0946         /* Store device 16 funcs 1 and 2 */
0947         switch (PCI_FUNC(pdev->devfn)) {
0948         case 1:
0949             if (!pvt->pci_dev_16_1_fsb_addr_map)
0950                 pvt->pci_dev_16_1_fsb_addr_map =
0951                             pci_dev_get(pdev);
0952             break;
0953         case 2:
0954             if (!pvt->pci_dev_16_2_fsb_err_regs)
0955                 pvt->pci_dev_16_2_fsb_err_regs =
0956                             pci_dev_get(pdev);
0957             break;
0958         }
0959     }
0960 
0961     if (!pvt->pci_dev_16_1_fsb_addr_map ||
0962         !pvt->pci_dev_16_2_fsb_err_regs) {
0963         /* At least one device was not found */
0964         i7300_printk(KERN_ERR,
0965             "'system address,Process Bus' device not found:"
0966             "vendor 0x%x device 0x%x ERR funcs (broken BIOS?)\n",
0967             PCI_VENDOR_ID_INTEL,
0968             PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
0969         goto error;
0970     }
0971 
0972     edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
0973          pci_name(pvt->pci_dev_16_0_fsb_ctlr),
0974          pvt->pci_dev_16_0_fsb_ctlr->vendor,
0975          pvt->pci_dev_16_0_fsb_ctlr->device);
0976     edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
0977          pci_name(pvt->pci_dev_16_1_fsb_addr_map),
0978          pvt->pci_dev_16_1_fsb_addr_map->vendor,
0979          pvt->pci_dev_16_1_fsb_addr_map->device);
0980     edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
0981          pci_name(pvt->pci_dev_16_2_fsb_err_regs),
0982          pvt->pci_dev_16_2_fsb_err_regs->vendor,
0983          pvt->pci_dev_16_2_fsb_err_regs->device);
0984 
0985     pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
0986                         PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
0987                         NULL);
0988     if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
0989         i7300_printk(KERN_ERR,
0990             "MC: 'BRANCH 0' device not found:"
0991             "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
0992             PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
0993         goto error;
0994     }
0995 
0996     pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
0997                         PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
0998                         NULL);
0999     if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
1000         i7300_printk(KERN_ERR,
1001             "MC: 'BRANCH 1' device not found:"
1002             "vendor 0x%x device 0x%x Func 0 "
1003             "(broken BIOS?)\n",
1004             PCI_VENDOR_ID_INTEL,
1005             PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1006         goto error;
1007     }
1008 
1009     return 0;
1010 
1011 error:
1012     i7300_put_devices(mci);
1013     return -ENODEV;
1014 }
1015 
1016 /**
1017  * i7300_init_one() - Probe for one instance of the device
1018  * @pdev: struct pci_dev pointer
1019  * @id: struct pci_device_id pointer - currently unused
1020  */
1021 static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1022 {
1023     struct mem_ctl_info *mci;
1024     struct edac_mc_layer layers[3];
1025     struct i7300_pvt *pvt;
1026     int rc;
1027 
1028     /* wake up device */
1029     rc = pci_enable_device(pdev);
1030     if (rc == -EIO)
1031         return rc;
1032 
1033     edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1034          pdev->bus->number,
1035          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1036 
1037     /* We only are looking for func 0 of the set */
1038     if (PCI_FUNC(pdev->devfn) != 0)
1039         return -ENODEV;
1040 
1041     /* allocate a new MC control structure */
1042     layers[0].type = EDAC_MC_LAYER_BRANCH;
1043     layers[0].size = MAX_BRANCHES;
1044     layers[0].is_virt_csrow = false;
1045     layers[1].type = EDAC_MC_LAYER_CHANNEL;
1046     layers[1].size = MAX_CH_PER_BRANCH;
1047     layers[1].is_virt_csrow = true;
1048     layers[2].type = EDAC_MC_LAYER_SLOT;
1049     layers[2].size = MAX_SLOTS;
1050     layers[2].is_virt_csrow = true;
1051     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1052     if (mci == NULL)
1053         return -ENOMEM;
1054 
1055     edac_dbg(0, "MC: mci = %p\n", mci);
1056 
1057     mci->pdev = &pdev->dev; /* record ptr  to the generic device */
1058 
1059     pvt = mci->pvt_info;
1060     pvt->pci_dev_16_0_fsb_ctlr = pdev;  /* Record this device in our private */
1061 
1062     pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
1063     if (!pvt->tmp_prt_buffer) {
1064         edac_mc_free(mci);
1065         return -ENOMEM;
1066     }
1067 
1068     /* 'get' the pci devices we want to reserve for our use */
1069     if (i7300_get_devices(mci))
1070         goto fail0;
1071 
1072     mci->mc_idx = 0;
1073     mci->mtype_cap = MEM_FLAG_FB_DDR2;
1074     mci->edac_ctl_cap = EDAC_FLAG_NONE;
1075     mci->edac_cap = EDAC_FLAG_NONE;
1076     mci->mod_name = "i7300_edac.c";
1077     mci->ctl_name = i7300_devs[0].ctl_name;
1078     mci->dev_name = pci_name(pdev);
1079     mci->ctl_page_to_phys = NULL;
1080 
1081     /* Set the function pointer to an actual operation function */
1082     mci->edac_check = i7300_check_error;
1083 
1084     /* initialize the MC control structure 'csrows' table
1085      * with the mapping and control information */
1086     if (i7300_get_mc_regs(mci)) {
1087         edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value\n");
1088         mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1089     } else {
1090         edac_dbg(1, "MC: Enable error reporting now\n");
1091         i7300_enable_error_reporting(mci);
1092     }
1093 
1094     /* add this new MC control structure to EDAC's list of MCs */
1095     if (edac_mc_add_mc(mci)) {
1096         edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1097         /* FIXME: perhaps some code should go here that disables error
1098          * reporting if we just enabled it
1099          */
1100         goto fail1;
1101     }
1102 
1103     i7300_clear_error(mci);
1104 
1105     /* allocating generic PCI control info */
1106     i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1107     if (!i7300_pci) {
1108         printk(KERN_WARNING
1109             "%s(): Unable to create PCI control\n",
1110             __func__);
1111         printk(KERN_WARNING
1112             "%s(): PCI error report via EDAC not setup\n",
1113             __func__);
1114     }
1115 
1116     return 0;
1117 
1118     /* Error exit unwinding stack */
1119 fail1:
1120 
1121     i7300_put_devices(mci);
1122 
1123 fail0:
1124     kfree(pvt->tmp_prt_buffer);
1125     edac_mc_free(mci);
1126     return -ENODEV;
1127 }
1128 
1129 /**
1130  * i7300_remove_one() - Remove the driver
1131  * @pdev: struct pci_dev pointer
1132  */
1133 static void i7300_remove_one(struct pci_dev *pdev)
1134 {
1135     struct mem_ctl_info *mci;
1136     char *tmp;
1137 
1138     edac_dbg(0, "\n");
1139 
1140     if (i7300_pci)
1141         edac_pci_release_generic_ctl(i7300_pci);
1142 
1143     mci = edac_mc_del_mc(&pdev->dev);
1144     if (!mci)
1145         return;
1146 
1147     tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;
1148 
1149     /* retrieve references to resources, and free those resources */
1150     i7300_put_devices(mci);
1151 
1152     kfree(tmp);
1153     edac_mc_free(mci);
1154 }
1155 
1156 /*
1157  * pci_device_id: table for which devices we are looking for
1158  *
1159  * Has only 8086:360c PCI ID
1160  */
1161 static const struct pci_device_id i7300_pci_tbl[] = {
1162     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1163     {0,}            /* 0 terminated list. */
1164 };
1165 
1166 MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1167 
1168 /*
1169  * i7300_driver: pci_driver structure for this module
1170  */
1171 static struct pci_driver i7300_driver = {
1172     .name = "i7300_edac",
1173     .probe = i7300_init_one,
1174     .remove = i7300_remove_one,
1175     .id_table = i7300_pci_tbl,
1176 };
1177 
1178 /**
1179  * i7300_init() - Registers the driver
1180  */
1181 static int __init i7300_init(void)
1182 {
1183     int pci_rc;
1184 
1185     edac_dbg(2, "\n");
1186 
1187     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1188     opstate_init();
1189 
1190     pci_rc = pci_register_driver(&i7300_driver);
1191 
1192     return (pci_rc < 0) ? pci_rc : 0;
1193 }
1194 
1195 /**
1196  * i7300_init() - Unregisters the driver
1197  */
1198 static void __exit i7300_exit(void)
1199 {
1200     edac_dbg(2, "\n");
1201     pci_unregister_driver(&i7300_driver);
1202 }
1203 
1204 module_init(i7300_init);
1205 module_exit(i7300_exit);
1206 
1207 MODULE_LICENSE("GPL");
1208 MODULE_AUTHOR("Mauro Carvalho Chehab");
1209 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
1210 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1211            I7300_REVISION);
1212 
1213 module_param(edac_op_state, int, 0444);
1214 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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