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0001 /*
0002  * Intel 5000(P/V/X) class Memory Controllers kernel module
0003  *
0004  * This file may be distributed under the terms of the
0005  * GNU General Public License.
0006  *
0007  * Written by Douglas Thompson Linux Networx (http://lnxi.com)
0008  *  norsk5@xmission.com
0009  *
0010  * This module is based on the following document:
0011  *
0012  * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
0013  *  http://developer.intel.com/design/chipsets/datashts/313070.htm
0014  *
0015  */
0016 
0017 #include <linux/module.h>
0018 #include <linux/init.h>
0019 #include <linux/pci.h>
0020 #include <linux/pci_ids.h>
0021 #include <linux/slab.h>
0022 #include <linux/edac.h>
0023 #include <asm/mmzone.h>
0024 
0025 #include "edac_module.h"
0026 
0027 /*
0028  * Alter this version for the I5000 module when modifications are made
0029  */
0030 #define I5000_REVISION    " Ver: 2.0.12"
0031 #define EDAC_MOD_STR      "i5000_edac"
0032 
0033 #define i5000_printk(level, fmt, arg...) \
0034         edac_printk(level, "i5000", fmt, ##arg)
0035 
0036 #define i5000_mc_printk(mci, level, fmt, arg...) \
0037         edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
0038 
0039 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
0040 #define PCI_DEVICE_ID_INTEL_FBD_0   0x25F5
0041 #endif
0042 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
0043 #define PCI_DEVICE_ID_INTEL_FBD_1   0x25F6
0044 #endif
0045 
0046 /* Device 16,
0047  * Function 0: System Address
0048  * Function 1: Memory Branch Map, Control, Errors Register
0049  * Function 2: FSB Error Registers
0050  *
0051  * All 3 functions of Device 16 (0,1,2) share the SAME DID
0052  */
0053 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
0054 
0055 /* OFFSETS for Function 0 */
0056 
0057 /* OFFSETS for Function 1 */
0058 #define     AMBASE          0x48
0059 #define     MAXCH           0x56
0060 #define     MAXDIMMPERCH        0x57
0061 #define     TOLM            0x6C
0062 #define     REDMEMB         0x7C
0063 #define         RED_ECC_LOCATOR(x)  ((x) & 0x3FFFF)
0064 #define         REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
0065 #define         REC_ECC_LOCATOR_ODD(x)  ((x) & 0x3FE00)
0066 #define     MIR0            0x80
0067 #define     MIR1            0x84
0068 #define     MIR2            0x88
0069 #define     AMIR0           0x8C
0070 #define     AMIR1           0x90
0071 #define     AMIR2           0x94
0072 
0073 #define     FERR_FAT_FBD        0x98
0074 #define     NERR_FAT_FBD        0x9C
0075 #define         EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
0076 #define         FERR_FAT_FBDCHAN 0x30000000
0077 #define         FERR_FAT_M3ERR  0x00000004
0078 #define         FERR_FAT_M2ERR  0x00000002
0079 #define         FERR_FAT_M1ERR  0x00000001
0080 #define         FERR_FAT_MASK   (FERR_FAT_M1ERR | \
0081                         FERR_FAT_M2ERR | \
0082                         FERR_FAT_M3ERR)
0083 
0084 #define     FERR_NF_FBD     0xA0
0085 
0086 /* Thermal and SPD or BFD errors */
0087 #define         FERR_NF_M28ERR  0x01000000
0088 #define         FERR_NF_M27ERR  0x00800000
0089 #define         FERR_NF_M26ERR  0x00400000
0090 #define         FERR_NF_M25ERR  0x00200000
0091 #define         FERR_NF_M24ERR  0x00100000
0092 #define         FERR_NF_M23ERR  0x00080000
0093 #define         FERR_NF_M22ERR  0x00040000
0094 #define         FERR_NF_M21ERR  0x00020000
0095 
0096 /* Correctable errors */
0097 #define         FERR_NF_M20ERR  0x00010000
0098 #define         FERR_NF_M19ERR  0x00008000
0099 #define         FERR_NF_M18ERR  0x00004000
0100 #define         FERR_NF_M17ERR  0x00002000
0101 
0102 /* Non-Retry or redundant Retry errors */
0103 #define         FERR_NF_M16ERR  0x00001000
0104 #define         FERR_NF_M15ERR  0x00000800
0105 #define         FERR_NF_M14ERR  0x00000400
0106 #define         FERR_NF_M13ERR  0x00000200
0107 
0108 /* Uncorrectable errors */
0109 #define         FERR_NF_M12ERR  0x00000100
0110 #define         FERR_NF_M11ERR  0x00000080
0111 #define         FERR_NF_M10ERR  0x00000040
0112 #define         FERR_NF_M9ERR   0x00000020
0113 #define         FERR_NF_M8ERR   0x00000010
0114 #define         FERR_NF_M7ERR   0x00000008
0115 #define         FERR_NF_M6ERR   0x00000004
0116 #define         FERR_NF_M5ERR   0x00000002
0117 #define         FERR_NF_M4ERR   0x00000001
0118 
0119 #define         FERR_NF_UNCORRECTABLE   (FERR_NF_M12ERR | \
0120                             FERR_NF_M11ERR | \
0121                             FERR_NF_M10ERR | \
0122                             FERR_NF_M9ERR | \
0123                             FERR_NF_M8ERR | \
0124                             FERR_NF_M7ERR | \
0125                             FERR_NF_M6ERR | \
0126                             FERR_NF_M5ERR | \
0127                             FERR_NF_M4ERR)
0128 #define         FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
0129                             FERR_NF_M19ERR | \
0130                             FERR_NF_M18ERR | \
0131                             FERR_NF_M17ERR)
0132 #define         FERR_NF_DIMM_SPARE  (FERR_NF_M27ERR | \
0133                             FERR_NF_M28ERR)
0134 #define         FERR_NF_THERMAL     (FERR_NF_M26ERR | \
0135                             FERR_NF_M25ERR | \
0136                             FERR_NF_M24ERR | \
0137                             FERR_NF_M23ERR)
0138 #define         FERR_NF_SPD_PROTOCOL    (FERR_NF_M22ERR)
0139 #define         FERR_NF_NORTH_CRC   (FERR_NF_M21ERR)
0140 #define         FERR_NF_NON_RETRY   (FERR_NF_M13ERR | \
0141                             FERR_NF_M14ERR | \
0142                             FERR_NF_M15ERR)
0143 
0144 #define     NERR_NF_FBD     0xA4
0145 #define         FERR_NF_MASK        (FERR_NF_UNCORRECTABLE | \
0146                             FERR_NF_CORRECTABLE | \
0147                             FERR_NF_DIMM_SPARE | \
0148                             FERR_NF_THERMAL | \
0149                             FERR_NF_SPD_PROTOCOL | \
0150                             FERR_NF_NORTH_CRC | \
0151                             FERR_NF_NON_RETRY)
0152 
0153 #define     EMASK_FBD       0xA8
0154 #define         EMASK_FBD_M28ERR    0x08000000
0155 #define         EMASK_FBD_M27ERR    0x04000000
0156 #define         EMASK_FBD_M26ERR    0x02000000
0157 #define         EMASK_FBD_M25ERR    0x01000000
0158 #define         EMASK_FBD_M24ERR    0x00800000
0159 #define         EMASK_FBD_M23ERR    0x00400000
0160 #define         EMASK_FBD_M22ERR    0x00200000
0161 #define         EMASK_FBD_M21ERR    0x00100000
0162 #define         EMASK_FBD_M20ERR    0x00080000
0163 #define         EMASK_FBD_M19ERR    0x00040000
0164 #define         EMASK_FBD_M18ERR    0x00020000
0165 #define         EMASK_FBD_M17ERR    0x00010000
0166 
0167 #define         EMASK_FBD_M15ERR    0x00004000
0168 #define         EMASK_FBD_M14ERR    0x00002000
0169 #define         EMASK_FBD_M13ERR    0x00001000
0170 #define         EMASK_FBD_M12ERR    0x00000800
0171 #define         EMASK_FBD_M11ERR    0x00000400
0172 #define         EMASK_FBD_M10ERR    0x00000200
0173 #define         EMASK_FBD_M9ERR     0x00000100
0174 #define         EMASK_FBD_M8ERR     0x00000080
0175 #define         EMASK_FBD_M7ERR     0x00000040
0176 #define         EMASK_FBD_M6ERR     0x00000020
0177 #define         EMASK_FBD_M5ERR     0x00000010
0178 #define         EMASK_FBD_M4ERR     0x00000008
0179 #define         EMASK_FBD_M3ERR     0x00000004
0180 #define         EMASK_FBD_M2ERR     0x00000002
0181 #define         EMASK_FBD_M1ERR     0x00000001
0182 
0183 #define         ENABLE_EMASK_FBD_FATAL_ERRORS   (EMASK_FBD_M1ERR | \
0184                             EMASK_FBD_M2ERR | \
0185                             EMASK_FBD_M3ERR)
0186 
0187 #define         ENABLE_EMASK_FBD_UNCORRECTABLE  (EMASK_FBD_M4ERR | \
0188                             EMASK_FBD_M5ERR | \
0189                             EMASK_FBD_M6ERR | \
0190                             EMASK_FBD_M7ERR | \
0191                             EMASK_FBD_M8ERR | \
0192                             EMASK_FBD_M9ERR | \
0193                             EMASK_FBD_M10ERR | \
0194                             EMASK_FBD_M11ERR | \
0195                             EMASK_FBD_M12ERR)
0196 #define         ENABLE_EMASK_FBD_CORRECTABLE    (EMASK_FBD_M17ERR | \
0197                             EMASK_FBD_M18ERR | \
0198                             EMASK_FBD_M19ERR | \
0199                             EMASK_FBD_M20ERR)
0200 #define         ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
0201                             EMASK_FBD_M28ERR)
0202 #define         ENABLE_EMASK_FBD_THERMALS   (EMASK_FBD_M26ERR | \
0203                             EMASK_FBD_M25ERR | \
0204                             EMASK_FBD_M24ERR | \
0205                             EMASK_FBD_M23ERR)
0206 #define         ENABLE_EMASK_FBD_SPD_PROTOCOL   (EMASK_FBD_M22ERR)
0207 #define         ENABLE_EMASK_FBD_NORTH_CRC  (EMASK_FBD_M21ERR)
0208 #define         ENABLE_EMASK_FBD_NON_RETRY  (EMASK_FBD_M15ERR | \
0209                             EMASK_FBD_M14ERR | \
0210                             EMASK_FBD_M13ERR)
0211 
0212 #define     ENABLE_EMASK_ALL    (ENABLE_EMASK_FBD_NON_RETRY | \
0213                     ENABLE_EMASK_FBD_NORTH_CRC | \
0214                     ENABLE_EMASK_FBD_SPD_PROTOCOL | \
0215                     ENABLE_EMASK_FBD_THERMALS | \
0216                     ENABLE_EMASK_FBD_DIMM_SPARE | \
0217                     ENABLE_EMASK_FBD_FATAL_ERRORS | \
0218                     ENABLE_EMASK_FBD_CORRECTABLE | \
0219                     ENABLE_EMASK_FBD_UNCORRECTABLE)
0220 
0221 #define     ERR0_FBD        0xAC
0222 #define     ERR1_FBD        0xB0
0223 #define     ERR2_FBD        0xB4
0224 #define     MCERR_FBD       0xB8
0225 #define     NRECMEMA        0xBE
0226 #define         NREC_BANK(x)        (((x)>>12) & 0x7)
0227 #define         NREC_RDWR(x)        (((x)>>11) & 1)
0228 #define         NREC_RANK(x)        (((x)>>8) & 0x7)
0229 #define     NRECMEMB        0xC0
0230 #define         NREC_CAS(x)     (((x)>>16) & 0xFFF)
0231 #define         NREC_RAS(x)     ((x) & 0x7FFF)
0232 #define     NRECFGLOG       0xC4
0233 #define     NREEECFBDA      0xC8
0234 #define     NREEECFBDB      0xCC
0235 #define     NREEECFBDC      0xD0
0236 #define     NREEECFBDD      0xD4
0237 #define     NREEECFBDE      0xD8
0238 #define     REDMEMA         0xDC
0239 #define     RECMEMA         0xE2
0240 #define         REC_BANK(x)     (((x)>>12) & 0x7)
0241 #define         REC_RDWR(x)     (((x)>>11) & 1)
0242 #define         REC_RANK(x)     (((x)>>8) & 0x7)
0243 #define     RECMEMB         0xE4
0244 #define         REC_CAS(x)      (((x)>>16) & 0xFFFFFF)
0245 #define         REC_RAS(x)      ((x) & 0x7FFF)
0246 #define     RECFGLOG        0xE8
0247 #define     RECFBDA         0xEC
0248 #define     RECFBDB         0xF0
0249 #define     RECFBDC         0xF4
0250 #define     RECFBDD         0xF8
0251 #define     RECFBDE         0xFC
0252 
0253 /* OFFSETS for Function 2 */
0254 
0255 /*
0256  * Device 21,
0257  * Function 0: Memory Map Branch 0
0258  *
0259  * Device 22,
0260  * Function 0: Memory Map Branch 1
0261  */
0262 #define PCI_DEVICE_ID_I5000_BRANCH_0    0x25F5
0263 #define PCI_DEVICE_ID_I5000_BRANCH_1    0x25F6
0264 
0265 #define AMB_PRESENT_0   0x64
0266 #define AMB_PRESENT_1   0x66
0267 #define MTR0        0x80
0268 #define MTR1        0x84
0269 #define MTR2        0x88
0270 #define MTR3        0x8C
0271 
0272 #define NUM_MTRS        4
0273 #define CHANNELS_PER_BRANCH 2
0274 #define MAX_BRANCHES        2
0275 
0276 /* Defines to extract the various fields from the
0277  *  MTRx - Memory Technology Registers
0278  */
0279 #define MTR_DIMMS_PRESENT(mtr)      ((mtr) & (0x1 << 8))
0280 #define MTR_DRAM_WIDTH(mtr)     ((((mtr) >> 6) & 0x1) ? 8 : 4)
0281 #define MTR_DRAM_BANKS(mtr)     ((((mtr) >> 5) & 0x1) ? 8 : 4)
0282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr)   ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
0283 #define MTR_DIMM_RANK(mtr)      (((mtr) >> 4) & 0x1)
0284 #define MTR_DIMM_RANK_ADDR_BITS(mtr)    (MTR_DIMM_RANK(mtr) ? 2 : 1)
0285 #define MTR_DIMM_ROWS(mtr)      (((mtr) >> 2) & 0x3)
0286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr)    (MTR_DIMM_ROWS(mtr) + 13)
0287 #define MTR_DIMM_COLS(mtr)      ((mtr) & 0x3)
0288 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
0289 
0290 /* enables the report of miscellaneous messages as CE errors - default off */
0291 static int misc_messages;
0292 
0293 /* Enumeration of supported devices */
0294 enum i5000_chips {
0295     I5000P = 0,
0296     I5000V = 1,     /* future */
0297     I5000X = 2      /* future */
0298 };
0299 
0300 /* Device name and register DID (Device ID) */
0301 struct i5000_dev_info {
0302     const char *ctl_name;   /* name for this device */
0303     u16 fsb_mapping_errors; /* DID for the branchmap,control */
0304 };
0305 
0306 /* Table of devices attributes supported by this driver */
0307 static const struct i5000_dev_info i5000_devs[] = {
0308     [I5000P] = {
0309         .ctl_name = "I5000",
0310         .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
0311     },
0312 };
0313 
0314 struct i5000_dimm_info {
0315     int megabytes;      /* size, 0 means not present  */
0316     int dual_rank;
0317 };
0318 
0319 #define MAX_CHANNELS    6   /* max possible channels */
0320 #define MAX_CSROWS  (8*2)   /* max possible csrows per channel */
0321 
0322 /* driver private data structure */
0323 struct i5000_pvt {
0324     struct pci_dev *system_address; /* 16.0 */
0325     struct pci_dev *branchmap_werrors;  /* 16.1 */
0326     struct pci_dev *fsb_error_regs; /* 16.2 */
0327     struct pci_dev *branch_0;   /* 21.0 */
0328     struct pci_dev *branch_1;   /* 22.0 */
0329 
0330     u16 tolm;       /* top of low memory */
0331     union {
0332         u64 ambase;     /* AMB BAR */
0333         struct {
0334             u32 ambase_bottom;
0335             u32 ambase_top;
0336         } u __packed;
0337     };
0338 
0339     u16 mir0, mir1, mir2;
0340 
0341     u16 b0_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
0342     u16 b0_ambpresent0; /* Branch 0, Channel 0 */
0343     u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
0344 
0345     u16 b1_mtr[NUM_MTRS];   /* Memory Technlogy Reg */
0346     u16 b1_ambpresent0; /* Branch 1, Channel 8 */
0347     u16 b1_ambpresent1; /* Branch 1, Channel 1 */
0348 
0349     /* DIMM information matrix, allocating architecture maximums */
0350     struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
0351 
0352     /* Actual values for this controller */
0353     int maxch;      /* Max channels */
0354     int maxdimmperch;   /* Max DIMMs per channel */
0355 };
0356 
0357 /* I5000 MCH error information retrieved from Hardware */
0358 struct i5000_error_info {
0359 
0360     /* These registers are always read from the MC */
0361     u32 ferr_fat_fbd;   /* First Errors Fatal */
0362     u32 nerr_fat_fbd;   /* Next Errors Fatal */
0363     u32 ferr_nf_fbd;    /* First Errors Non-Fatal */
0364     u32 nerr_nf_fbd;    /* Next Errors Non-Fatal */
0365 
0366     /* These registers are input ONLY if there was a Recoverable  Error */
0367     u32 redmemb;        /* Recoverable Mem Data Error log B */
0368     u16 recmema;        /* Recoverable Mem Error log A */
0369     u32 recmemb;        /* Recoverable Mem Error log B */
0370 
0371     /* These registers are input ONLY if there was a
0372      * Non-Recoverable Error */
0373     u16 nrecmema;       /* Non-Recoverable Mem log A */
0374     u32 nrecmemb;       /* Non-Recoverable Mem log B */
0375 
0376 };
0377 
0378 static struct edac_pci_ctl_info *i5000_pci;
0379 
0380 /*
0381  *  i5000_get_error_info    Retrieve the hardware error information from
0382  *              the hardware and cache it in the 'info'
0383  *              structure
0384  */
0385 static void i5000_get_error_info(struct mem_ctl_info *mci,
0386                  struct i5000_error_info *info)
0387 {
0388     struct i5000_pvt *pvt;
0389     u32 value;
0390 
0391     pvt = mci->pvt_info;
0392 
0393     /* read in the 1st FATAL error register */
0394     pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
0395 
0396     /* Mask only the bits that the doc says are valid
0397      */
0398     value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
0399 
0400     /* If there is an error, then read in the */
0401     /* NEXT FATAL error register and the Memory Error Log Register A */
0402     if (value & FERR_FAT_MASK) {
0403         info->ferr_fat_fbd = value;
0404 
0405         /* harvest the various error data we need */
0406         pci_read_config_dword(pvt->branchmap_werrors,
0407                 NERR_FAT_FBD, &info->nerr_fat_fbd);
0408         pci_read_config_word(pvt->branchmap_werrors,
0409                 NRECMEMA, &info->nrecmema);
0410         pci_read_config_dword(pvt->branchmap_werrors,
0411                 NRECMEMB, &info->nrecmemb);
0412 
0413         /* Clear the error bits, by writing them back */
0414         pci_write_config_dword(pvt->branchmap_werrors,
0415                 FERR_FAT_FBD, value);
0416     } else {
0417         info->ferr_fat_fbd = 0;
0418         info->nerr_fat_fbd = 0;
0419         info->nrecmema = 0;
0420         info->nrecmemb = 0;
0421     }
0422 
0423     /* read in the 1st NON-FATAL error register */
0424     pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
0425 
0426     /* If there is an error, then read in the 1st NON-FATAL error
0427      * register as well */
0428     if (value & FERR_NF_MASK) {
0429         info->ferr_nf_fbd = value;
0430 
0431         /* harvest the various error data we need */
0432         pci_read_config_dword(pvt->branchmap_werrors,
0433                 NERR_NF_FBD, &info->nerr_nf_fbd);
0434         pci_read_config_word(pvt->branchmap_werrors,
0435                 RECMEMA, &info->recmema);
0436         pci_read_config_dword(pvt->branchmap_werrors,
0437                 RECMEMB, &info->recmemb);
0438         pci_read_config_dword(pvt->branchmap_werrors,
0439                 REDMEMB, &info->redmemb);
0440 
0441         /* Clear the error bits, by writing them back */
0442         pci_write_config_dword(pvt->branchmap_werrors,
0443                 FERR_NF_FBD, value);
0444     } else {
0445         info->ferr_nf_fbd = 0;
0446         info->nerr_nf_fbd = 0;
0447         info->recmema = 0;
0448         info->recmemb = 0;
0449         info->redmemb = 0;
0450     }
0451 }
0452 
0453 /*
0454  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
0455  *                  struct i5000_error_info *info,
0456  *                  int handle_errors);
0457  *
0458  *  handle the Intel FATAL errors, if any
0459  */
0460 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
0461                     struct i5000_error_info *info,
0462                     int handle_errors)
0463 {
0464     char msg[EDAC_MC_LABEL_LEN + 1 + 160];
0465     char *specific = NULL;
0466     u32 allErrors;
0467     int channel;
0468     int bank;
0469     int rank;
0470     int rdwr;
0471     int ras, cas;
0472 
0473     /* mask off the Error bits that are possible */
0474     allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
0475     if (!allErrors)
0476         return;     /* if no error, return now */
0477 
0478     channel = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
0479 
0480     /* Use the NON-Recoverable macros to extract data */
0481     bank = NREC_BANK(info->nrecmema);
0482     rank = NREC_RANK(info->nrecmema);
0483     rdwr = NREC_RDWR(info->nrecmema);
0484     ras = NREC_RAS(info->nrecmemb);
0485     cas = NREC_CAS(info->nrecmemb);
0486 
0487     edac_dbg(0, "\t\tCSROW= %d  Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
0488          rank, channel, bank,
0489          rdwr ? "Write" : "Read", ras, cas);
0490 
0491     /* Only 1 bit will be on */
0492     switch (allErrors) {
0493     case FERR_FAT_M1ERR:
0494         specific = "Alert on non-redundant retry or fast "
0495                 "reset timeout";
0496         break;
0497     case FERR_FAT_M2ERR:
0498         specific = "Northbound CRC error on non-redundant "
0499                 "retry";
0500         break;
0501     case FERR_FAT_M3ERR:
0502         {
0503         static int done;
0504 
0505         /*
0506          * This error is generated to inform that the intelligent
0507          * throttling is disabled and the temperature passed the
0508          * specified middle point. Since this is something the BIOS
0509          * should take care of, we'll warn only once to avoid
0510          * worthlessly flooding the log.
0511          */
0512         if (done)
0513             return;
0514         done++;
0515 
0516         specific = ">Tmid Thermal event with intelligent "
0517                "throttling disabled";
0518         }
0519         break;
0520     }
0521 
0522     /* Form out message */
0523     snprintf(msg, sizeof(msg),
0524          "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
0525          bank, ras, cas, allErrors, specific);
0526 
0527     /* Call the helper to output message */
0528     edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
0529                  channel >> 1, channel & 1, rank,
0530                  rdwr ? "Write error" : "Read error",
0531                  msg);
0532 }
0533 
0534 /*
0535  * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
0536  *              struct i5000_error_info *info,
0537  *              int handle_errors);
0538  *
0539  *  handle the Intel NON-FATAL errors, if any
0540  */
0541 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
0542                     struct i5000_error_info *info,
0543                     int handle_errors)
0544 {
0545     char msg[EDAC_MC_LABEL_LEN + 1 + 170];
0546     char *specific = NULL;
0547     u32 allErrors;
0548     u32 ue_errors;
0549     u32 ce_errors;
0550     u32 misc_errors;
0551     int branch;
0552     int channel;
0553     int bank;
0554     int rank;
0555     int rdwr;
0556     int ras, cas;
0557 
0558     /* mask off the Error bits that are possible */
0559     allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
0560     if (!allErrors)
0561         return;     /* if no error, return now */
0562 
0563     /* ONLY ONE of the possible error bits will be set, as per the docs */
0564     ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
0565     if (ue_errors) {
0566         edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
0567 
0568         branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
0569 
0570         /*
0571          * According with i5000 datasheet, bit 28 has no significance
0572          * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
0573          */
0574         channel = branch & 2;
0575 
0576         bank = NREC_BANK(info->nrecmema);
0577         rank = NREC_RANK(info->nrecmema);
0578         rdwr = NREC_RDWR(info->nrecmema);
0579         ras = NREC_RAS(info->nrecmemb);
0580         cas = NREC_CAS(info->nrecmemb);
0581 
0582         edac_dbg(0, "\t\tCSROW= %d  Channels= %d,%d  (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
0583              rank, channel, channel + 1, branch >> 1, bank,
0584              rdwr ? "Write" : "Read", ras, cas);
0585 
0586         switch (ue_errors) {
0587         case FERR_NF_M12ERR:
0588             specific = "Non-Aliased Uncorrectable Patrol Data ECC";
0589             break;
0590         case FERR_NF_M11ERR:
0591             specific = "Non-Aliased Uncorrectable Spare-Copy "
0592                     "Data ECC";
0593             break;
0594         case FERR_NF_M10ERR:
0595             specific = "Non-Aliased Uncorrectable Mirrored Demand "
0596                     "Data ECC";
0597             break;
0598         case FERR_NF_M9ERR:
0599             specific = "Non-Aliased Uncorrectable Non-Mirrored "
0600                     "Demand Data ECC";
0601             break;
0602         case FERR_NF_M8ERR:
0603             specific = "Aliased Uncorrectable Patrol Data ECC";
0604             break;
0605         case FERR_NF_M7ERR:
0606             specific = "Aliased Uncorrectable Spare-Copy Data ECC";
0607             break;
0608         case FERR_NF_M6ERR:
0609             specific = "Aliased Uncorrectable Mirrored Demand "
0610                     "Data ECC";
0611             break;
0612         case FERR_NF_M5ERR:
0613             specific = "Aliased Uncorrectable Non-Mirrored Demand "
0614                     "Data ECC";
0615             break;
0616         case FERR_NF_M4ERR:
0617             specific = "Uncorrectable Data ECC on Replay";
0618             break;
0619         }
0620 
0621         /* Form out message */
0622         snprintf(msg, sizeof(msg),
0623              "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
0624              rank, bank, ras, cas, ue_errors, specific);
0625 
0626         /* Call the helper to output message */
0627         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0628                 channel >> 1, -1, rank,
0629                 rdwr ? "Write error" : "Read error",
0630                 msg);
0631     }
0632 
0633     /* Check correctable errors */
0634     ce_errors = allErrors & FERR_NF_CORRECTABLE;
0635     if (ce_errors) {
0636         edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
0637 
0638         branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
0639 
0640         channel = 0;
0641         if (REC_ECC_LOCATOR_ODD(info->redmemb))
0642             channel = 1;
0643 
0644         /* Convert channel to be based from zero, instead of
0645          * from branch base of 0 */
0646         channel += branch;
0647 
0648         bank = REC_BANK(info->recmema);
0649         rank = REC_RANK(info->recmema);
0650         rdwr = REC_RDWR(info->recmema);
0651         ras = REC_RAS(info->recmemb);
0652         cas = REC_CAS(info->recmemb);
0653 
0654         edac_dbg(0, "\t\tCSROW= %d Channel= %d  (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
0655              rank, channel, branch >> 1, bank,
0656              rdwr ? "Write" : "Read", ras, cas);
0657 
0658         switch (ce_errors) {
0659         case FERR_NF_M17ERR:
0660             specific = "Correctable Non-Mirrored Demand Data ECC";
0661             break;
0662         case FERR_NF_M18ERR:
0663             specific = "Correctable Mirrored Demand Data ECC";
0664             break;
0665         case FERR_NF_M19ERR:
0666             specific = "Correctable Spare-Copy Data ECC";
0667             break;
0668         case FERR_NF_M20ERR:
0669             specific = "Correctable Patrol Data ECC";
0670             break;
0671         }
0672 
0673         /* Form out message */
0674         snprintf(msg, sizeof(msg),
0675              "Rank=%d Bank=%d RDWR=%s RAS=%d "
0676              "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
0677              rdwr ? "Write" : "Read", ras, cas, ce_errors,
0678              specific);
0679 
0680         /* Call the helper to output message */
0681         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
0682                 channel >> 1, channel % 2, rank,
0683                 rdwr ? "Write error" : "Read error",
0684                 msg);
0685     }
0686 
0687     if (!misc_messages)
0688         return;
0689 
0690     misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
0691                    FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
0692     if (misc_errors) {
0693         switch (misc_errors) {
0694         case FERR_NF_M13ERR:
0695             specific = "Non-Retry or Redundant Retry FBD Memory "
0696                     "Alert or Redundant Fast Reset Timeout";
0697             break;
0698         case FERR_NF_M14ERR:
0699             specific = "Non-Retry or Redundant Retry FBD "
0700                     "Configuration Alert";
0701             break;
0702         case FERR_NF_M15ERR:
0703             specific = "Non-Retry or Redundant Retry FBD "
0704                     "Northbound CRC error on read data";
0705             break;
0706         case FERR_NF_M21ERR:
0707             specific = "FBD Northbound CRC error on "
0708                     "FBD Sync Status";
0709             break;
0710         case FERR_NF_M22ERR:
0711             specific = "SPD protocol error";
0712             break;
0713         case FERR_NF_M27ERR:
0714             specific = "DIMM-spare copy started";
0715             break;
0716         case FERR_NF_M28ERR:
0717             specific = "DIMM-spare copy completed";
0718             break;
0719         }
0720         branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
0721 
0722         /* Form out message */
0723         snprintf(msg, sizeof(msg),
0724              "Err=%#x (%s)", misc_errors, specific);
0725 
0726         /* Call the helper to output message */
0727         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
0728                 branch >> 1, -1, -1,
0729                 "Misc error", msg);
0730     }
0731 }
0732 
0733 /*
0734  *  i5000_process_error_info    Process the error info that is
0735  *  in the 'info' structure, previously retrieved from hardware
0736  */
0737 static void i5000_process_error_info(struct mem_ctl_info *mci,
0738                 struct i5000_error_info *info,
0739                 int handle_errors)
0740 {
0741     /* First handle any fatal errors that occurred */
0742     i5000_process_fatal_error_info(mci, info, handle_errors);
0743 
0744     /* now handle any non-fatal errors that occurred */
0745     i5000_process_nonfatal_error_info(mci, info, handle_errors);
0746 }
0747 
0748 /*
0749  *  i5000_clear_error   Retrieve any error from the hardware
0750  *              but do NOT process that error.
0751  *              Used for 'clearing' out of previous errors
0752  *              Called by the Core module.
0753  */
0754 static void i5000_clear_error(struct mem_ctl_info *mci)
0755 {
0756     struct i5000_error_info info;
0757 
0758     i5000_get_error_info(mci, &info);
0759 }
0760 
0761 /*
0762  *  i5000_check_error   Retrieve and process errors reported by the
0763  *              hardware. Called by the Core module.
0764  */
0765 static void i5000_check_error(struct mem_ctl_info *mci)
0766 {
0767     struct i5000_error_info info;
0768 
0769     i5000_get_error_info(mci, &info);
0770     i5000_process_error_info(mci, &info, 1);
0771 }
0772 
0773 /*
0774  *  i5000_get_devices   Find and perform 'get' operation on the MCH's
0775  *          device/functions we want to reference for this driver
0776  *
0777  *          Need to 'get' device 16 func 1 and func 2
0778  */
0779 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
0780 {
0781     //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
0782     struct i5000_pvt *pvt;
0783     struct pci_dev *pdev;
0784 
0785     pvt = mci->pvt_info;
0786 
0787     /* Attempt to 'get' the MCH register we want */
0788     pdev = NULL;
0789     while (1) {
0790         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0791                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
0792 
0793         /* End of list, leave */
0794         if (pdev == NULL) {
0795             i5000_printk(KERN_ERR,
0796                 "'system address,Process Bus' "
0797                 "device not found:"
0798                 "vendor 0x%x device 0x%x FUNC 1 "
0799                 "(broken BIOS?)\n",
0800                 PCI_VENDOR_ID_INTEL,
0801                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
0802 
0803             return 1;
0804         }
0805 
0806         /* Scan for device 16 func 1 */
0807         if (PCI_FUNC(pdev->devfn) == 1)
0808             break;
0809     }
0810 
0811     pvt->branchmap_werrors = pdev;
0812 
0813     /* Attempt to 'get' the MCH register we want */
0814     pdev = NULL;
0815     while (1) {
0816         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0817                 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
0818 
0819         if (pdev == NULL) {
0820             i5000_printk(KERN_ERR,
0821                 "MC: 'branchmap,control,errors' "
0822                 "device not found:"
0823                 "vendor 0x%x device 0x%x Func 2 "
0824                 "(broken BIOS?)\n",
0825                 PCI_VENDOR_ID_INTEL,
0826                 PCI_DEVICE_ID_INTEL_I5000_DEV16);
0827 
0828             pci_dev_put(pvt->branchmap_werrors);
0829             return 1;
0830         }
0831 
0832         /* Scan for device 16 func 1 */
0833         if (PCI_FUNC(pdev->devfn) == 2)
0834             break;
0835     }
0836 
0837     pvt->fsb_error_regs = pdev;
0838 
0839     edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
0840          pci_name(pvt->system_address),
0841          pvt->system_address->vendor, pvt->system_address->device);
0842     edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
0843          pci_name(pvt->branchmap_werrors),
0844          pvt->branchmap_werrors->vendor,
0845          pvt->branchmap_werrors->device);
0846     edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
0847          pci_name(pvt->fsb_error_regs),
0848          pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
0849 
0850     pdev = NULL;
0851     pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0852             PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
0853 
0854     if (pdev == NULL) {
0855         i5000_printk(KERN_ERR,
0856             "MC: 'BRANCH 0' device not found:"
0857             "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
0858             PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
0859 
0860         pci_dev_put(pvt->branchmap_werrors);
0861         pci_dev_put(pvt->fsb_error_regs);
0862         return 1;
0863     }
0864 
0865     pvt->branch_0 = pdev;
0866 
0867     /* If this device claims to have more than 2 channels then
0868      * fetch Branch 1's information
0869      */
0870     if (pvt->maxch >= CHANNELS_PER_BRANCH) {
0871         pdev = NULL;
0872         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0873                 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
0874 
0875         if (pdev == NULL) {
0876             i5000_printk(KERN_ERR,
0877                 "MC: 'BRANCH 1' device not found:"
0878                 "vendor 0x%x device 0x%x Func 0 "
0879                 "(broken BIOS?)\n",
0880                 PCI_VENDOR_ID_INTEL,
0881                 PCI_DEVICE_ID_I5000_BRANCH_1);
0882 
0883             pci_dev_put(pvt->branchmap_werrors);
0884             pci_dev_put(pvt->fsb_error_regs);
0885             pci_dev_put(pvt->branch_0);
0886             return 1;
0887         }
0888 
0889         pvt->branch_1 = pdev;
0890     }
0891 
0892     return 0;
0893 }
0894 
0895 /*
0896  *  i5000_put_devices   'put' all the devices that we have
0897  *              reserved via 'get'
0898  */
0899 static void i5000_put_devices(struct mem_ctl_info *mci)
0900 {
0901     struct i5000_pvt *pvt;
0902 
0903     pvt = mci->pvt_info;
0904 
0905     pci_dev_put(pvt->branchmap_werrors);    /* FUNC 1 */
0906     pci_dev_put(pvt->fsb_error_regs);   /* FUNC 2 */
0907     pci_dev_put(pvt->branch_0); /* DEV 21 */
0908 
0909     /* Only if more than 2 channels do we release the second branch */
0910     if (pvt->maxch >= CHANNELS_PER_BRANCH)
0911         pci_dev_put(pvt->branch_1); /* DEV 22 */
0912 }
0913 
0914 /*
0915  *  determine_amb_resent
0916  *
0917  *      the information is contained in NUM_MTRS different registers
0918  *      determineing which of the NUM_MTRS requires knowing
0919  *      which channel is in question
0920  *
0921  *  2 branches, each with 2 channels
0922  *      b0_ambpresent0 for channel '0'
0923  *      b0_ambpresent1 for channel '1'
0924  *      b1_ambpresent0 for channel '2'
0925  *      b1_ambpresent1 for channel '3'
0926  */
0927 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
0928 {
0929     int amb_present;
0930 
0931     if (channel < CHANNELS_PER_BRANCH) {
0932         if (channel & 0x1)
0933             amb_present = pvt->b0_ambpresent1;
0934         else
0935             amb_present = pvt->b0_ambpresent0;
0936     } else {
0937         if (channel & 0x1)
0938             amb_present = pvt->b1_ambpresent1;
0939         else
0940             amb_present = pvt->b1_ambpresent0;
0941     }
0942 
0943     return amb_present;
0944 }
0945 
0946 /*
0947  * determine_mtr(pvt, csrow, channel)
0948  *
0949  *  return the proper MTR register as determine by the csrow and channel desired
0950  */
0951 static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
0952 {
0953     int mtr;
0954 
0955     if (channel < CHANNELS_PER_BRANCH)
0956         mtr = pvt->b0_mtr[slot];
0957     else
0958         mtr = pvt->b1_mtr[slot];
0959 
0960     return mtr;
0961 }
0962 
0963 /*
0964  */
0965 static void decode_mtr(int slot_row, u16 mtr)
0966 {
0967     int ans;
0968 
0969     ans = MTR_DIMMS_PRESENT(mtr);
0970 
0971     edac_dbg(2, "\tMTR%d=0x%x:  DIMMs are %sPresent\n",
0972          slot_row, mtr, ans ? "" : "NOT ");
0973     if (!ans)
0974         return;
0975 
0976     edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
0977     edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
0978     edac_dbg(2, "\t\tNUMRANK: %s\n",
0979          MTR_DIMM_RANK(mtr) ? "double" : "single");
0980     edac_dbg(2, "\t\tNUMROW: %s\n",
0981          MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
0982          MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
0983          MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
0984          "reserved");
0985     edac_dbg(2, "\t\tNUMCOL: %s\n",
0986          MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
0987          MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
0988          MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
0989          "reserved");
0990 }
0991 
0992 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
0993             struct i5000_dimm_info *dinfo)
0994 {
0995     int mtr;
0996     int amb_present_reg;
0997     int addrBits;
0998 
0999     mtr = determine_mtr(pvt, slot, channel);
1000     if (MTR_DIMMS_PRESENT(mtr)) {
1001         amb_present_reg = determine_amb_present_reg(pvt, channel);
1002 
1003         /* Determine if there is a DIMM present in this DIMM slot */
1004         if (amb_present_reg) {
1005             dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1006 
1007             /* Start with the number of bits for a Bank
1008                 * on the DRAM */
1009             addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1010             /* Add the number of ROW bits */
1011             addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1012             /* add the number of COLUMN bits */
1013             addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1014 
1015             /* Dual-rank memories have twice the size */
1016             if (dinfo->dual_rank)
1017                 addrBits++;
1018 
1019             addrBits += 6;  /* add 64 bits per DIMM */
1020             addrBits -= 20; /* divide by 2^^20 */
1021             addrBits -= 3;  /* 8 bits per bytes */
1022 
1023             dinfo->megabytes = 1 << addrBits;
1024         }
1025     }
1026 }
1027 
1028 /*
1029  *  calculate_dimm_size
1030  *
1031  *  also will output a DIMM matrix map, if debug is enabled, for viewing
1032  *  how the DIMMs are populated
1033  */
1034 static void calculate_dimm_size(struct i5000_pvt *pvt)
1035 {
1036     struct i5000_dimm_info *dinfo;
1037     int slot, channel, branch;
1038     char *p, *mem_buffer;
1039     int space, n;
1040 
1041     /* ================= Generate some debug output ================= */
1042     space = PAGE_SIZE;
1043     mem_buffer = p = kmalloc(space, GFP_KERNEL);
1044     if (p == NULL) {
1045         i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1046             __FILE__, __func__);
1047         return;
1048     }
1049 
1050     /* Scan all the actual slots
1051      * and calculate the information for each DIMM
1052      * Start with the highest slot first, to display it first
1053      * and work toward the 0th slot
1054      */
1055     for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
1056 
1057         /* on an odd slot, first output a 'boundary' marker,
1058          * then reset the message buffer  */
1059         if (slot & 0x1) {
1060             n = snprintf(p, space, "--------------------------"
1061                 "--------------------------------");
1062             p += n;
1063             space -= n;
1064             edac_dbg(2, "%s\n", mem_buffer);
1065             p = mem_buffer;
1066             space = PAGE_SIZE;
1067         }
1068         n = snprintf(p, space, "slot %2d    ", slot);
1069         p += n;
1070         space -= n;
1071 
1072         for (channel = 0; channel < pvt->maxch; channel++) {
1073             dinfo = &pvt->dimm_info[slot][channel];
1074             handle_channel(pvt, slot, channel, dinfo);
1075             if (dinfo->megabytes)
1076                 n = snprintf(p, space, "%4d MB %dR| ",
1077                          dinfo->megabytes, dinfo->dual_rank + 1);
1078             else
1079                 n = snprintf(p, space, "%4d MB   | ", 0);
1080             p += n;
1081             space -= n;
1082         }
1083         p += n;
1084         space -= n;
1085         edac_dbg(2, "%s\n", mem_buffer);
1086         p = mem_buffer;
1087         space = PAGE_SIZE;
1088     }
1089 
1090     /* Output the last bottom 'boundary' marker */
1091     n = snprintf(p, space, "--------------------------"
1092         "--------------------------------");
1093     p += n;
1094     space -= n;
1095     edac_dbg(2, "%s\n", mem_buffer);
1096     p = mem_buffer;
1097     space = PAGE_SIZE;
1098 
1099     /* now output the 'channel' labels */
1100     n = snprintf(p, space, "           ");
1101     p += n;
1102     space -= n;
1103     for (channel = 0; channel < pvt->maxch; channel++) {
1104         n = snprintf(p, space, "channel %d | ", channel);
1105         p += n;
1106         space -= n;
1107     }
1108     edac_dbg(2, "%s\n", mem_buffer);
1109     p = mem_buffer;
1110     space = PAGE_SIZE;
1111 
1112     n = snprintf(p, space, "           ");
1113     p += n;
1114     for (branch = 0; branch < MAX_BRANCHES; branch++) {
1115         n = snprintf(p, space, "       branch %d       | ", branch);
1116         p += n;
1117         space -= n;
1118     }
1119 
1120     /* output the last message and free buffer */
1121     edac_dbg(2, "%s\n", mem_buffer);
1122     kfree(mem_buffer);
1123 }
1124 
1125 /*
1126  *  i5000_get_mc_regs   read in the necessary registers and
1127  *              cache locally
1128  *
1129  *          Fills in the private data members
1130  */
1131 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1132 {
1133     struct i5000_pvt *pvt;
1134     u32 actual_tolm;
1135     u16 limit;
1136     int slot_row;
1137     int way0, way1;
1138 
1139     pvt = mci->pvt_info;
1140 
1141     pci_read_config_dword(pvt->system_address, AMBASE,
1142             &pvt->u.ambase_bottom);
1143     pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1144             &pvt->u.ambase_top);
1145 
1146     edac_dbg(2, "AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
1147          (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1148 
1149     /* Get the Branch Map regs */
1150     pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1151     pvt->tolm >>= 12;
1152     edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
1153          pvt->tolm, pvt->tolm);
1154 
1155     actual_tolm = pvt->tolm << 28;
1156     edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
1157          actual_tolm, actual_tolm);
1158 
1159     pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1160     pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1161     pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1162 
1163     /* Get the MIR[0-2] regs */
1164     limit = (pvt->mir0 >> 4) & 0x0FFF;
1165     way0 = pvt->mir0 & 0x1;
1166     way1 = pvt->mir0 & 0x2;
1167     edac_dbg(2, "MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n",
1168          limit, way1, way0);
1169     limit = (pvt->mir1 >> 4) & 0x0FFF;
1170     way0 = pvt->mir1 & 0x1;
1171     way1 = pvt->mir1 & 0x2;
1172     edac_dbg(2, "MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n",
1173          limit, way1, way0);
1174     limit = (pvt->mir2 >> 4) & 0x0FFF;
1175     way0 = pvt->mir2 & 0x1;
1176     way1 = pvt->mir2 & 0x2;
1177     edac_dbg(2, "MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n",
1178          limit, way1, way0);
1179 
1180     /* Get the MTR[0-3] regs */
1181     for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1182         int where = MTR0 + (slot_row * sizeof(u32));
1183 
1184         pci_read_config_word(pvt->branch_0, where,
1185                 &pvt->b0_mtr[slot_row]);
1186 
1187         edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
1188              slot_row, where, pvt->b0_mtr[slot_row]);
1189 
1190         if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1191             pci_read_config_word(pvt->branch_1, where,
1192                     &pvt->b1_mtr[slot_row]);
1193             edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
1194                  slot_row, where, pvt->b1_mtr[slot_row]);
1195         } else {
1196             pvt->b1_mtr[slot_row] = 0;
1197         }
1198     }
1199 
1200     /* Read and dump branch 0's MTRs */
1201     edac_dbg(2, "Memory Technology Registers:\n");
1202     edac_dbg(2, "   Branch 0:\n");
1203     for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1204         decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1205     }
1206     pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1207             &pvt->b0_ambpresent0);
1208     edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1209     pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1210             &pvt->b0_ambpresent1);
1211     edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1212 
1213     /* Only if we have 2 branchs (4 channels) */
1214     if (pvt->maxch < CHANNELS_PER_BRANCH) {
1215         pvt->b1_ambpresent0 = 0;
1216         pvt->b1_ambpresent1 = 0;
1217     } else {
1218         /* Read and dump  branch 1's MTRs */
1219         edac_dbg(2, "   Branch 1:\n");
1220         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1221             decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1222         }
1223         pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1224                 &pvt->b1_ambpresent0);
1225         edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
1226              pvt->b1_ambpresent0);
1227         pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1228                 &pvt->b1_ambpresent1);
1229         edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
1230              pvt->b1_ambpresent1);
1231     }
1232 
1233     /* Go and determine the size of each DIMM and place in an
1234      * orderly matrix */
1235     calculate_dimm_size(pvt);
1236 }
1237 
1238 /*
1239  *  i5000_init_csrows   Initialize the 'csrows' table within
1240  *              the mci control structure with the
1241  *              addressing of memory.
1242  *
1243  *  return:
1244  *      0   success
1245  *      1   no actual memory found on this MC
1246  */
1247 static int i5000_init_csrows(struct mem_ctl_info *mci)
1248 {
1249     struct i5000_pvt *pvt;
1250     struct dimm_info *dimm;
1251     int empty;
1252     int max_csrows;
1253     int mtr;
1254     int csrow_megs;
1255     int channel;
1256     int slot;
1257 
1258     pvt = mci->pvt_info;
1259     max_csrows = pvt->maxdimmperch * 2;
1260 
1261     empty = 1;      /* Assume NO memory */
1262 
1263     /*
1264      * FIXME: The memory layout used to map slot/channel into the
1265      * real memory architecture is weird: branch+slot are "csrows"
1266      * and channel is channel. That required an extra array (dimm_info)
1267      * to map the dimms. A good cleanup would be to remove this array,
1268      * and do a loop here with branch, channel, slot
1269      */
1270     for (slot = 0; slot < max_csrows; slot++) {
1271         for (channel = 0; channel < pvt->maxch; channel++) {
1272 
1273             mtr = determine_mtr(pvt, slot, channel);
1274 
1275             if (!MTR_DIMMS_PRESENT(mtr))
1276                 continue;
1277 
1278             dimm = edac_get_dimm(mci, channel / MAX_BRANCHES,
1279                          channel % MAX_BRANCHES, slot);
1280 
1281             csrow_megs = pvt->dimm_info[slot][channel].megabytes;
1282             dimm->grain = 8;
1283 
1284             /* Assume DDR2 for now */
1285             dimm->mtype = MEM_FB_DDR2;
1286 
1287             /* ask what device type on this row */
1288             if (MTR_DRAM_WIDTH(mtr) == 8)
1289                 dimm->dtype = DEV_X8;
1290             else
1291                 dimm->dtype = DEV_X4;
1292 
1293             dimm->edac_mode = EDAC_S8ECD8ED;
1294             dimm->nr_pages = csrow_megs << 8;
1295         }
1296 
1297         empty = 0;
1298     }
1299 
1300     return empty;
1301 }
1302 
1303 /*
1304  *  i5000_enable_error_reporting
1305  *          Turn on the memory reporting features of the hardware
1306  */
1307 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1308 {
1309     struct i5000_pvt *pvt;
1310     u32 fbd_error_mask;
1311 
1312     pvt = mci->pvt_info;
1313 
1314     /* Read the FBD Error Mask Register */
1315     pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1316             &fbd_error_mask);
1317 
1318     /* Enable with a '0' */
1319     fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1320 
1321     pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1322             fbd_error_mask);
1323 }
1324 
1325 /*
1326  * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
1327  *
1328  *  ask the device how many channels are present and how many CSROWS
1329  *   as well
1330  */
1331 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1332                     int *num_dimms_per_channel,
1333                     int *num_channels)
1334 {
1335     u8 value;
1336 
1337     /* Need to retrieve just how many channels and dimms per channel are
1338      * supported on this memory controller
1339      */
1340     pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1341     *num_dimms_per_channel = (int)value;
1342 
1343     pci_read_config_byte(pdev, MAXCH, &value);
1344     *num_channels = (int)value;
1345 }
1346 
1347 /*
1348  *  i5000_probe1    Probe for ONE instance of device to see if it is
1349  *          present.
1350  *  return:
1351  *      0 for FOUND a device
1352  *      < 0 for error code
1353  */
1354 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1355 {
1356     struct mem_ctl_info *mci;
1357     struct edac_mc_layer layers[3];
1358     struct i5000_pvt *pvt;
1359     int num_channels;
1360     int num_dimms_per_channel;
1361 
1362     edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1363          pdev->bus->number,
1364          PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1365 
1366     /* We only are looking for func 0 of the set */
1367     if (PCI_FUNC(pdev->devfn) != 0)
1368         return -ENODEV;
1369 
1370     /* Ask the devices for the number of CSROWS and CHANNELS so
1371      * that we can calculate the memory resources, etc
1372      *
1373      * The Chipset will report what it can handle which will be greater
1374      * or equal to what the motherboard manufacturer will implement.
1375      *
1376      * As we don't have a motherboard identification routine to determine
1377      * actual number of slots/dimms per channel, we thus utilize the
1378      * resource as specified by the chipset. Thus, we might have
1379      * have more DIMMs per channel than actually on the mobo, but this
1380      * allows the driver to support up to the chipset max, without
1381      * some fancy mobo determination.
1382      */
1383     i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1384                     &num_channels);
1385 
1386     edac_dbg(0, "MC: Number of Branches=2 Channels= %d  DIMMS= %d\n",
1387          num_channels, num_dimms_per_channel);
1388 
1389     /* allocate a new MC control structure */
1390 
1391     layers[0].type = EDAC_MC_LAYER_BRANCH;
1392     layers[0].size = MAX_BRANCHES;
1393     layers[0].is_virt_csrow = false;
1394     layers[1].type = EDAC_MC_LAYER_CHANNEL;
1395     layers[1].size = num_channels / MAX_BRANCHES;
1396     layers[1].is_virt_csrow = false;
1397     layers[2].type = EDAC_MC_LAYER_SLOT;
1398     layers[2].size = num_dimms_per_channel;
1399     layers[2].is_virt_csrow = true;
1400     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1401     if (mci == NULL)
1402         return -ENOMEM;
1403 
1404     edac_dbg(0, "MC: mci = %p\n", mci);
1405 
1406     mci->pdev = &pdev->dev; /* record ptr  to the generic device */
1407 
1408     pvt = mci->pvt_info;
1409     pvt->system_address = pdev; /* Record this device in our private */
1410     pvt->maxch = num_channels;
1411     pvt->maxdimmperch = num_dimms_per_channel;
1412 
1413     /* 'get' the pci devices we want to reserve for our use */
1414     if (i5000_get_devices(mci, dev_idx))
1415         goto fail0;
1416 
1417     /* Time to get serious */
1418     i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1419 
1420     mci->mc_idx = 0;
1421     mci->mtype_cap = MEM_FLAG_FB_DDR2;
1422     mci->edac_ctl_cap = EDAC_FLAG_NONE;
1423     mci->edac_cap = EDAC_FLAG_NONE;
1424     mci->mod_name = "i5000_edac.c";
1425     mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1426     mci->dev_name = pci_name(pdev);
1427     mci->ctl_page_to_phys = NULL;
1428 
1429     /* Set the function pointer to an actual operation function */
1430     mci->edac_check = i5000_check_error;
1431 
1432     /* initialize the MC control structure 'csrows' table
1433      * with the mapping and control information */
1434     if (i5000_init_csrows(mci)) {
1435         edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
1436         mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1437     } else {
1438         edac_dbg(1, "MC: Enable error reporting now\n");
1439         i5000_enable_error_reporting(mci);
1440     }
1441 
1442     /* add this new MC control structure to EDAC's list of MCs */
1443     if (edac_mc_add_mc(mci)) {
1444         edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1445         /* FIXME: perhaps some code should go here that disables error
1446          * reporting if we just enabled it
1447          */
1448         goto fail1;
1449     }
1450 
1451     i5000_clear_error(mci);
1452 
1453     /* allocating generic PCI control info */
1454     i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1455     if (!i5000_pci) {
1456         printk(KERN_WARNING
1457             "%s(): Unable to create PCI control\n",
1458             __func__);
1459         printk(KERN_WARNING
1460             "%s(): PCI error report via EDAC not setup\n",
1461             __func__);
1462     }
1463 
1464     return 0;
1465 
1466     /* Error exit unwinding stack */
1467 fail1:
1468 
1469     i5000_put_devices(mci);
1470 
1471 fail0:
1472     edac_mc_free(mci);
1473     return -ENODEV;
1474 }
1475 
1476 /*
1477  *  i5000_init_one  constructor for one instance of device
1478  *
1479  *  returns:
1480  *      negative on error
1481  *      count (>= 0)
1482  */
1483 static int i5000_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1484 {
1485     int rc;
1486 
1487     edac_dbg(0, "MC:\n");
1488 
1489     /* wake up device */
1490     rc = pci_enable_device(pdev);
1491     if (rc)
1492         return rc;
1493 
1494     /* now probe and enable the device */
1495     return i5000_probe1(pdev, id->driver_data);
1496 }
1497 
1498 /*
1499  *  i5000_remove_one    destructor for one instance of device
1500  *
1501  */
1502 static void i5000_remove_one(struct pci_dev *pdev)
1503 {
1504     struct mem_ctl_info *mci;
1505 
1506     edac_dbg(0, "\n");
1507 
1508     if (i5000_pci)
1509         edac_pci_release_generic_ctl(i5000_pci);
1510 
1511     if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1512         return;
1513 
1514     /* retrieve references to resources, and free those resources */
1515     i5000_put_devices(mci);
1516     edac_mc_free(mci);
1517 }
1518 
1519 /*
1520  *  pci_device_id   table for which devices we are looking for
1521  *
1522  *  The "E500P" device is the first device supported.
1523  */
1524 static const struct pci_device_id i5000_pci_tbl[] = {
1525     {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1526      .driver_data = I5000P},
1527 
1528     {0,}            /* 0 terminated list. */
1529 };
1530 
1531 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1532 
1533 /*
1534  *  i5000_driver    pci_driver structure for this module
1535  *
1536  */
1537 static struct pci_driver i5000_driver = {
1538     .name = KBUILD_BASENAME,
1539     .probe = i5000_init_one,
1540     .remove = i5000_remove_one,
1541     .id_table = i5000_pci_tbl,
1542 };
1543 
1544 /*
1545  *  i5000_init      Module entry function
1546  *          Try to initialize this module for its devices
1547  */
1548 static int __init i5000_init(void)
1549 {
1550     int pci_rc;
1551 
1552     edac_dbg(2, "MC:\n");
1553 
1554     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1555     opstate_init();
1556 
1557     pci_rc = pci_register_driver(&i5000_driver);
1558 
1559     return (pci_rc < 0) ? pci_rc : 0;
1560 }
1561 
1562 /*
1563  *  i5000_exit()    Module exit function
1564  *          Unregister the driver
1565  */
1566 static void __exit i5000_exit(void)
1567 {
1568     edac_dbg(2, "MC:\n");
1569     pci_unregister_driver(&i5000_driver);
1570 }
1571 
1572 module_init(i5000_init);
1573 module_exit(i5000_exit);
1574 
1575 MODULE_LICENSE("GPL");
1576 MODULE_AUTHOR
1577     ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1578 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1579         I5000_REVISION);
1580 
1581 module_param(edac_op_state, int, 0444);
1582 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1583 module_param(misc_messages, int, 0444);
1584 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1585
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