drivers/edac/i3200_edac.c

0001 /*
0002  * Intel 3200/3210 Memory Controller kernel module
0003  * Copyright (C) 2008-2009 Akamai Technologies, Inc.
0004  * Portions by Hitoshi Mitake <h.mitake@gmail.com>.
0005  *
0006  * This file may be distributed under the terms of the
0007  * GNU General Public License.
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/init.h>
0012 #include <linux/pci.h>
0013 #include <linux/pci_ids.h>
0014 #include <linux/edac.h>
0015 #include <linux/io.h>
0016 #include "edac_module.h"
0017
0018 #include <linux/io-64-nonatomic-lo-hi.h>
0019
0020 #define EDAC_MOD_STR        "i3200_edac"
0021
0022 #define PCI_DEVICE_ID_INTEL_3200_HB    0x29f0
0023
0024 #define I3200_DIMMS     4
0025 #define I3200_RANKS     8
0026 #define I3200_RANKS_PER_CHANNEL 4
0027 #define I3200_CHANNELS      2
0028
0029 /* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */
0030
0031 #define I3200_MCHBAR_LOW    0x48    /* MCH Memory Mapped Register BAR */
0032 #define I3200_MCHBAR_HIGH   0x4c
0033 #define I3200_MCHBAR_MASK   0xfffffc000ULL  /* bits 35:14 */
0034 #define I3200_MMR_WINDOW_SIZE   16384
0035
0036 #define I3200_TOM       0xa0    /* Top of Memory (16b)
0037          *
0038          * 15:10 reserved
0039          *  9:0  total populated physical memory
0040          */
0041 #define I3200_TOM_MASK      0x3ff   /* bits 9:0 */
0042 #define I3200_TOM_SHIFT     26  /* 64MiB grain */
0043
0044 #define I3200_ERRSTS        0xc8    /* Error Status Register (16b)
0045          *
0046          * 15    reserved
0047          * 14    Isochronous TBWRR Run Behind FIFO Full
0048          *       (ITCV)
0049          * 13    Isochronous TBWRR Run Behind FIFO Put
0050          *       (ITSTV)
0051          * 12    reserved
0052          * 11    MCH Thermal Sensor Event
0053          *       for SMI/SCI/SERR (GTSE)
0054          * 10    reserved
0055          *  9    LOCK to non-DRAM Memory Flag (LCKF)
0056          *  8    reserved
0057          *  7    DRAM Throttle Flag (DTF)
0058          *  6:2  reserved
0059          *  1    Multi-bit DRAM ECC Error Flag (DMERR)
0060          *  0    Single-bit DRAM ECC Error Flag (DSERR)
0061          */
0062 #define I3200_ERRSTS_UE     0x0002
0063 #define I3200_ERRSTS_CE     0x0001
0064 #define I3200_ERRSTS_BITS   (I3200_ERRSTS_UE | I3200_ERRSTS_CE)
0065
0066
0067 /* Intel  MMIO register space - device 0 function 0 - MMR space */
0068
0069 #define I3200_C0DRB 0x200   /* Channel 0 DRAM Rank Boundary (16b x 4)
0070          *
0071          * 15:10 reserved
0072          *  9:0  Channel 0 DRAM Rank Boundary Address
0073          */
0074 #define I3200_C1DRB 0x600   /* Channel 1 DRAM Rank Boundary (16b x 4) */
0075 #define I3200_DRB_MASK  0x3ff   /* bits 9:0 */
0076 #define I3200_DRB_SHIFT 26  /* 64MiB grain */
0077
0078 #define I3200_C0ECCERRLOG   0x280   /* Channel 0 ECC Error Log (64b)
0079          *
0080          * 63:48 Error Column Address (ERRCOL)
0081          * 47:32 Error Row Address (ERRROW)
0082          * 31:29 Error Bank Address (ERRBANK)
0083          * 28:27 Error Rank Address (ERRRANK)
0084          * 26:24 reserved
0085          * 23:16 Error Syndrome (ERRSYND)
0086          * 15: 2 reserved
0087          *    1  Multiple Bit Error Status (MERRSTS)
0088          *    0  Correctable Error Status (CERRSTS)
0089          */
0090 #define I3200_C1ECCERRLOG       0x680   /* Chan 1 ECC Error Log (64b) */
0091 #define I3200_ECCERRLOG_CE      0x1
0092 #define I3200_ECCERRLOG_UE      0x2
0093 #define I3200_ECCERRLOG_RANK_BITS   0x18000000
0094 #define I3200_ECCERRLOG_RANK_SHIFT  27
0095 #define I3200_ECCERRLOG_SYNDROME_BITS   0xff0000
0096 #define I3200_ECCERRLOG_SYNDROME_SHIFT  16
0097 #define I3200_CAPID0            0xe0    /* P.95 of spec for details */
0098
0099 struct i3200_priv {
0100     void __iomem *window;
0101 };
0102
0103 static int nr_channels;
0104
0105 static int how_many_channels(struct pci_dev *pdev)
0106 {
0107     int n_channels;
0108
0109     unsigned char capid0_8b; /* 8th byte of CAPID0 */
0110
0111     pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
0112
0113     if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
0114         edac_dbg(0, "In single channel mode\n");
0115         n_channels = 1;
0116     } else {
0117         edac_dbg(0, "In dual channel mode\n");
0118         n_channels = 2;
0119     }
0120
0121     if (capid0_8b & 0x10) /* check if both channels are filled */
0122         edac_dbg(0, "2 DIMMS per channel disabled\n");
0123     else
0124         edac_dbg(0, "2 DIMMS per channel enabled\n");
0125
0126     return n_channels;
0127 }
0128
0129 static unsigned long eccerrlog_syndrome(u64 log)
0130 {
0131     return (log & I3200_ECCERRLOG_SYNDROME_BITS) >>
0132         I3200_ECCERRLOG_SYNDROME_SHIFT;
0133 }
0134
0135 static int eccerrlog_row(int channel, u64 log)
0136 {
0137     u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>
0138         I3200_ECCERRLOG_RANK_SHIFT);
0139     return rank | (channel * I3200_RANKS_PER_CHANNEL);
0140 }
0141
0142 enum i3200_chips {
0143     I3200 = 0,
0144 };
0145
0146 struct i3200_dev_info {
0147     const char *ctl_name;
0148 };
0149
0150 struct i3200_error_info {
0151     u16 errsts;
0152     u16 errsts2;
0153     u64 eccerrlog[I3200_CHANNELS];
0154 };
0155
0156 static const struct i3200_dev_info i3200_devs[] = {
0157     [I3200] = {
0158         .ctl_name = "i3200"
0159     },
0160 };
0161
0162 static struct pci_dev *mci_pdev;
0163 static int i3200_registered = 1;
0164
0165
0166 static void i3200_clear_error_info(struct mem_ctl_info *mci)
0167 {
0168     struct pci_dev *pdev;
0169
0170     pdev = to_pci_dev(mci->pdev);
0171
0172     /*
0173      * Clear any error bits.
0174      * (Yes, we really clear bits by writing 1 to them.)
0175      */
0176     pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS,
0177         I3200_ERRSTS_BITS);
0178 }
0179
0180 static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci,
0181         struct i3200_error_info *info)
0182 {
0183     struct pci_dev *pdev;
0184     struct i3200_priv *priv = mci->pvt_info;
0185     void __iomem *window = priv->window;
0186
0187     pdev = to_pci_dev(mci->pdev);
0188
0189     /*
0190      * This is a mess because there is no atomic way to read all the
0191      * registers at once and the registers can transition from CE being
0192      * overwritten by UE.
0193      */
0194     pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts);
0195     if (!(info->errsts & I3200_ERRSTS_BITS))
0196         return;
0197
0198     info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
0199     if (nr_channels == 2)
0200         info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
0201
0202     pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2);
0203
0204     /*
0205      * If the error is the same for both reads then the first set
0206      * of reads is valid.  If there is a change then there is a CE
0207      * with no info and the second set of reads is valid and
0208      * should be UE info.
0209      */
0210     if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
0211         info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG);
0212         if (nr_channels == 2)
0213             info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG);
0214     }
0215
0216     i3200_clear_error_info(mci);
0217 }
0218
0219 static void i3200_process_error_info(struct mem_ctl_info *mci,
0220         struct i3200_error_info *info)
0221 {
0222     int channel;
0223     u64 log;
0224
0225     if (!(info->errsts & I3200_ERRSTS_BITS))
0226         return;
0227
0228     if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) {
0229         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0230                      -1, -1, -1, "UE overwrote CE", "");
0231         info->errsts = info->errsts2;
0232     }
0233
0234     for (channel = 0; channel < nr_channels; channel++) {
0235         log = info->eccerrlog[channel];
0236         if (log & I3200_ECCERRLOG_UE) {
0237             edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0238                          0, 0, 0,
0239                          eccerrlog_row(channel, log),
0240                          -1, -1,
0241                          "i3000 UE", "");
0242         } else if (log & I3200_ECCERRLOG_CE) {
0243             edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0244                          0, 0, eccerrlog_syndrome(log),
0245                          eccerrlog_row(channel, log),
0246                          -1, -1,
0247                          "i3000 CE", "");
0248         }
0249     }
0250 }
0251
0252 static void i3200_check(struct mem_ctl_info *mci)
0253 {
0254     struct i3200_error_info info;
0255
0256     i3200_get_and_clear_error_info(mci, &info);
0257     i3200_process_error_info(mci, &info);
0258 }
0259
0260 static void __iomem *i3200_map_mchbar(struct pci_dev *pdev)
0261 {
0262     union {
0263         u64 mchbar;
0264         struct {
0265             u32 mchbar_low;
0266             u32 mchbar_high;
0267         };
0268     } u;
0269     void __iomem *window;
0270
0271     pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low);
0272     pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high);
0273     u.mchbar &= I3200_MCHBAR_MASK;
0274
0275     if (u.mchbar != (resource_size_t)u.mchbar) {
0276         printk(KERN_ERR
0277             "i3200: mmio space beyond accessible range (0x%llx)\n",
0278             (unsigned long long)u.mchbar);
0279         return NULL;
0280     }
0281
0282     window = ioremap(u.mchbar, I3200_MMR_WINDOW_SIZE);
0283     if (!window)
0284         printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n",
0285             (unsigned long long)u.mchbar);
0286
0287     return window;
0288 }
0289
0290
0291 static void i3200_get_drbs(void __iomem *window,
0292     u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
0293 {
0294     int i;
0295
0296     for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
0297         drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
0298         drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
0299
0300         edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
0301     }
0302 }
0303
0304 static bool i3200_is_stacked(struct pci_dev *pdev,
0305     u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL])
0306 {
0307     u16 tom;
0308
0309     pci_read_config_word(pdev, I3200_TOM, &tom);
0310     tom &= I3200_TOM_MASK;
0311
0312     return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom;
0313 }
0314
0315 static unsigned long drb_to_nr_pages(
0316     u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked,
0317     int channel, int rank)
0318 {
0319     int n;
0320
0321     n = drbs[channel][rank];
0322     if (!n)
0323         return 0;
0324
0325     if (rank > 0)
0326         n -= drbs[channel][rank - 1];
0327     if (stacked && (channel == 1) &&
0328     drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])
0329         n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1];
0330
0331     n <<= (I3200_DRB_SHIFT - PAGE_SHIFT);
0332     return n;
0333 }
0334
0335 static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
0336 {
0337     int rc;
0338     int i, j;
0339     struct mem_ctl_info *mci = NULL;
0340     struct edac_mc_layer layers[2];
0341     u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL];
0342     bool stacked;
0343     void __iomem *window;
0344     struct i3200_priv *priv;
0345
0346     edac_dbg(0, "MC:\n");
0347
0348     window = i3200_map_mchbar(pdev);
0349     if (!window)
0350         return -ENODEV;
0351
0352     i3200_get_drbs(window, drbs);
0353     nr_channels = how_many_channels(pdev);
0354
0355     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0356     layers[0].size = I3200_DIMMS;
0357     layers[0].is_virt_csrow = true;
0358     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0359     layers[1].size = nr_channels;
0360     layers[1].is_virt_csrow = false;
0361     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
0362                 sizeof(struct i3200_priv));
0363     if (!mci)
0364         return -ENOMEM;
0365
0366     edac_dbg(3, "MC: init mci\n");
0367
0368     mci->pdev = &pdev->dev;
0369     mci->mtype_cap = MEM_FLAG_DDR2;
0370
0371     mci->edac_ctl_cap = EDAC_FLAG_SECDED;
0372     mci->edac_cap = EDAC_FLAG_SECDED;
0373
0374     mci->mod_name = EDAC_MOD_STR;
0375     mci->ctl_name = i3200_devs[dev_idx].ctl_name;
0376     mci->dev_name = pci_name(pdev);
0377     mci->edac_check = i3200_check;
0378     mci->ctl_page_to_phys = NULL;
0379     priv = mci->pvt_info;
0380     priv->window = window;
0381
0382     stacked = i3200_is_stacked(pdev, drbs);
0383
0384     /*
0385      * The dram rank boundary (DRB) reg values are boundary addresses
0386      * for each DRAM rank with a granularity of 64MB.  DRB regs are
0387      * cumulative; the last one will contain the total memory
0388      * contained in all ranks.
0389      */
0390     for (i = 0; i < I3200_DIMMS; i++) {
0391         unsigned long nr_pages;
0392
0393         for (j = 0; j < nr_channels; j++) {
0394             struct dimm_info *dimm = edac_get_dimm(mci, i, j, 0);
0395
0396             nr_pages = drb_to_nr_pages(drbs, stacked, j, i);
0397             if (nr_pages == 0)
0398                 continue;
0399
0400             edac_dbg(0, "csrow %d, channel %d%s, size = %ld MiB\n", i, j,
0401                  stacked ? " (stacked)" : "", PAGES_TO_MiB(nr_pages));
0402
0403             dimm->nr_pages = nr_pages;
0404             dimm->grain = nr_pages << PAGE_SHIFT;
0405             dimm->mtype = MEM_DDR2;
0406             dimm->dtype = DEV_UNKNOWN;
0407             dimm->edac_mode = EDAC_UNKNOWN;
0408         }
0409     }
0410
0411     i3200_clear_error_info(mci);
0412
0413     rc = -ENODEV;
0414     if (edac_mc_add_mc(mci)) {
0415         edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
0416         goto fail;
0417     }
0418
0419     /* get this far and it's successful */
0420     edac_dbg(3, "MC: success\n");
0421     return 0;
0422
0423 fail:
0424     iounmap(window);
0425     if (mci)
0426         edac_mc_free(mci);
0427
0428     return rc;
0429 }
0430
0431 static int i3200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0432 {
0433     int rc;
0434
0435     edac_dbg(0, "MC:\n");
0436
0437     if (pci_enable_device(pdev) < 0)
0438         return -EIO;
0439
0440     rc = i3200_probe1(pdev, ent->driver_data);
0441     if (!mci_pdev)
0442         mci_pdev = pci_dev_get(pdev);
0443
0444     return rc;
0445 }
0446
0447 static void i3200_remove_one(struct pci_dev *pdev)
0448 {
0449     struct mem_ctl_info *mci;
0450     struct i3200_priv *priv;
0451
0452     edac_dbg(0, "\n");
0453
0454     mci = edac_mc_del_mc(&pdev->dev);
0455     if (!mci)
0456         return;
0457
0458     priv = mci->pvt_info;
0459     iounmap(priv->window);
0460
0461     edac_mc_free(mci);
0462
0463     pci_disable_device(pdev);
0464 }
0465
0466 static const struct pci_device_id i3200_pci_tbl[] = {
0467     {
0468         PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0469         I3200},
0470     {
0471         0,
0472     }            /* 0 terminated list. */
0473 };
0474
0475 MODULE_DEVICE_TABLE(pci, i3200_pci_tbl);
0476
0477 static struct pci_driver i3200_driver = {
0478     .name = EDAC_MOD_STR,
0479     .probe = i3200_init_one,
0480     .remove = i3200_remove_one,
0481     .id_table = i3200_pci_tbl,
0482 };
0483
0484 static int __init i3200_init(void)
0485 {
0486     int pci_rc;
0487
0488     edac_dbg(3, "MC:\n");
0489
0490     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0491     opstate_init();
0492
0493     pci_rc = pci_register_driver(&i3200_driver);
0494     if (pci_rc < 0)
0495         goto fail0;
0496
0497     if (!mci_pdev) {
0498         i3200_registered = 0;
0499         mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0500                 PCI_DEVICE_ID_INTEL_3200_HB, NULL);
0501         if (!mci_pdev) {
0502             edac_dbg(0, "i3200 pci_get_device fail\n");
0503             pci_rc = -ENODEV;
0504             goto fail1;
0505         }
0506
0507         pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
0508         if (pci_rc < 0) {
0509             edac_dbg(0, "i3200 init fail\n");
0510             pci_rc = -ENODEV;
0511             goto fail1;
0512         }
0513     }
0514
0515     return 0;
0516
0517 fail1:
0518     pci_unregister_driver(&i3200_driver);
0519
0520 fail0:
0521     pci_dev_put(mci_pdev);
0522
0523     return pci_rc;
0524 }
0525
0526 static void __exit i3200_exit(void)
0527 {
0528     edac_dbg(3, "MC:\n");
0529
0530     pci_unregister_driver(&i3200_driver);
0531     if (!i3200_registered) {
0532         i3200_remove_one(mci_pdev);
0533         pci_dev_put(mci_pdev);
0534     }
0535 }
0536
0537 module_init(i3200_init);
0538 module_exit(i3200_exit);
0539
0540 MODULE_LICENSE("GPL");
0541 MODULE_AUTHOR("Akamai Technologies, Inc.");
0542 MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers");
0543
0544 module_param(edac_op_state, int, 0444);
0545 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");