drivers/edac/i3000_edac.c

0001 /*
0002  * Intel 3000/3010 Memory Controller kernel module
0003  * Copyright (C) 2007 Akamai Technologies, Inc.
0004  * Shamelessly copied from:
0005  *  Intel D82875P Memory Controller kernel module
0006  *  (C) 2003 Linux Networx (http://lnxi.com)
0007  *
0008  * This file may be distributed under the terms of the
0009  * GNU General Public License.
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/pci.h>
0015 #include <linux/pci_ids.h>
0016 #include <linux/edac.h>
0017 #include "edac_module.h"
0018
0019 #define EDAC_MOD_STR        "i3000_edac"
0020
0021 #define I3000_RANKS     8
0022 #define I3000_RANKS_PER_CHANNEL 4
0023 #define I3000_CHANNELS      2
0024
0025 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
0026
0027 #define I3000_MCHBAR        0x44    /* MCH Memory Mapped Register BAR */
0028 #define I3000_MCHBAR_MASK   0xffffc000
0029 #define I3000_MMR_WINDOW_SIZE   16384
0030
0031 #define I3000_EDEAP 0x70    /* Extended DRAM Error Address Pointer (8b)
0032                  *
0033                  * 7:1   reserved
0034                  * 0     bit 32 of address
0035                  */
0036 #define I3000_DEAP  0x58    /* DRAM Error Address Pointer (32b)
0037                  *
0038                  * 31:7  address
0039                  * 6:1   reserved
0040                  * 0     Error channel 0/1
0041                  */
0042 #define I3000_DEAP_GRAIN        (1 << 7)
0043
0044 /*
0045  * Helper functions to decode the DEAP/EDEAP hardware registers.
0046  *
0047  * The type promotion here is deliberate; we're deriving an
0048  * unsigned long pfn and offset from hardware regs which are u8/u32.
0049  */
0050
0051 static inline unsigned long deap_pfn(u8 edeap, u32 deap)
0052 {
0053     deap >>= PAGE_SHIFT;
0054     deap |= (edeap & 1) << (32 - PAGE_SHIFT);
0055     return deap;
0056 }
0057
0058 static inline unsigned long deap_offset(u32 deap)
0059 {
0060     return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
0061 }
0062
0063 static inline int deap_channel(u32 deap)
0064 {
0065     return deap & 1;
0066 }
0067
0068 #define I3000_DERRSYN   0x5c    /* DRAM Error Syndrome (8b)
0069                  *
0070                  *  7:0  DRAM ECC Syndrome
0071                  */
0072
0073 #define I3000_ERRSTS    0xc8    /* Error Status Register (16b)
0074                  *
0075                  * 15:12 reserved
0076                  * 11    MCH Thermal Sensor Event
0077                  *         for SMI/SCI/SERR
0078                  * 10    reserved
0079                  *  9    LOCK to non-DRAM Memory Flag (LCKF)
0080                  *  8    Received Refresh Timeout Flag (RRTOF)
0081                  *  7:2  reserved
0082                  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
0083                  *  0    Single-bit DRAM ECC Error Flag (DSERR)
0084                  */
0085 #define I3000_ERRSTS_BITS   0x0b03  /* bits which indicate errors */
0086 #define I3000_ERRSTS_UE     0x0002
0087 #define I3000_ERRSTS_CE     0x0001
0088
0089 #define I3000_ERRCMD    0xca    /* Error Command (16b)
0090                  *
0091                  * 15:12 reserved
0092                  * 11    SERR on MCH Thermal Sensor Event
0093                  *         (TSESERR)
0094                  * 10    reserved
0095                  *  9    SERR on LOCK to non-DRAM Memory
0096                  *         (LCKERR)
0097                  *  8    SERR on DRAM Refresh Timeout
0098                  *         (DRTOERR)
0099                  *  7:2  reserved
0100                  *  1    SERR Multi-Bit DRAM ECC Error
0101                  *         (DMERR)
0102                  *  0    SERR on Single-Bit ECC Error
0103                  *         (DSERR)
0104                  */
0105
0106 /* Intel  MMIO register space - device 0 function 0 - MMR space */
0107
0108 #define I3000_DRB_SHIFT 25  /* 32MiB grain */
0109
0110 #define I3000_C0DRB 0x100   /* Channel 0 DRAM Rank Boundary (8b x 4)
0111                  *
0112                  * 7:0   Channel 0 DRAM Rank Boundary Address
0113                  */
0114 #define I3000_C1DRB 0x180   /* Channel 1 DRAM Rank Boundary (8b x 4)
0115                  *
0116                  * 7:0   Channel 1 DRAM Rank Boundary Address
0117                  */
0118
0119 #define I3000_C0DRA 0x108   /* Channel 0 DRAM Rank Attribute (8b x 2)
0120                  *
0121                  * 7     reserved
0122                  * 6:4   DRAM odd Rank Attribute
0123                  * 3     reserved
0124                  * 2:0   DRAM even Rank Attribute
0125                  *
0126                  * Each attribute defines the page
0127                  * size of the corresponding rank:
0128                  *     000: unpopulated
0129                  *     001: reserved
0130                  *     010: 4 KB
0131                  *     011: 8 KB
0132                  *     100: 16 KB
0133                  *     Others: reserved
0134                  */
0135 #define I3000_C1DRA 0x188   /* Channel 1 DRAM Rank Attribute (8b x 2) */
0136
0137 static inline unsigned char odd_rank_attrib(unsigned char dra)
0138 {
0139     return (dra & 0x70) >> 4;
0140 }
0141
0142 static inline unsigned char even_rank_attrib(unsigned char dra)
0143 {
0144     return dra & 0x07;
0145 }
0146
0147 #define I3000_C0DRC0    0x120   /* DRAM Controller Mode 0 (32b)
0148                  *
0149                  * 31:30 reserved
0150                  * 29    Initialization Complete (IC)
0151                  * 28:11 reserved
0152                  * 10:8  Refresh Mode Select (RMS)
0153                  * 7     reserved
0154                  * 6:4   Mode Select (SMS)
0155                  * 3:2   reserved
0156                  * 1:0   DRAM Type (DT)
0157                  */
0158
0159 #define I3000_C0DRC1    0x124   /* DRAM Controller Mode 1 (32b)
0160                  *
0161                  * 31    Enhanced Addressing Enable (ENHADE)
0162                  * 30:0  reserved
0163                  */
0164
0165 enum i3000p_chips {
0166     I3000 = 0,
0167 };
0168
0169 struct i3000_dev_info {
0170     const char *ctl_name;
0171 };
0172
0173 struct i3000_error_info {
0174     u16 errsts;
0175     u8 derrsyn;
0176     u8 edeap;
0177     u32 deap;
0178     u16 errsts2;
0179 };
0180
0181 static const struct i3000_dev_info i3000_devs[] = {
0182     [I3000] = {
0183         .ctl_name = "i3000"},
0184 };
0185
0186 static struct pci_dev *mci_pdev;
0187 static int i3000_registered = 1;
0188 static struct edac_pci_ctl_info *i3000_pci;
0189
0190 static void i3000_get_error_info(struct mem_ctl_info *mci,
0191                  struct i3000_error_info *info)
0192 {
0193     struct pci_dev *pdev;
0194
0195     pdev = to_pci_dev(mci->pdev);
0196
0197     /*
0198      * This is a mess because there is no atomic way to read all the
0199      * registers at once and the registers can transition from CE being
0200      * overwritten by UE.
0201      */
0202     pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
0203     if (!(info->errsts & I3000_ERRSTS_BITS))
0204         return;
0205     pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
0206     pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
0207     pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
0208     pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
0209
0210     /*
0211      * If the error is the same for both reads then the first set
0212      * of reads is valid.  If there is a change then there is a CE
0213      * with no info and the second set of reads is valid and
0214      * should be UE info.
0215      */
0216     if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
0217         pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
0218         pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
0219         pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
0220     }
0221
0222     /*
0223      * Clear any error bits.
0224      * (Yes, we really clear bits by writing 1 to them.)
0225      */
0226     pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
0227              I3000_ERRSTS_BITS);
0228 }
0229
0230 static int i3000_process_error_info(struct mem_ctl_info *mci,
0231                 struct i3000_error_info *info,
0232                 int handle_errors)
0233 {
0234     int row, multi_chan, channel;
0235     unsigned long pfn, offset;
0236
0237     multi_chan = mci->csrows[0]->nr_channels - 1;
0238
0239     if (!(info->errsts & I3000_ERRSTS_BITS))
0240         return 0;
0241
0242     if (!handle_errors)
0243         return 1;
0244
0245     if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
0246         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
0247                      -1, -1, -1,
0248                      "UE overwrote CE", "");
0249         info->errsts = info->errsts2;
0250     }
0251
0252     pfn = deap_pfn(info->edeap, info->deap);
0253     offset = deap_offset(info->deap);
0254     channel = deap_channel(info->deap);
0255
0256     row = edac_mc_find_csrow_by_page(mci, pfn);
0257
0258     if (info->errsts & I3000_ERRSTS_UE)
0259         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0260                      pfn, offset, 0,
0261                      row, -1, -1,
0262                      "i3000 UE", "");
0263     else
0264         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0265                      pfn, offset, info->derrsyn,
0266                      row, multi_chan ? channel : 0, -1,
0267                      "i3000 CE", "");
0268
0269     return 1;
0270 }
0271
0272 static void i3000_check(struct mem_ctl_info *mci)
0273 {
0274     struct i3000_error_info info;
0275
0276     i3000_get_error_info(mci, &info);
0277     i3000_process_error_info(mci, &info, 1);
0278 }
0279
0280 static int i3000_is_interleaved(const unsigned char *c0dra,
0281                 const unsigned char *c1dra,
0282                 const unsigned char *c0drb,
0283                 const unsigned char *c1drb)
0284 {
0285     int i;
0286
0287     /*
0288      * If the channels aren't populated identically then
0289      * we're not interleaved.
0290      */
0291     for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
0292         if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
0293             even_rank_attrib(c0dra[i]) !=
0294                         even_rank_attrib(c1dra[i]))
0295             return 0;
0296
0297     /*
0298      * If the rank boundaries for the two channels are different
0299      * then we're not interleaved.
0300      */
0301     for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
0302         if (c0drb[i] != c1drb[i])
0303             return 0;
0304
0305     return 1;
0306 }
0307
0308 static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
0309 {
0310     int rc;
0311     int i, j;
0312     struct mem_ctl_info *mci = NULL;
0313     struct edac_mc_layer layers[2];
0314     unsigned long last_cumul_size, nr_pages;
0315     int interleaved, nr_channels;
0316     unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
0317     unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
0318     unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
0319     unsigned long mchbar;
0320     void __iomem *window;
0321
0322     edac_dbg(0, "MC:\n");
0323
0324     pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
0325     mchbar &= I3000_MCHBAR_MASK;
0326     window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);
0327     if (!window) {
0328         printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
0329             mchbar);
0330         return -ENODEV;
0331     }
0332
0333     c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
0334     c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
0335     c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
0336     c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
0337
0338     for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
0339         c0drb[i] = readb(window + I3000_C0DRB + i);
0340         c1drb[i] = readb(window + I3000_C1DRB + i);
0341     }
0342
0343     iounmap(window);
0344
0345     /*
0346      * Figure out how many channels we have.
0347      *
0348      * If we have what the datasheet calls "asymmetric channels"
0349      * (essentially the same as what was called "virtual single
0350      * channel mode" in the i82875) then it's a single channel as
0351      * far as EDAC is concerned.
0352      */
0353     interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
0354     nr_channels = interleaved ? 2 : 1;
0355
0356     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0357     layers[0].size = I3000_RANKS / nr_channels;
0358     layers[0].is_virt_csrow = true;
0359     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0360     layers[1].size = nr_channels;
0361     layers[1].is_virt_csrow = false;
0362     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
0363     if (!mci)
0364         return -ENOMEM;
0365
0366     edac_dbg(3, "MC: init mci\n");
0367
0368     mci->pdev = &pdev->dev;
0369     mci->mtype_cap = MEM_FLAG_DDR2;
0370
0371     mci->edac_ctl_cap = EDAC_FLAG_SECDED;
0372     mci->edac_cap = EDAC_FLAG_SECDED;
0373
0374     mci->mod_name = EDAC_MOD_STR;
0375     mci->ctl_name = i3000_devs[dev_idx].ctl_name;
0376     mci->dev_name = pci_name(pdev);
0377     mci->edac_check = i3000_check;
0378     mci->ctl_page_to_phys = NULL;
0379
0380     /*
0381      * The dram rank boundary (DRB) reg values are boundary addresses
0382      * for each DRAM rank with a granularity of 32MB.  DRB regs are
0383      * cumulative; the last one will contain the total memory
0384      * contained in all ranks.
0385      *
0386      * If we're in interleaved mode then we're only walking through
0387      * the ranks of controller 0, so we double all the values we see.
0388      */
0389     for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
0390         u8 value;
0391         u32 cumul_size;
0392         struct csrow_info *csrow = mci->csrows[i];
0393
0394         value = drb[i];
0395         cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
0396         if (interleaved)
0397             cumul_size <<= 1;
0398         edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
0399         if (cumul_size == last_cumul_size)
0400             continue;
0401
0402         csrow->first_page = last_cumul_size;
0403         csrow->last_page = cumul_size - 1;
0404         nr_pages = cumul_size - last_cumul_size;
0405         last_cumul_size = cumul_size;
0406
0407         for (j = 0; j < nr_channels; j++) {
0408             struct dimm_info *dimm = csrow->channels[j]->dimm;
0409
0410             dimm->nr_pages = nr_pages / nr_channels;
0411             dimm->grain = I3000_DEAP_GRAIN;
0412             dimm->mtype = MEM_DDR2;
0413             dimm->dtype = DEV_UNKNOWN;
0414             dimm->edac_mode = EDAC_UNKNOWN;
0415         }
0416     }
0417
0418     /*
0419      * Clear any error bits.
0420      * (Yes, we really clear bits by writing 1 to them.)
0421      */
0422     pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
0423              I3000_ERRSTS_BITS);
0424
0425     rc = -ENODEV;
0426     if (edac_mc_add_mc(mci)) {
0427         edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
0428         goto fail;
0429     }
0430
0431     /* allocating generic PCI control info */
0432     i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
0433     if (!i3000_pci) {
0434         printk(KERN_WARNING
0435             "%s(): Unable to create PCI control\n",
0436             __func__);
0437         printk(KERN_WARNING
0438             "%s(): PCI error report via EDAC not setup\n",
0439             __func__);
0440     }
0441
0442     /* get this far and it's successful */
0443     edac_dbg(3, "MC: success\n");
0444     return 0;
0445
0446 fail:
0447     if (mci)
0448         edac_mc_free(mci);
0449
0450     return rc;
0451 }
0452
0453 /* returns count (>= 0), or negative on error */
0454 static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0455 {
0456     int rc;
0457
0458     edac_dbg(0, "MC:\n");
0459
0460     if (pci_enable_device(pdev) < 0)
0461         return -EIO;
0462
0463     rc = i3000_probe1(pdev, ent->driver_data);
0464     if (!mci_pdev)
0465         mci_pdev = pci_dev_get(pdev);
0466
0467     return rc;
0468 }
0469
0470 static void i3000_remove_one(struct pci_dev *pdev)
0471 {
0472     struct mem_ctl_info *mci;
0473
0474     edac_dbg(0, "\n");
0475
0476     if (i3000_pci)
0477         edac_pci_release_generic_ctl(i3000_pci);
0478
0479     mci = edac_mc_del_mc(&pdev->dev);
0480     if (!mci)
0481         return;
0482
0483     edac_mc_free(mci);
0484 }
0485
0486 static const struct pci_device_id i3000_pci_tbl[] = {
0487     {
0488      PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0489      I3000},
0490     {
0491      0,
0492      }          /* 0 terminated list. */
0493 };
0494
0495 MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
0496
0497 static struct pci_driver i3000_driver = {
0498     .name = EDAC_MOD_STR,
0499     .probe = i3000_init_one,
0500     .remove = i3000_remove_one,
0501     .id_table = i3000_pci_tbl,
0502 };
0503
0504 static int __init i3000_init(void)
0505 {
0506     int pci_rc;
0507
0508     edac_dbg(3, "MC:\n");
0509
0510     /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0511     opstate_init();
0512
0513     pci_rc = pci_register_driver(&i3000_driver);
0514     if (pci_rc < 0)
0515         goto fail0;
0516
0517     if (!mci_pdev) {
0518         i3000_registered = 0;
0519         mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
0520                     PCI_DEVICE_ID_INTEL_3000_HB, NULL);
0521         if (!mci_pdev) {
0522             edac_dbg(0, "i3000 pci_get_device fail\n");
0523             pci_rc = -ENODEV;
0524             goto fail1;
0525         }
0526
0527         pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
0528         if (pci_rc < 0) {
0529             edac_dbg(0, "i3000 init fail\n");
0530             pci_rc = -ENODEV;
0531             goto fail1;
0532         }
0533     }
0534
0535     return 0;
0536
0537 fail1:
0538     pci_unregister_driver(&i3000_driver);
0539
0540 fail0:
0541     pci_dev_put(mci_pdev);
0542
0543     return pci_rc;
0544 }
0545
0546 static void __exit i3000_exit(void)
0547 {
0548     edac_dbg(3, "MC:\n");
0549
0550     pci_unregister_driver(&i3000_driver);
0551     if (!i3000_registered) {
0552         i3000_remove_one(mci_pdev);
0553         pci_dev_put(mci_pdev);
0554     }
0555 }
0556
0557 module_init(i3000_init);
0558 module_exit(i3000_exit);
0559
0560 MODULE_LICENSE("GPL");
0561 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
0562 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
0563
0564 module_param(edac_op_state, int, 0444);
0565 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");