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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for Intel(R) 10nm server memory controller.
0004  * Copyright (c) 2019, Intel Corporation.
0005  *
0006  */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/io.h>
0010 #include <asm/cpu_device_id.h>
0011 #include <asm/intel-family.h>
0012 #include <asm/mce.h>
0013 #include "edac_module.h"
0014 #include "skx_common.h"
0015 
0016 #define I10NM_REVISION  "v0.0.5"
0017 #define EDAC_MOD_STR    "i10nm_edac"
0018 
0019 /* Debug macros */
0020 #define i10nm_printk(level, fmt, arg...)    \
0021     edac_printk(level, "i10nm", fmt, ##arg)
0022 
0023 #define I10NM_GET_SCK_BAR(d, reg)   \
0024     pci_read_config_dword((d)->uracu, 0xd0, &(reg))
0025 #define I10NM_GET_IMC_BAR(d, i, reg)    \
0026     pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
0027 #define I10NM_GET_SAD(d, offset, i, reg)\
0028     pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
0029 #define I10NM_GET_HBM_IMC_BAR(d, reg)   \
0030     pci_read_config_dword((d)->uracu, 0xd4, &(reg))
0031 #define I10NM_GET_CAPID3_CFG(d, reg)    \
0032     pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
0033 #define I10NM_GET_DIMMMTR(m, i, j)  \
0034     readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
0035     (i) * (m)->chan_mmio_sz + (j) * 4)
0036 #define I10NM_GET_MCDDRTCFG(m, i)   \
0037     readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
0038     (i) * (m)->chan_mmio_sz)
0039 #define I10NM_GET_MCMTR(m, i)       \
0040     readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
0041     (i) * (m)->chan_mmio_sz)
0042 #define I10NM_GET_AMAP(m, i)        \
0043     readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
0044     (i) * (m)->chan_mmio_sz)
0045 #define I10NM_GET_REG32(m, i, offset)   \
0046     readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
0047 #define I10NM_GET_REG64(m, i, offset)   \
0048     readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
0049 #define I10NM_SET_REG32(m, i, offset, v)    \
0050     writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
0051 
0052 #define I10NM_GET_SCK_MMIO_BASE(reg)    (GET_BITFIELD(reg, 0, 28) << 23)
0053 #define I10NM_GET_IMC_MMIO_OFFSET(reg)  (GET_BITFIELD(reg, 0, 10) << 12)
0054 #define I10NM_GET_IMC_MMIO_SIZE(reg)    ((GET_BITFIELD(reg, 13, 23) - \
0055                      GET_BITFIELD(reg, 0, 10) + 1) << 12)
0056 #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg)  \
0057     ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
0058 
0059 #define I10NM_HBM_IMC_MMIO_SIZE     0x9000
0060 #define I10NM_IS_HBM_PRESENT(reg)   GET_BITFIELD(reg, 27, 30)
0061 #define I10NM_IS_HBM_IMC(reg)       GET_BITFIELD(reg, 29, 29)
0062 
0063 #define I10NM_MAX_SAD           16
0064 #define I10NM_SAD_ENABLE(reg)       GET_BITFIELD(reg, 0, 0)
0065 #define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5)
0066 
0067 #define RETRY_RD_ERR_LOG_UC     BIT(1)
0068 #define RETRY_RD_ERR_LOG_NOOVER     BIT(14)
0069 #define RETRY_RD_ERR_LOG_EN     BIT(15)
0070 #define RETRY_RD_ERR_LOG_NOOVER_UC  (BIT(14) | BIT(1))
0071 #define RETRY_RD_ERR_LOG_OVER_UC_V  (BIT(2) | BIT(1) | BIT(0))
0072 
0073 static struct list_head *i10nm_edac_list;
0074 
0075 static struct res_config *res_cfg;
0076 static int retry_rd_err_log;
0077 
0078 static u32 offsets_scrub_icx[]  = {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8};
0079 static u32 offsets_scrub_spr[]  = {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8};
0080 static u32 offsets_demand_icx[] = {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0};
0081 static u32 offsets_demand_spr[] = {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0};
0082 
0083 static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable)
0084 {
0085     u32 s, d;
0086 
0087     if (!imc->mbase)
0088         return;
0089 
0090     s = I10NM_GET_REG32(imc, chan, res_cfg->offsets_scrub[0]);
0091     d = I10NM_GET_REG32(imc, chan, res_cfg->offsets_demand[0]);
0092 
0093     if (enable) {
0094         /* Save default configurations */
0095         imc->chan[chan].retry_rd_err_log_s = s;
0096         imc->chan[chan].retry_rd_err_log_d = d;
0097 
0098         s &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
0099         s |=  RETRY_RD_ERR_LOG_EN;
0100         d &= ~RETRY_RD_ERR_LOG_NOOVER_UC;
0101         d |=  RETRY_RD_ERR_LOG_EN;
0102     } else {
0103         /* Restore default configurations */
0104         if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC)
0105             s |=  RETRY_RD_ERR_LOG_UC;
0106         if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER)
0107             s |=  RETRY_RD_ERR_LOG_NOOVER;
0108         if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN))
0109             s &= ~RETRY_RD_ERR_LOG_EN;
0110         if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC)
0111             d |=  RETRY_RD_ERR_LOG_UC;
0112         if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER)
0113             d |=  RETRY_RD_ERR_LOG_NOOVER;
0114         if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN))
0115             d &= ~RETRY_RD_ERR_LOG_EN;
0116     }
0117 
0118     I10NM_SET_REG32(imc, chan, res_cfg->offsets_scrub[0], s);
0119     I10NM_SET_REG32(imc, chan, res_cfg->offsets_demand[0], d);
0120 }
0121 
0122 static void enable_retry_rd_err_log(bool enable)
0123 {
0124     struct skx_dev *d;
0125     int i, j;
0126 
0127     edac_dbg(2, "\n");
0128 
0129     list_for_each_entry(d, i10nm_edac_list, list)
0130         for (i = 0; i < I10NM_NUM_IMC; i++)
0131             for (j = 0; j < I10NM_NUM_CHANNELS; j++)
0132                 __enable_retry_rd_err_log(&d->imc[i], j, enable);
0133 }
0134 
0135 static void show_retry_rd_err_log(struct decoded_addr *res, char *msg,
0136                   int len, bool scrub_err)
0137 {
0138     struct skx_imc *imc = &res->dev->imc[res->imc];
0139     u32 log0, log1, log2, log3, log4;
0140     u32 corr0, corr1, corr2, corr3;
0141     u64 log2a, log5;
0142     u32 *offsets;
0143     int n;
0144 
0145     if (!imc->mbase)
0146         return;
0147 
0148     offsets = scrub_err ? res_cfg->offsets_scrub : res_cfg->offsets_demand;
0149 
0150     log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]);
0151     log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]);
0152     log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]);
0153     log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]);
0154     log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]);
0155 
0156     if (res_cfg->type == SPR) {
0157         log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]);
0158         n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.16llx %.8x %.8x %.16llx]",
0159                  log0, log1, log2a, log3, log4, log5);
0160     } else {
0161         log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]);
0162         n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x %.16llx]",
0163                  log0, log1, log2, log3, log4, log5);
0164     }
0165 
0166     corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18);
0167     corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c);
0168     corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20);
0169     corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24);
0170 
0171     if (len - n > 0)
0172         snprintf(msg + n, len - n,
0173              " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]",
0174              corr0 & 0xffff, corr0 >> 16,
0175              corr1 & 0xffff, corr1 >> 16,
0176              corr2 & 0xffff, corr2 >> 16,
0177              corr3 & 0xffff, corr3 >> 16);
0178 
0179     /* Clear status bits */
0180     if (retry_rd_err_log == 2 && (log0 & RETRY_RD_ERR_LOG_OVER_UC_V)) {
0181         log0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V;
0182         I10NM_SET_REG32(imc, res->channel, offsets[0], log0);
0183     }
0184 }
0185 
0186 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
0187                        unsigned int dev, unsigned int fun)
0188 {
0189     struct pci_dev *pdev;
0190 
0191     pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
0192     if (!pdev) {
0193         edac_dbg(2, "No device %02x:%02x.%x\n",
0194              bus, dev, fun);
0195         return NULL;
0196     }
0197 
0198     if (unlikely(pci_enable_device(pdev) < 0)) {
0199         edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
0200              bus, dev, fun);
0201         return NULL;
0202     }
0203 
0204     pci_dev_get(pdev);
0205 
0206     return pdev;
0207 }
0208 
0209 static bool i10nm_check_2lm(struct res_config *cfg)
0210 {
0211     struct skx_dev *d;
0212     u32 reg;
0213     int i;
0214 
0215     list_for_each_entry(d, i10nm_edac_list, list) {
0216         d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1],
0217                          PCI_SLOT(cfg->sad_all_devfn),
0218                          PCI_FUNC(cfg->sad_all_devfn));
0219         if (!d->sad_all)
0220             continue;
0221 
0222         for (i = 0; i < I10NM_MAX_SAD; i++) {
0223             I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg);
0224             if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) {
0225                 edac_dbg(2, "2-level memory configuration.\n");
0226                 return true;
0227             }
0228         }
0229     }
0230 
0231     return false;
0232 }
0233 
0234 static int i10nm_get_ddr_munits(void)
0235 {
0236     struct pci_dev *mdev;
0237     void __iomem *mbase;
0238     unsigned long size;
0239     struct skx_dev *d;
0240     int i, j = 0;
0241     u32 reg, off;
0242     u64 base;
0243 
0244     list_for_each_entry(d, i10nm_edac_list, list) {
0245         d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
0246         if (!d->util_all)
0247             return -ENODEV;
0248 
0249         d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
0250         if (!d->uracu)
0251             return -ENODEV;
0252 
0253         if (I10NM_GET_SCK_BAR(d, reg)) {
0254             i10nm_printk(KERN_ERR, "Failed to socket bar\n");
0255             return -ENODEV;
0256         }
0257 
0258         base = I10NM_GET_SCK_MMIO_BASE(reg);
0259         edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
0260              j++, base, reg);
0261 
0262         for (i = 0; i < I10NM_NUM_DDR_IMC; i++) {
0263             mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
0264                            12 + i, 0);
0265             if (i == 0 && !mdev) {
0266                 i10nm_printk(KERN_ERR, "No IMC found\n");
0267                 return -ENODEV;
0268             }
0269             if (!mdev)
0270                 continue;
0271 
0272             d->imc[i].mdev = mdev;
0273 
0274             if (I10NM_GET_IMC_BAR(d, i, reg)) {
0275                 i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
0276                 return -ENODEV;
0277             }
0278 
0279             off  = I10NM_GET_IMC_MMIO_OFFSET(reg);
0280             size = I10NM_GET_IMC_MMIO_SIZE(reg);
0281             edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
0282                  i, base + off, size, reg);
0283 
0284             mbase = ioremap(base + off, size);
0285             if (!mbase) {
0286                 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
0287                          base + off);
0288                 return -ENODEV;
0289             }
0290 
0291             d->imc[i].mbase = mbase;
0292         }
0293     }
0294 
0295     return 0;
0296 }
0297 
0298 static bool i10nm_check_hbm_imc(struct skx_dev *d)
0299 {
0300     u32 reg;
0301 
0302     if (I10NM_GET_CAPID3_CFG(d, reg)) {
0303         i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
0304         return false;
0305     }
0306 
0307     return I10NM_IS_HBM_PRESENT(reg) != 0;
0308 }
0309 
0310 static int i10nm_get_hbm_munits(void)
0311 {
0312     struct pci_dev *mdev;
0313     void __iomem *mbase;
0314     u32 reg, off, mcmtr;
0315     struct skx_dev *d;
0316     int i, lmc;
0317     u64 base;
0318 
0319     list_for_each_entry(d, i10nm_edac_list, list) {
0320         d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3);
0321         if (!d->pcu_cr3)
0322             return -ENODEV;
0323 
0324         if (!i10nm_check_hbm_imc(d)) {
0325             i10nm_printk(KERN_DEBUG, "No hbm memory\n");
0326             return -ENODEV;
0327         }
0328 
0329         if (I10NM_GET_SCK_BAR(d, reg)) {
0330             i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
0331             return -ENODEV;
0332         }
0333         base = I10NM_GET_SCK_MMIO_BASE(reg);
0334 
0335         if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
0336             i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
0337             return -ENODEV;
0338         }
0339         base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);
0340 
0341         lmc = I10NM_NUM_DDR_IMC;
0342 
0343         for (i = 0; i < I10NM_NUM_HBM_IMC; i++) {
0344             mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
0345                            12 + i / 4, 1 + i % 4);
0346             if (i == 0 && !mdev) {
0347                 i10nm_printk(KERN_ERR, "No hbm mc found\n");
0348                 return -ENODEV;
0349             }
0350             if (!mdev)
0351                 continue;
0352 
0353             d->imc[lmc].mdev = mdev;
0354             off = i * I10NM_HBM_IMC_MMIO_SIZE;
0355 
0356             edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
0357                  lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);
0358 
0359             mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE);
0360             if (!mbase) {
0361                 pci_dev_put(d->imc[lmc].mdev);
0362                 d->imc[lmc].mdev = NULL;
0363 
0364                 i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
0365                          base + off);
0366                 return -ENOMEM;
0367             }
0368 
0369             d->imc[lmc].mbase = mbase;
0370             d->imc[lmc].hbm_mc = true;
0371 
0372             mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
0373             if (!I10NM_IS_HBM_IMC(mcmtr)) {
0374                 iounmap(d->imc[lmc].mbase);
0375                 d->imc[lmc].mbase = NULL;
0376                 d->imc[lmc].hbm_mc = false;
0377                 pci_dev_put(d->imc[lmc].mdev);
0378                 d->imc[lmc].mdev = NULL;
0379 
0380                 i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
0381                 return -ENODEV;
0382             }
0383 
0384             lmc++;
0385         }
0386     }
0387 
0388     return 0;
0389 }
0390 
0391 static struct res_config i10nm_cfg0 = {
0392     .type           = I10NM,
0393     .decs_did       = 0x3452,
0394     .busno_cfg_offset   = 0xcc,
0395     .ddr_chan_mmio_sz   = 0x4000,
0396     .sad_all_devfn      = PCI_DEVFN(29, 0),
0397     .sad_all_offset     = 0x108,
0398     .offsets_scrub      = offsets_scrub_icx,
0399     .offsets_demand     = offsets_demand_icx,
0400 };
0401 
0402 static struct res_config i10nm_cfg1 = {
0403     .type           = I10NM,
0404     .decs_did       = 0x3452,
0405     .busno_cfg_offset   = 0xd0,
0406     .ddr_chan_mmio_sz   = 0x4000,
0407     .sad_all_devfn      = PCI_DEVFN(29, 0),
0408     .sad_all_offset     = 0x108,
0409     .offsets_scrub      = offsets_scrub_icx,
0410     .offsets_demand     = offsets_demand_icx,
0411 };
0412 
0413 static struct res_config spr_cfg = {
0414     .type           = SPR,
0415     .decs_did       = 0x3252,
0416     .busno_cfg_offset   = 0xd0,
0417     .ddr_chan_mmio_sz   = 0x8000,
0418     .hbm_chan_mmio_sz   = 0x4000,
0419     .support_ddr5       = true,
0420     .sad_all_devfn      = PCI_DEVFN(10, 0),
0421     .sad_all_offset     = 0x300,
0422     .offsets_scrub      = offsets_scrub_spr,
0423     .offsets_demand     = offsets_demand_spr,
0424 };
0425 
0426 static const struct x86_cpu_id i10nm_cpuids[] = {
0427     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
0428     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D,    X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
0429     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,     X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
0430     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X,     X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
0431     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D,     X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
0432     X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X,  X86_STEPPINGS(0x0, 0xf), &spr_cfg),
0433     {}
0434 };
0435 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
0436 
0437 static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
0438 {
0439     u32 mcmtr;
0440 
0441     mcmtr = I10NM_GET_MCMTR(imc, chan);
0442     edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
0443 
0444     return !!GET_BITFIELD(mcmtr, 2, 2);
0445 }
0446 
0447 static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
0448                  struct res_config *cfg)
0449 {
0450     struct skx_pvt *pvt = mci->pvt_info;
0451     struct skx_imc *imc = pvt->imc;
0452     u32 mtr, amap, mcddrtcfg;
0453     struct dimm_info *dimm;
0454     int i, j, ndimms;
0455 
0456     for (i = 0; i < imc->num_channels; i++) {
0457         if (!imc->mbase)
0458             continue;
0459 
0460         ndimms = 0;
0461         amap = I10NM_GET_AMAP(imc, i);
0462         mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
0463         for (j = 0; j < imc->num_dimms; j++) {
0464             dimm = edac_get_dimm(mci, i, j, 0);
0465             mtr = I10NM_GET_DIMMMTR(imc, i, j);
0466             edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
0467                  mtr, mcddrtcfg, imc->mc, i, j);
0468 
0469             if (IS_DIMM_PRESENT(mtr))
0470                 ndimms += skx_get_dimm_info(mtr, 0, amap, dimm,
0471                                 imc, i, j, cfg);
0472             else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
0473                 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
0474                                   EDAC_MOD_STR);
0475         }
0476         if (ndimms && !i10nm_check_ecc(imc, i)) {
0477             i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
0478                      imc->mc, i);
0479             return -ENODEV;
0480         }
0481     }
0482 
0483     return 0;
0484 }
0485 
0486 static struct notifier_block i10nm_mce_dec = {
0487     .notifier_call  = skx_mce_check_error,
0488     .priority   = MCE_PRIO_EDAC,
0489 };
0490 
0491 #ifdef CONFIG_EDAC_DEBUG
0492 /*
0493  * Debug feature.
0494  * Exercise the address decode logic by writing an address to
0495  * /sys/kernel/debug/edac/i10nm_test/addr.
0496  */
0497 static struct dentry *i10nm_test;
0498 
0499 static int debugfs_u64_set(void *data, u64 val)
0500 {
0501     struct mce m;
0502 
0503     pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
0504 
0505     memset(&m, 0, sizeof(m));
0506     /* ADDRV + MemRd + Unknown channel */
0507     m.status = MCI_STATUS_ADDRV + 0x90;
0508     /* One corrected error */
0509     m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
0510     m.addr = val;
0511     skx_mce_check_error(NULL, 0, &m);
0512 
0513     return 0;
0514 }
0515 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
0516 
0517 static void setup_i10nm_debug(void)
0518 {
0519     i10nm_test = edac_debugfs_create_dir("i10nm_test");
0520     if (!i10nm_test)
0521         return;
0522 
0523     if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
0524                       NULL, &fops_u64_wo)) {
0525         debugfs_remove(i10nm_test);
0526         i10nm_test = NULL;
0527     }
0528 }
0529 
0530 static void teardown_i10nm_debug(void)
0531 {
0532     debugfs_remove_recursive(i10nm_test);
0533 }
0534 #else
0535 static inline void setup_i10nm_debug(void) {}
0536 static inline void teardown_i10nm_debug(void) {}
0537 #endif /*CONFIG_EDAC_DEBUG*/
0538 
0539 static int __init i10nm_init(void)
0540 {
0541     u8 mc = 0, src_id = 0, node_id = 0;
0542     const struct x86_cpu_id *id;
0543     struct res_config *cfg;
0544     const char *owner;
0545     struct skx_dev *d;
0546     int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
0547     u64 tolm, tohm;
0548 
0549     edac_dbg(2, "\n");
0550 
0551     owner = edac_get_owner();
0552     if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
0553         return -EBUSY;
0554 
0555     if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
0556         return -ENODEV;
0557 
0558     id = x86_match_cpu(i10nm_cpuids);
0559     if (!id)
0560         return -ENODEV;
0561 
0562     cfg = (struct res_config *)id->driver_data;
0563     res_cfg = cfg;
0564 
0565     rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
0566     if (rc)
0567         return rc;
0568 
0569     rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
0570     if (rc < 0)
0571         goto fail;
0572     if (rc == 0) {
0573         i10nm_printk(KERN_ERR, "No memory controllers found\n");
0574         return -ENODEV;
0575     }
0576 
0577     skx_set_mem_cfg(i10nm_check_2lm(cfg));
0578 
0579     rc = i10nm_get_ddr_munits();
0580 
0581     if (i10nm_get_hbm_munits() && rc)
0582         goto fail;
0583 
0584     list_for_each_entry(d, i10nm_edac_list, list) {
0585         rc = skx_get_src_id(d, 0xf8, &src_id);
0586         if (rc < 0)
0587             goto fail;
0588 
0589         rc = skx_get_node_id(d, &node_id);
0590         if (rc < 0)
0591             goto fail;
0592 
0593         edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
0594         for (i = 0; i < I10NM_NUM_IMC; i++) {
0595             if (!d->imc[i].mdev)
0596                 continue;
0597 
0598             d->imc[i].mc  = mc++;
0599             d->imc[i].lmc = i;
0600             d->imc[i].src_id  = src_id;
0601             d->imc[i].node_id = node_id;
0602             if (d->imc[i].hbm_mc) {
0603                 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
0604                 d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS;
0605                 d->imc[i].num_dimms    = I10NM_NUM_HBM_DIMMS;
0606             } else {
0607                 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
0608                 d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS;
0609                 d->imc[i].num_dimms    = I10NM_NUM_DDR_DIMMS;
0610             }
0611 
0612             rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
0613                           "Intel_10nm Socket", EDAC_MOD_STR,
0614                           i10nm_get_dimm_config, cfg);
0615             if (rc < 0)
0616                 goto fail;
0617         }
0618     }
0619 
0620     rc = skx_adxl_get();
0621     if (rc)
0622         goto fail;
0623 
0624     opstate_init();
0625     mce_register_decode_chain(&i10nm_mce_dec);
0626     setup_i10nm_debug();
0627 
0628     if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
0629         skx_set_decode(NULL, show_retry_rd_err_log);
0630         if (retry_rd_err_log == 2)
0631             enable_retry_rd_err_log(true);
0632     }
0633 
0634     i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
0635 
0636     return 0;
0637 fail:
0638     skx_remove();
0639     return rc;
0640 }
0641 
0642 static void __exit i10nm_exit(void)
0643 {
0644     edac_dbg(2, "\n");
0645 
0646     if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) {
0647         skx_set_decode(NULL, NULL);
0648         if (retry_rd_err_log == 2)
0649             enable_retry_rd_err_log(false);
0650     }
0651 
0652     teardown_i10nm_debug();
0653     mce_unregister_decode_chain(&i10nm_mce_dec);
0654     skx_adxl_put();
0655     skx_remove();
0656 }
0657 
0658 module_init(i10nm_init);
0659 module_exit(i10nm_exit);
0660 
0661 module_param(retry_rd_err_log, int, 0444);
0662 MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)");
0663 
0664 MODULE_LICENSE("GPL v2");
0665 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");
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