drivers/edac/fsl_ddr_edac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Freescale Memory Controller kernel module
0004  *
0005  * Support  Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
0006  * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
0007  * split out from mpc85xx_edac EDAC driver.
0008  *
0009  * Author: Dave Jiang <djiang@mvista.com>
0010  *
0011  * 2006-2007 (c) MontaVista Software, Inc.
0012  */
0013 #ifndef _FSL_DDR_EDAC_H_
0014 #define _FSL_DDR_EDAC_H_
0015
0016 #define fsl_mc_printk(mci, level, fmt, arg...) \
0017     edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
0018
0019 /*
0020  * DRAM error defines
0021  */
0022
0023 /* DDR_SDRAM_CFG */
0024 #define FSL_MC_DDR_SDRAM_CFG    0x0110
0025 #define FSL_MC_CS_BNDS_0        0x0000
0026 #define FSL_MC_CS_BNDS_OFS      0x0008
0027
0028 #define FSL_MC_DATA_ERR_INJECT_HI   0x0e00
0029 #define FSL_MC_DATA_ERR_INJECT_LO   0x0e04
0030 #define FSL_MC_ECC_ERR_INJECT   0x0e08
0031 #define FSL_MC_CAPTURE_DATA_HI  0x0e20
0032 #define FSL_MC_CAPTURE_DATA_LO  0x0e24
0033 #define FSL_MC_CAPTURE_ECC      0x0e28
0034 #define FSL_MC_ERR_DETECT       0x0e40
0035 #define FSL_MC_ERR_DISABLE      0x0e44
0036 #define FSL_MC_ERR_INT_EN       0x0e48
0037 #define FSL_MC_CAPTURE_ATRIBUTES    0x0e4c
0038 #define FSL_MC_CAPTURE_ADDRESS  0x0e50
0039 #define FSL_MC_CAPTURE_EXT_ADDRESS  0x0e54
0040 #define FSL_MC_ERR_SBE      0x0e58
0041
0042 #define DSC_MEM_EN  0x80000000
0043 #define DSC_ECC_EN  0x20000000
0044 #define DSC_RD_EN   0x10000000
0045 #define DSC_DBW_MASK    0x00180000
0046 #define DSC_DBW_32  0x00080000
0047 #define DSC_DBW_64  0x00000000
0048
0049 #define DSC_SDTYPE_MASK     0x07000000
0050 #define DSC_X32_EN  0x00000020
0051
0052 /* Err_Int_En */
0053 #define DDR_EIE_MSEE    0x1 /* memory select */
0054 #define DDR_EIE_SBEE    0x4 /* single-bit ECC error */
0055 #define DDR_EIE_MBEE    0x8 /* multi-bit ECC error */
0056
0057 /* Err_Detect */
0058 #define DDR_EDE_MSE     0x1 /* memory select */
0059 #define DDR_EDE_SBE     0x4 /* single-bit ECC error */
0060 #define DDR_EDE_MBE     0x8 /* multi-bit ECC error */
0061 #define DDR_EDE_MME     0x80000000  /* multiple memory errors */
0062
0063 /* Err_Disable */
0064 #define DDR_EDI_MSED    0x1 /* memory select disable */
0065 #define DDR_EDI_SBED    0x4 /* single-bit ECC error disable */
0066 #define DDR_EDI_MBED    0x8 /* multi-bit ECC error disable */
0067
0068 struct fsl_mc_pdata {
0069     char *name;
0070     int edac_idx;
0071     void __iomem *mc_vbase;
0072     int irq;
0073 };
0074 int fsl_mc_err_probe(struct platform_device *op);
0075 int fsl_mc_err_remove(struct platform_device *op);
0076 #endif