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0001 /*
0002  * edac_mc kernel module
0003  * (C) 2005, 2006 Linux Networx (http://lnxi.com)
0004  * This file may be distributed under the terms of the
0005  * GNU General Public License.
0006  *
0007  * Written by Thayne Harbaugh
0008  * Based on work by Dan Hollis <goemon at anime dot net> and others.
0009  *  http://www.anime.net/~goemon/linux-ecc/
0010  *
0011  * Modified by Dave Peterson and Doug Thompson
0012  *
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/proc_fs.h>
0017 #include <linux/kernel.h>
0018 #include <linux/types.h>
0019 #include <linux/smp.h>
0020 #include <linux/init.h>
0021 #include <linux/sysctl.h>
0022 #include <linux/highmem.h>
0023 #include <linux/timer.h>
0024 #include <linux/slab.h>
0025 #include <linux/jiffies.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/list.h>
0028 #include <linux/ctype.h>
0029 #include <linux/edac.h>
0030 #include <linux/bitops.h>
0031 #include <linux/uaccess.h>
0032 #include <asm/page.h>
0033 #include "edac_mc.h"
0034 #include "edac_module.h"
0035 #include <ras/ras_event.h>
0036 
0037 #ifdef CONFIG_EDAC_ATOMIC_SCRUB
0038 #include <asm/edac.h>
0039 #else
0040 #define edac_atomic_scrub(va, size) do { } while (0)
0041 #endif
0042 
0043 int edac_op_state = EDAC_OPSTATE_INVAL;
0044 EXPORT_SYMBOL_GPL(edac_op_state);
0045 
0046 /* lock to memory controller's control array */
0047 static DEFINE_MUTEX(mem_ctls_mutex);
0048 static LIST_HEAD(mc_devices);
0049 
0050 /*
0051  * Used to lock EDAC MC to just one module, avoiding two drivers e. g.
0052  *  apei/ghes and i7core_edac to be used at the same time.
0053  */
0054 static const char *edac_mc_owner;
0055 
0056 static struct mem_ctl_info *error_desc_to_mci(struct edac_raw_error_desc *e)
0057 {
0058     return container_of(e, struct mem_ctl_info, error_desc);
0059 }
0060 
0061 unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf,
0062                      unsigned int len)
0063 {
0064     struct mem_ctl_info *mci = dimm->mci;
0065     int i, n, count = 0;
0066     char *p = buf;
0067 
0068     for (i = 0; i < mci->n_layers; i++) {
0069         n = scnprintf(p, len, "%s %d ",
0070                   edac_layer_name[mci->layers[i].type],
0071                   dimm->location[i]);
0072         p += n;
0073         len -= n;
0074         count += n;
0075     }
0076 
0077     return count;
0078 }
0079 
0080 #ifdef CONFIG_EDAC_DEBUG
0081 
0082 static void edac_mc_dump_channel(struct rank_info *chan)
0083 {
0084     edac_dbg(4, "  channel->chan_idx = %d\n", chan->chan_idx);
0085     edac_dbg(4, "    channel = %p\n", chan);
0086     edac_dbg(4, "    channel->csrow = %p\n", chan->csrow);
0087     edac_dbg(4, "    channel->dimm = %p\n", chan->dimm);
0088 }
0089 
0090 static void edac_mc_dump_dimm(struct dimm_info *dimm)
0091 {
0092     char location[80];
0093 
0094     if (!dimm->nr_pages)
0095         return;
0096 
0097     edac_dimm_info_location(dimm, location, sizeof(location));
0098 
0099     edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n",
0100          dimm->mci->csbased ? "rank" : "dimm",
0101          dimm->idx, location, dimm->csrow, dimm->cschannel);
0102     edac_dbg(4, "  dimm = %p\n", dimm);
0103     edac_dbg(4, "  dimm->label = '%s'\n", dimm->label);
0104     edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
0105     edac_dbg(4, "  dimm->grain = %d\n", dimm->grain);
0106     edac_dbg(4, "  dimm->nr_pages = 0x%x\n", dimm->nr_pages);
0107 }
0108 
0109 static void edac_mc_dump_csrow(struct csrow_info *csrow)
0110 {
0111     edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx);
0112     edac_dbg(4, "  csrow = %p\n", csrow);
0113     edac_dbg(4, "  csrow->first_page = 0x%lx\n", csrow->first_page);
0114     edac_dbg(4, "  csrow->last_page = 0x%lx\n", csrow->last_page);
0115     edac_dbg(4, "  csrow->page_mask = 0x%lx\n", csrow->page_mask);
0116     edac_dbg(4, "  csrow->nr_channels = %d\n", csrow->nr_channels);
0117     edac_dbg(4, "  csrow->channels = %p\n", csrow->channels);
0118     edac_dbg(4, "  csrow->mci = %p\n", csrow->mci);
0119 }
0120 
0121 static void edac_mc_dump_mci(struct mem_ctl_info *mci)
0122 {
0123     edac_dbg(3, "\tmci = %p\n", mci);
0124     edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
0125     edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
0126     edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
0127     edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
0128     edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
0129          mci->nr_csrows, mci->csrows);
0130     edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
0131          mci->tot_dimms, mci->dimms);
0132     edac_dbg(3, "\tdev = %p\n", mci->pdev);
0133     edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
0134          mci->mod_name, mci->ctl_name);
0135     edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
0136 }
0137 
0138 #endif              /* CONFIG_EDAC_DEBUG */
0139 
0140 const char * const edac_mem_types[] = {
0141     [MEM_EMPTY] = "Empty",
0142     [MEM_RESERVED]  = "Reserved",
0143     [MEM_UNKNOWN]   = "Unknown",
0144     [MEM_FPM]   = "FPM",
0145     [MEM_EDO]   = "EDO",
0146     [MEM_BEDO]  = "BEDO",
0147     [MEM_SDR]   = "Unbuffered-SDR",
0148     [MEM_RDR]   = "Registered-SDR",
0149     [MEM_DDR]   = "Unbuffered-DDR",
0150     [MEM_RDDR]  = "Registered-DDR",
0151     [MEM_RMBS]  = "RMBS",
0152     [MEM_DDR2]  = "Unbuffered-DDR2",
0153     [MEM_FB_DDR2]   = "FullyBuffered-DDR2",
0154     [MEM_RDDR2] = "Registered-DDR2",
0155     [MEM_XDR]   = "XDR",
0156     [MEM_DDR3]  = "Unbuffered-DDR3",
0157     [MEM_RDDR3] = "Registered-DDR3",
0158     [MEM_LRDDR3]    = "Load-Reduced-DDR3-RAM",
0159     [MEM_LPDDR3]    = "Low-Power-DDR3-RAM",
0160     [MEM_DDR4]  = "Unbuffered-DDR4",
0161     [MEM_RDDR4] = "Registered-DDR4",
0162     [MEM_LPDDR4]    = "Low-Power-DDR4-RAM",
0163     [MEM_LRDDR4]    = "Load-Reduced-DDR4-RAM",
0164     [MEM_DDR5]  = "Unbuffered-DDR5",
0165     [MEM_RDDR5] = "Registered-DDR5",
0166     [MEM_LRDDR5]    = "Load-Reduced-DDR5-RAM",
0167     [MEM_NVDIMM]    = "Non-volatile-RAM",
0168     [MEM_WIO2]  = "Wide-IO-2",
0169     [MEM_HBM2]  = "High-bandwidth-memory-Gen2",
0170 };
0171 EXPORT_SYMBOL_GPL(edac_mem_types);
0172 
0173 static void _edac_mc_free(struct mem_ctl_info *mci)
0174 {
0175     put_device(&mci->dev);
0176 }
0177 
0178 static void mci_release(struct device *dev)
0179 {
0180     struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
0181     struct csrow_info *csr;
0182     int i, chn, row;
0183 
0184     if (mci->dimms) {
0185         for (i = 0; i < mci->tot_dimms; i++)
0186             kfree(mci->dimms[i]);
0187         kfree(mci->dimms);
0188     }
0189 
0190     if (mci->csrows) {
0191         for (row = 0; row < mci->nr_csrows; row++) {
0192             csr = mci->csrows[row];
0193             if (!csr)
0194                 continue;
0195 
0196             if (csr->channels) {
0197                 for (chn = 0; chn < mci->num_cschannel; chn++)
0198                     kfree(csr->channels[chn]);
0199                 kfree(csr->channels);
0200             }
0201             kfree(csr);
0202         }
0203         kfree(mci->csrows);
0204     }
0205     kfree(mci->pvt_info);
0206     kfree(mci->layers);
0207     kfree(mci);
0208 }
0209 
0210 static int edac_mc_alloc_csrows(struct mem_ctl_info *mci)
0211 {
0212     unsigned int tot_channels = mci->num_cschannel;
0213     unsigned int tot_csrows = mci->nr_csrows;
0214     unsigned int row, chn;
0215 
0216     /*
0217      * Alocate and fill the csrow/channels structs
0218      */
0219     mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL);
0220     if (!mci->csrows)
0221         return -ENOMEM;
0222 
0223     for (row = 0; row < tot_csrows; row++) {
0224         struct csrow_info *csr;
0225 
0226         csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
0227         if (!csr)
0228             return -ENOMEM;
0229 
0230         mci->csrows[row] = csr;
0231         csr->csrow_idx = row;
0232         csr->mci = mci;
0233         csr->nr_channels = tot_channels;
0234         csr->channels = kcalloc(tot_channels, sizeof(*csr->channels),
0235                     GFP_KERNEL);
0236         if (!csr->channels)
0237             return -ENOMEM;
0238 
0239         for (chn = 0; chn < tot_channels; chn++) {
0240             struct rank_info *chan;
0241 
0242             chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL);
0243             if (!chan)
0244                 return -ENOMEM;
0245 
0246             csr->channels[chn] = chan;
0247             chan->chan_idx = chn;
0248             chan->csrow = csr;
0249         }
0250     }
0251 
0252     return 0;
0253 }
0254 
0255 static int edac_mc_alloc_dimms(struct mem_ctl_info *mci)
0256 {
0257     unsigned int pos[EDAC_MAX_LAYERS];
0258     unsigned int row, chn, idx;
0259     int layer;
0260     void *p;
0261 
0262     /*
0263      * Allocate and fill the dimm structs
0264      */
0265     mci->dimms  = kcalloc(mci->tot_dimms, sizeof(*mci->dimms), GFP_KERNEL);
0266     if (!mci->dimms)
0267         return -ENOMEM;
0268 
0269     memset(&pos, 0, sizeof(pos));
0270     row = 0;
0271     chn = 0;
0272     for (idx = 0; idx < mci->tot_dimms; idx++) {
0273         struct dimm_info *dimm;
0274         struct rank_info *chan;
0275         int n, len;
0276 
0277         chan = mci->csrows[row]->channels[chn];
0278 
0279         dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL);
0280         if (!dimm)
0281             return -ENOMEM;
0282         mci->dimms[idx] = dimm;
0283         dimm->mci = mci;
0284         dimm->idx = idx;
0285 
0286         /*
0287          * Copy DIMM location and initialize it.
0288          */
0289         len = sizeof(dimm->label);
0290         p = dimm->label;
0291         n = scnprintf(p, len, "mc#%u", mci->mc_idx);
0292         p += n;
0293         len -= n;
0294         for (layer = 0; layer < mci->n_layers; layer++) {
0295             n = scnprintf(p, len, "%s#%u",
0296                       edac_layer_name[mci->layers[layer].type],
0297                       pos[layer]);
0298             p += n;
0299             len -= n;
0300             dimm->location[layer] = pos[layer];
0301         }
0302 
0303         /* Link it to the csrows old API data */
0304         chan->dimm = dimm;
0305         dimm->csrow = row;
0306         dimm->cschannel = chn;
0307 
0308         /* Increment csrow location */
0309         if (mci->layers[0].is_virt_csrow) {
0310             chn++;
0311             if (chn == mci->num_cschannel) {
0312                 chn = 0;
0313                 row++;
0314             }
0315         } else {
0316             row++;
0317             if (row == mci->nr_csrows) {
0318                 row = 0;
0319                 chn++;
0320             }
0321         }
0322 
0323         /* Increment dimm location */
0324         for (layer = mci->n_layers - 1; layer >= 0; layer--) {
0325             pos[layer]++;
0326             if (pos[layer] < mci->layers[layer].size)
0327                 break;
0328             pos[layer] = 0;
0329         }
0330     }
0331 
0332     return 0;
0333 }
0334 
0335 struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num,
0336                    unsigned int n_layers,
0337                    struct edac_mc_layer *layers,
0338                    unsigned int sz_pvt)
0339 {
0340     struct mem_ctl_info *mci;
0341     struct edac_mc_layer *layer;
0342     unsigned int idx, tot_dimms = 1;
0343     unsigned int tot_csrows = 1, tot_channels = 1;
0344     bool per_rank = false;
0345 
0346     if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0))
0347         return NULL;
0348 
0349     /*
0350      * Calculate the total amount of dimms and csrows/cschannels while
0351      * in the old API emulation mode
0352      */
0353     for (idx = 0; idx < n_layers; idx++) {
0354         tot_dimms *= layers[idx].size;
0355 
0356         if (layers[idx].is_virt_csrow)
0357             tot_csrows *= layers[idx].size;
0358         else
0359             tot_channels *= layers[idx].size;
0360 
0361         if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT)
0362             per_rank = true;
0363     }
0364 
0365     mci = kzalloc(sizeof(struct mem_ctl_info), GFP_KERNEL);
0366     if (!mci)
0367         return NULL;
0368 
0369     mci->layers = kcalloc(n_layers, sizeof(struct edac_mc_layer), GFP_KERNEL);
0370     if (!mci->layers)
0371         goto error;
0372 
0373     mci->pvt_info = kzalloc(sz_pvt, GFP_KERNEL);
0374     if (!mci->pvt_info)
0375         goto error;
0376 
0377     mci->dev.release = mci_release;
0378     device_initialize(&mci->dev);
0379 
0380     /* setup index and various internal pointers */
0381     mci->mc_idx = mc_num;
0382     mci->tot_dimms = tot_dimms;
0383     mci->n_layers = n_layers;
0384     memcpy(mci->layers, layers, sizeof(*layer) * n_layers);
0385     mci->nr_csrows = tot_csrows;
0386     mci->num_cschannel = tot_channels;
0387     mci->csbased = per_rank;
0388 
0389     if (edac_mc_alloc_csrows(mci))
0390         goto error;
0391 
0392     if (edac_mc_alloc_dimms(mci))
0393         goto error;
0394 
0395     mci->op_state = OP_ALLOC;
0396 
0397     return mci;
0398 
0399 error:
0400     _edac_mc_free(mci);
0401 
0402     return NULL;
0403 }
0404 EXPORT_SYMBOL_GPL(edac_mc_alloc);
0405 
0406 void edac_mc_free(struct mem_ctl_info *mci)
0407 {
0408     edac_dbg(1, "\n");
0409 
0410     _edac_mc_free(mci);
0411 }
0412 EXPORT_SYMBOL_GPL(edac_mc_free);
0413 
0414 bool edac_has_mcs(void)
0415 {
0416     bool ret;
0417 
0418     mutex_lock(&mem_ctls_mutex);
0419 
0420     ret = list_empty(&mc_devices);
0421 
0422     mutex_unlock(&mem_ctls_mutex);
0423 
0424     return !ret;
0425 }
0426 EXPORT_SYMBOL_GPL(edac_has_mcs);
0427 
0428 /* Caller must hold mem_ctls_mutex */
0429 static struct mem_ctl_info *__find_mci_by_dev(struct device *dev)
0430 {
0431     struct mem_ctl_info *mci;
0432     struct list_head *item;
0433 
0434     edac_dbg(3, "\n");
0435 
0436     list_for_each(item, &mc_devices) {
0437         mci = list_entry(item, struct mem_ctl_info, link);
0438 
0439         if (mci->pdev == dev)
0440             return mci;
0441     }
0442 
0443     return NULL;
0444 }
0445 
0446 /**
0447  * find_mci_by_dev
0448  *
0449  *  scan list of controllers looking for the one that manages
0450  *  the 'dev' device
0451  * @dev: pointer to a struct device related with the MCI
0452  */
0453 struct mem_ctl_info *find_mci_by_dev(struct device *dev)
0454 {
0455     struct mem_ctl_info *ret;
0456 
0457     mutex_lock(&mem_ctls_mutex);
0458     ret = __find_mci_by_dev(dev);
0459     mutex_unlock(&mem_ctls_mutex);
0460 
0461     return ret;
0462 }
0463 EXPORT_SYMBOL_GPL(find_mci_by_dev);
0464 
0465 /*
0466  * edac_mc_workq_function
0467  *  performs the operation scheduled by a workq request
0468  */
0469 static void edac_mc_workq_function(struct work_struct *work_req)
0470 {
0471     struct delayed_work *d_work = to_delayed_work(work_req);
0472     struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work);
0473 
0474     mutex_lock(&mem_ctls_mutex);
0475 
0476     if (mci->op_state != OP_RUNNING_POLL) {
0477         mutex_unlock(&mem_ctls_mutex);
0478         return;
0479     }
0480 
0481     if (edac_op_state == EDAC_OPSTATE_POLL)
0482         mci->edac_check(mci);
0483 
0484     mutex_unlock(&mem_ctls_mutex);
0485 
0486     /* Queue ourselves again. */
0487     edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
0488 }
0489 
0490 /*
0491  * edac_mc_reset_delay_period(unsigned long value)
0492  *
0493  *  user space has updated our poll period value, need to
0494  *  reset our workq delays
0495  */
0496 void edac_mc_reset_delay_period(unsigned long value)
0497 {
0498     struct mem_ctl_info *mci;
0499     struct list_head *item;
0500 
0501     mutex_lock(&mem_ctls_mutex);
0502 
0503     list_for_each(item, &mc_devices) {
0504         mci = list_entry(item, struct mem_ctl_info, link);
0505 
0506         if (mci->op_state == OP_RUNNING_POLL)
0507             edac_mod_work(&mci->work, value);
0508     }
0509     mutex_unlock(&mem_ctls_mutex);
0510 }
0511 
0512 
0513 
0514 /* Return 0 on success, 1 on failure.
0515  * Before calling this function, caller must
0516  * assign a unique value to mci->mc_idx.
0517  *
0518  *  locking model:
0519  *
0520  *      called with the mem_ctls_mutex lock held
0521  */
0522 static int add_mc_to_global_list(struct mem_ctl_info *mci)
0523 {
0524     struct list_head *item, *insert_before;
0525     struct mem_ctl_info *p;
0526 
0527     insert_before = &mc_devices;
0528 
0529     p = __find_mci_by_dev(mci->pdev);
0530     if (unlikely(p != NULL))
0531         goto fail0;
0532 
0533     list_for_each(item, &mc_devices) {
0534         p = list_entry(item, struct mem_ctl_info, link);
0535 
0536         if (p->mc_idx >= mci->mc_idx) {
0537             if (unlikely(p->mc_idx == mci->mc_idx))
0538                 goto fail1;
0539 
0540             insert_before = item;
0541             break;
0542         }
0543     }
0544 
0545     list_add_tail_rcu(&mci->link, insert_before);
0546     return 0;
0547 
0548 fail0:
0549     edac_printk(KERN_WARNING, EDAC_MC,
0550         "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev),
0551         edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx);
0552     return 1;
0553 
0554 fail1:
0555     edac_printk(KERN_WARNING, EDAC_MC,
0556         "bug in low-level driver: attempt to assign\n"
0557         "    duplicate mc_idx %d in %s()\n", p->mc_idx, __func__);
0558     return 1;
0559 }
0560 
0561 static int del_mc_from_global_list(struct mem_ctl_info *mci)
0562 {
0563     list_del_rcu(&mci->link);
0564 
0565     /* these are for safe removal of devices from global list while
0566      * NMI handlers may be traversing list
0567      */
0568     synchronize_rcu();
0569     INIT_LIST_HEAD(&mci->link);
0570 
0571     return list_empty(&mc_devices);
0572 }
0573 
0574 struct mem_ctl_info *edac_mc_find(int idx)
0575 {
0576     struct mem_ctl_info *mci;
0577     struct list_head *item;
0578 
0579     mutex_lock(&mem_ctls_mutex);
0580 
0581     list_for_each(item, &mc_devices) {
0582         mci = list_entry(item, struct mem_ctl_info, link);
0583         if (mci->mc_idx == idx)
0584             goto unlock;
0585     }
0586 
0587     mci = NULL;
0588 unlock:
0589     mutex_unlock(&mem_ctls_mutex);
0590     return mci;
0591 }
0592 EXPORT_SYMBOL(edac_mc_find);
0593 
0594 const char *edac_get_owner(void)
0595 {
0596     return edac_mc_owner;
0597 }
0598 EXPORT_SYMBOL_GPL(edac_get_owner);
0599 
0600 /* FIXME - should a warning be printed if no error detection? correction? */
0601 int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
0602                    const struct attribute_group **groups)
0603 {
0604     int ret = -EINVAL;
0605     edac_dbg(0, "\n");
0606 
0607 #ifdef CONFIG_EDAC_DEBUG
0608     if (edac_debug_level >= 3)
0609         edac_mc_dump_mci(mci);
0610 
0611     if (edac_debug_level >= 4) {
0612         struct dimm_info *dimm;
0613         int i;
0614 
0615         for (i = 0; i < mci->nr_csrows; i++) {
0616             struct csrow_info *csrow = mci->csrows[i];
0617             u32 nr_pages = 0;
0618             int j;
0619 
0620             for (j = 0; j < csrow->nr_channels; j++)
0621                 nr_pages += csrow->channels[j]->dimm->nr_pages;
0622             if (!nr_pages)
0623                 continue;
0624             edac_mc_dump_csrow(csrow);
0625             for (j = 0; j < csrow->nr_channels; j++)
0626                 if (csrow->channels[j]->dimm->nr_pages)
0627                     edac_mc_dump_channel(csrow->channels[j]);
0628         }
0629 
0630         mci_for_each_dimm(mci, dimm)
0631             edac_mc_dump_dimm(dimm);
0632     }
0633 #endif
0634     mutex_lock(&mem_ctls_mutex);
0635 
0636     if (edac_mc_owner && edac_mc_owner != mci->mod_name) {
0637         ret = -EPERM;
0638         goto fail0;
0639     }
0640 
0641     if (add_mc_to_global_list(mci))
0642         goto fail0;
0643 
0644     /* set load time so that error rate can be tracked */
0645     mci->start_time = jiffies;
0646 
0647     mci->bus = edac_get_sysfs_subsys();
0648 
0649     if (edac_create_sysfs_mci_device(mci, groups)) {
0650         edac_mc_printk(mci, KERN_WARNING,
0651             "failed to create sysfs device\n");
0652         goto fail1;
0653     }
0654 
0655     if (mci->edac_check) {
0656         mci->op_state = OP_RUNNING_POLL;
0657 
0658         INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function);
0659         edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec()));
0660 
0661     } else {
0662         mci->op_state = OP_RUNNING_INTERRUPT;
0663     }
0664 
0665     /* Report action taken */
0666     edac_mc_printk(mci, KERN_INFO,
0667         "Giving out device to module %s controller %s: DEV %s (%s)\n",
0668         mci->mod_name, mci->ctl_name, mci->dev_name,
0669         edac_op_state_to_string(mci->op_state));
0670 
0671     edac_mc_owner = mci->mod_name;
0672 
0673     mutex_unlock(&mem_ctls_mutex);
0674     return 0;
0675 
0676 fail1:
0677     del_mc_from_global_list(mci);
0678 
0679 fail0:
0680     mutex_unlock(&mem_ctls_mutex);
0681     return ret;
0682 }
0683 EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups);
0684 
0685 struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
0686 {
0687     struct mem_ctl_info *mci;
0688 
0689     edac_dbg(0, "\n");
0690 
0691     mutex_lock(&mem_ctls_mutex);
0692 
0693     /* find the requested mci struct in the global list */
0694     mci = __find_mci_by_dev(dev);
0695     if (mci == NULL) {
0696         mutex_unlock(&mem_ctls_mutex);
0697         return NULL;
0698     }
0699 
0700     /* mark MCI offline: */
0701     mci->op_state = OP_OFFLINE;
0702 
0703     if (del_mc_from_global_list(mci))
0704         edac_mc_owner = NULL;
0705 
0706     mutex_unlock(&mem_ctls_mutex);
0707 
0708     if (mci->edac_check)
0709         edac_stop_work(&mci->work);
0710 
0711     /* remove from sysfs */
0712     edac_remove_sysfs_mci_device(mci);
0713 
0714     edac_printk(KERN_INFO, EDAC_MC,
0715         "Removed device %d for %s %s: DEV %s\n", mci->mc_idx,
0716         mci->mod_name, mci->ctl_name, edac_dev_name(mci));
0717 
0718     return mci;
0719 }
0720 EXPORT_SYMBOL_GPL(edac_mc_del_mc);
0721 
0722 static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
0723                 u32 size)
0724 {
0725     struct page *pg;
0726     void *virt_addr;
0727     unsigned long flags = 0;
0728 
0729     edac_dbg(3, "\n");
0730 
0731     /* ECC error page was not in our memory. Ignore it. */
0732     if (!pfn_valid(page))
0733         return;
0734 
0735     /* Find the actual page structure then map it and fix */
0736     pg = pfn_to_page(page);
0737 
0738     if (PageHighMem(pg))
0739         local_irq_save(flags);
0740 
0741     virt_addr = kmap_atomic(pg);
0742 
0743     /* Perform architecture specific atomic scrub operation */
0744     edac_atomic_scrub(virt_addr + offset, size);
0745 
0746     /* Unmap and complete */
0747     kunmap_atomic(virt_addr);
0748 
0749     if (PageHighMem(pg))
0750         local_irq_restore(flags);
0751 }
0752 
0753 /* FIXME - should return -1 */
0754 int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
0755 {
0756     struct csrow_info **csrows = mci->csrows;
0757     int row, i, j, n;
0758 
0759     edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
0760     row = -1;
0761 
0762     for (i = 0; i < mci->nr_csrows; i++) {
0763         struct csrow_info *csrow = csrows[i];
0764         n = 0;
0765         for (j = 0; j < csrow->nr_channels; j++) {
0766             struct dimm_info *dimm = csrow->channels[j]->dimm;
0767             n += dimm->nr_pages;
0768         }
0769         if (n == 0)
0770             continue;
0771 
0772         edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
0773              mci->mc_idx,
0774              csrow->first_page, page, csrow->last_page,
0775              csrow->page_mask);
0776 
0777         if ((page >= csrow->first_page) &&
0778             (page <= csrow->last_page) &&
0779             ((page & csrow->page_mask) ==
0780              (csrow->first_page & csrow->page_mask))) {
0781             row = i;
0782             break;
0783         }
0784     }
0785 
0786     if (row == -1)
0787         edac_mc_printk(mci, KERN_ERR,
0788             "could not look up page error address %lx\n",
0789             (unsigned long)page);
0790 
0791     return row;
0792 }
0793 EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page);
0794 
0795 const char *edac_layer_name[] = {
0796     [EDAC_MC_LAYER_BRANCH] = "branch",
0797     [EDAC_MC_LAYER_CHANNEL] = "channel",
0798     [EDAC_MC_LAYER_SLOT] = "slot",
0799     [EDAC_MC_LAYER_CHIP_SELECT] = "csrow",
0800     [EDAC_MC_LAYER_ALL_MEM] = "memory",
0801 };
0802 EXPORT_SYMBOL_GPL(edac_layer_name);
0803 
0804 static void edac_inc_ce_error(struct edac_raw_error_desc *e)
0805 {
0806     int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
0807     struct mem_ctl_info *mci = error_desc_to_mci(e);
0808     struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
0809 
0810     mci->ce_mc += e->error_count;
0811 
0812     if (dimm)
0813         dimm->ce_count += e->error_count;
0814     else
0815         mci->ce_noinfo_count += e->error_count;
0816 }
0817 
0818 static void edac_inc_ue_error(struct edac_raw_error_desc *e)
0819 {
0820     int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer };
0821     struct mem_ctl_info *mci = error_desc_to_mci(e);
0822     struct dimm_info *dimm = edac_get_dimm(mci, pos[0], pos[1], pos[2]);
0823 
0824     mci->ue_mc += e->error_count;
0825 
0826     if (dimm)
0827         dimm->ue_count += e->error_count;
0828     else
0829         mci->ue_noinfo_count += e->error_count;
0830 }
0831 
0832 static void edac_ce_error(struct edac_raw_error_desc *e)
0833 {
0834     struct mem_ctl_info *mci = error_desc_to_mci(e);
0835     unsigned long remapped_page;
0836 
0837     if (edac_mc_get_log_ce()) {
0838         edac_mc_printk(mci, KERN_WARNING,
0839             "%d CE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx%s%s)\n",
0840             e->error_count, e->msg,
0841             *e->msg ? " " : "",
0842             e->label, e->location, e->page_frame_number, e->offset_in_page,
0843             e->grain, e->syndrome,
0844             *e->other_detail ? " - " : "",
0845             e->other_detail);
0846     }
0847 
0848     edac_inc_ce_error(e);
0849 
0850     if (mci->scrub_mode == SCRUB_SW_SRC) {
0851         /*
0852             * Some memory controllers (called MCs below) can remap
0853             * memory so that it is still available at a different
0854             * address when PCI devices map into memory.
0855             * MC's that can't do this, lose the memory where PCI
0856             * devices are mapped. This mapping is MC-dependent
0857             * and so we call back into the MC driver for it to
0858             * map the MC page to a physical (CPU) page which can
0859             * then be mapped to a virtual page - which can then
0860             * be scrubbed.
0861             */
0862         remapped_page = mci->ctl_page_to_phys ?
0863             mci->ctl_page_to_phys(mci, e->page_frame_number) :
0864             e->page_frame_number;
0865 
0866         edac_mc_scrub_block(remapped_page, e->offset_in_page, e->grain);
0867     }
0868 }
0869 
0870 static void edac_ue_error(struct edac_raw_error_desc *e)
0871 {
0872     struct mem_ctl_info *mci = error_desc_to_mci(e);
0873 
0874     if (edac_mc_get_log_ue()) {
0875         edac_mc_printk(mci, KERN_WARNING,
0876             "%d UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
0877             e->error_count, e->msg,
0878             *e->msg ? " " : "",
0879             e->label, e->location, e->page_frame_number, e->offset_in_page,
0880             e->grain,
0881             *e->other_detail ? " - " : "",
0882             e->other_detail);
0883     }
0884 
0885     edac_inc_ue_error(e);
0886 
0887     if (edac_mc_get_panic_on_ue()) {
0888         panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
0889             e->msg,
0890             *e->msg ? " " : "",
0891             e->label, e->location, e->page_frame_number, e->offset_in_page,
0892             e->grain,
0893             *e->other_detail ? " - " : "",
0894             e->other_detail);
0895     }
0896 }
0897 
0898 static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan)
0899 {
0900     struct mem_ctl_info *mci = error_desc_to_mci(e);
0901     enum hw_event_mc_err_type type = e->type;
0902     u16 count = e->error_count;
0903 
0904     if (row < 0)
0905         return;
0906 
0907     edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
0908 
0909     if (type == HW_EVENT_ERR_CORRECTED) {
0910         mci->csrows[row]->ce_count += count;
0911         if (chan >= 0)
0912             mci->csrows[row]->channels[chan]->ce_count += count;
0913     } else {
0914         mci->csrows[row]->ue_count += count;
0915     }
0916 }
0917 
0918 void edac_raw_mc_handle_error(struct edac_raw_error_desc *e)
0919 {
0920     struct mem_ctl_info *mci = error_desc_to_mci(e);
0921     u8 grain_bits;
0922 
0923     /* Sanity-check driver-supplied grain value. */
0924     if (WARN_ON_ONCE(!e->grain))
0925         e->grain = 1;
0926 
0927     grain_bits = fls_long(e->grain - 1);
0928 
0929     /* Report the error via the trace interface */
0930     if (IS_ENABLED(CONFIG_RAS))
0931         trace_mc_event(e->type, e->msg, e->label, e->error_count,
0932                    mci->mc_idx, e->top_layer, e->mid_layer,
0933                    e->low_layer,
0934                    (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
0935                    grain_bits, e->syndrome, e->other_detail);
0936 
0937     if (e->type == HW_EVENT_ERR_CORRECTED)
0938         edac_ce_error(e);
0939     else
0940         edac_ue_error(e);
0941 }
0942 EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error);
0943 
0944 void edac_mc_handle_error(const enum hw_event_mc_err_type type,
0945               struct mem_ctl_info *mci,
0946               const u16 error_count,
0947               const unsigned long page_frame_number,
0948               const unsigned long offset_in_page,
0949               const unsigned long syndrome,
0950               const int top_layer,
0951               const int mid_layer,
0952               const int low_layer,
0953               const char *msg,
0954               const char *other_detail)
0955 {
0956     struct dimm_info *dimm;
0957     char *p, *end;
0958     int row = -1, chan = -1;
0959     int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer };
0960     int i, n_labels = 0;
0961     struct edac_raw_error_desc *e = &mci->error_desc;
0962     bool any_memory = true;
0963     const char *prefix;
0964 
0965     edac_dbg(3, "MC%d\n", mci->mc_idx);
0966 
0967     /* Fills the error report buffer */
0968     memset(e, 0, sizeof (*e));
0969     e->error_count = error_count;
0970     e->type = type;
0971     e->top_layer = top_layer;
0972     e->mid_layer = mid_layer;
0973     e->low_layer = low_layer;
0974     e->page_frame_number = page_frame_number;
0975     e->offset_in_page = offset_in_page;
0976     e->syndrome = syndrome;
0977     /* need valid strings here for both: */
0978     e->msg = msg ?: "";
0979     e->other_detail = other_detail ?: "";
0980 
0981     /*
0982      * Check if the event report is consistent and if the memory location is
0983      * known. If it is, the DIMM(s) label info will be filled and the DIMM's
0984      * error counters will be incremented.
0985      */
0986     for (i = 0; i < mci->n_layers; i++) {
0987         if (pos[i] >= (int)mci->layers[i].size) {
0988 
0989             edac_mc_printk(mci, KERN_ERR,
0990                        "INTERNAL ERROR: %s value is out of range (%d >= %d)\n",
0991                        edac_layer_name[mci->layers[i].type],
0992                        pos[i], mci->layers[i].size);
0993             /*
0994              * Instead of just returning it, let's use what's
0995              * known about the error. The increment routines and
0996              * the DIMM filter logic will do the right thing by
0997              * pointing the likely damaged DIMMs.
0998              */
0999             pos[i] = -1;
1000         }
1001         if (pos[i] >= 0)
1002             any_memory = false;
1003     }
1004 
1005     /*
1006      * Get the dimm label/grain that applies to the match criteria.
1007      * As the error algorithm may not be able to point to just one memory
1008      * stick, the logic here will get all possible labels that could
1009      * pottentially be affected by the error.
1010      * On FB-DIMM memory controllers, for uncorrected errors, it is common
1011      * to have only the MC channel and the MC dimm (also called "branch")
1012      * but the channel is not known, as the memory is arranged in pairs,
1013      * where each memory belongs to a separate channel within the same
1014      * branch.
1015      */
1016     p = e->label;
1017     *p = '\0';
1018     end = p + sizeof(e->label);
1019     prefix = "";
1020 
1021     mci_for_each_dimm(mci, dimm) {
1022         if (top_layer >= 0 && top_layer != dimm->location[0])
1023             continue;
1024         if (mid_layer >= 0 && mid_layer != dimm->location[1])
1025             continue;
1026         if (low_layer >= 0 && low_layer != dimm->location[2])
1027             continue;
1028 
1029         /* get the max grain, over the error match range */
1030         if (dimm->grain > e->grain)
1031             e->grain = dimm->grain;
1032 
1033         /*
1034          * If the error is memory-controller wide, there's no need to
1035          * seek for the affected DIMMs because the whole channel/memory
1036          * controller/... may be affected. Also, don't show errors for
1037          * empty DIMM slots.
1038          */
1039         if (!dimm->nr_pages)
1040             continue;
1041 
1042         n_labels++;
1043         if (n_labels > EDAC_MAX_LABELS) {
1044             p = e->label;
1045             *p = '\0';
1046         } else {
1047             p += scnprintf(p, end - p, "%s%s", prefix, dimm->label);
1048             prefix = OTHER_LABEL;
1049         }
1050 
1051         /*
1052          * get csrow/channel of the DIMM, in order to allow
1053          * incrementing the compat API counters
1054          */
1055         edac_dbg(4, "%s csrows map: (%d,%d)\n",
1056             mci->csbased ? "rank" : "dimm",
1057             dimm->csrow, dimm->cschannel);
1058         if (row == -1)
1059             row = dimm->csrow;
1060         else if (row >= 0 && row != dimm->csrow)
1061             row = -2;
1062 
1063         if (chan == -1)
1064             chan = dimm->cschannel;
1065         else if (chan >= 0 && chan != dimm->cschannel)
1066             chan = -2;
1067     }
1068 
1069     if (any_memory)
1070         strscpy(e->label, "any memory", sizeof(e->label));
1071     else if (!*e->label)
1072         strscpy(e->label, "unknown memory", sizeof(e->label));
1073 
1074     edac_inc_csrow(e, row, chan);
1075 
1076     /* Fill the RAM location data */
1077     p = e->location;
1078     end = p + sizeof(e->location);
1079     prefix = "";
1080 
1081     for (i = 0; i < mci->n_layers; i++) {
1082         if (pos[i] < 0)
1083             continue;
1084 
1085         p += scnprintf(p, end - p, "%s%s:%d", prefix,
1086                    edac_layer_name[mci->layers[i].type], pos[i]);
1087         prefix = " ";
1088     }
1089 
1090     edac_raw_mc_handle_error(e);
1091 }
1092 EXPORT_SYMBOL_GPL(edac_mc_handle_error);
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