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0001 /*
0002  * Intel e7xxx Memory Controller kernel module
0003  * (C) 2003 Linux Networx (http://lnxi.com)
0004  * This file may be distributed under the terms of the
0005  * GNU General Public License.
0006  *
0007  * See "enum e7xxx_chips" below for supported chipsets
0008  *
0009  * Written by Thayne Harbaugh
0010  * Based on work by Dan Hollis <goemon at anime dot net> and others.
0011  *  http://www.anime.net/~goemon/linux-ecc/
0012  *
0013  * Datasheet:
0014  *  http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
0015  *
0016  * Contributors:
0017  *  Eric Biederman (Linux Networx)
0018  *  Tom Zimmerman (Linux Networx)
0019  *  Jim Garlick (Lawrence Livermore National Labs)
0020  *  Dave Peterson (Lawrence Livermore National Labs)
0021  *  That One Guy (Some other place)
0022  *  Wang Zhenyu (intel.com)
0023  *
0024  * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
0025  *
0026  */
0027 
0028 #include <linux/module.h>
0029 #include <linux/init.h>
0030 #include <linux/pci.h>
0031 #include <linux/pci_ids.h>
0032 #include <linux/edac.h>
0033 #include "edac_module.h"
0034 
0035 #define EDAC_MOD_STR    "e7xxx_edac"
0036 
0037 #define e7xxx_printk(level, fmt, arg...) \
0038     edac_printk(level, "e7xxx", fmt, ##arg)
0039 
0040 #define e7xxx_mc_printk(mci, level, fmt, arg...) \
0041     edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
0042 
0043 #ifndef PCI_DEVICE_ID_INTEL_7205_0
0044 #define PCI_DEVICE_ID_INTEL_7205_0  0x255d
0045 #endif              /* PCI_DEVICE_ID_INTEL_7205_0 */
0046 
0047 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
0048 #define PCI_DEVICE_ID_INTEL_7205_1_ERR  0x2551
0049 #endif              /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
0050 
0051 #ifndef PCI_DEVICE_ID_INTEL_7500_0
0052 #define PCI_DEVICE_ID_INTEL_7500_0  0x2540
0053 #endif              /* PCI_DEVICE_ID_INTEL_7500_0 */
0054 
0055 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
0056 #define PCI_DEVICE_ID_INTEL_7500_1_ERR  0x2541
0057 #endif              /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
0058 
0059 #ifndef PCI_DEVICE_ID_INTEL_7501_0
0060 #define PCI_DEVICE_ID_INTEL_7501_0  0x254c
0061 #endif              /* PCI_DEVICE_ID_INTEL_7501_0 */
0062 
0063 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
0064 #define PCI_DEVICE_ID_INTEL_7501_1_ERR  0x2541
0065 #endif              /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
0066 
0067 #ifndef PCI_DEVICE_ID_INTEL_7505_0
0068 #define PCI_DEVICE_ID_INTEL_7505_0  0x2550
0069 #endif              /* PCI_DEVICE_ID_INTEL_7505_0 */
0070 
0071 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
0072 #define PCI_DEVICE_ID_INTEL_7505_1_ERR  0x2551
0073 #endif              /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
0074 
0075 #define E7XXX_NR_CSROWS     8   /* number of csrows */
0076 #define E7XXX_NR_DIMMS      8   /* 2 channels, 4 dimms/channel */
0077 
0078 /* E7XXX register addresses - device 0 function 0 */
0079 #define E7XXX_DRB       0x60    /* DRAM row boundary register (8b) */
0080 #define E7XXX_DRA       0x70    /* DRAM row attribute register (8b) */
0081                     /*
0082                      * 31   Device width row 7 0=x8 1=x4
0083                      * 27   Device width row 6
0084                      * 23   Device width row 5
0085                      * 19   Device width row 4
0086                      * 15   Device width row 3
0087                      * 11   Device width row 2
0088                      *  7   Device width row 1
0089                      *  3   Device width row 0
0090                      */
0091 #define E7XXX_DRC       0x7C    /* DRAM controller mode reg (32b) */
0092                     /*
0093                      * 22    Number channels 0=1,1=2
0094                      * 19:18 DRB Granularity 32/64MB
0095                      */
0096 #define E7XXX_TOLM      0xC4    /* DRAM top of low memory reg (16b) */
0097 #define E7XXX_REMAPBASE     0xC6    /* DRAM remap base address reg (16b) */
0098 #define E7XXX_REMAPLIMIT    0xC8    /* DRAM remap limit address reg (16b) */
0099 
0100 /* E7XXX register addresses - device 0 function 1 */
0101 #define E7XXX_DRAM_FERR     0x80    /* DRAM first error register (8b) */
0102 #define E7XXX_DRAM_NERR     0x82    /* DRAM next error register (8b) */
0103 #define E7XXX_DRAM_CELOG_ADD    0xA0    /* DRAM first correctable memory */
0104                     /*     error address register (32b) */
0105                     /*
0106                      * 31:28 Reserved
0107                      * 27:6  CE address (4k block 33:12)
0108                      *  5:0  Reserved
0109                      */
0110 #define E7XXX_DRAM_UELOG_ADD    0xB0    /* DRAM first uncorrectable memory */
0111                     /*     error address register (32b) */
0112                     /*
0113                      * 31:28 Reserved
0114                      * 27:6  CE address (4k block 33:12)
0115                      *  5:0  Reserved
0116                      */
0117 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0  /* DRAM first correctable memory */
0118                     /*     error syndrome register (16b) */
0119 
0120 enum e7xxx_chips {
0121     E7500 = 0,
0122     E7501,
0123     E7505,
0124     E7205,
0125 };
0126 
0127 struct e7xxx_pvt {
0128     struct pci_dev *bridge_ck;
0129     u32 tolm;
0130     u32 remapbase;
0131     u32 remaplimit;
0132     const struct e7xxx_dev_info *dev_info;
0133 };
0134 
0135 struct e7xxx_dev_info {
0136     u16 err_dev;
0137     const char *ctl_name;
0138 };
0139 
0140 struct e7xxx_error_info {
0141     u8 dram_ferr;
0142     u8 dram_nerr;
0143     u32 dram_celog_add;
0144     u16 dram_celog_syndrome;
0145     u32 dram_uelog_add;
0146 };
0147 
0148 static struct edac_pci_ctl_info *e7xxx_pci;
0149 
0150 static const struct e7xxx_dev_info e7xxx_devs[] = {
0151     [E7500] = {
0152         .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
0153         .ctl_name = "E7500"},
0154     [E7501] = {
0155         .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
0156         .ctl_name = "E7501"},
0157     [E7505] = {
0158         .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
0159         .ctl_name = "E7505"},
0160     [E7205] = {
0161         .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
0162         .ctl_name = "E7205"},
0163 };
0164 
0165 /* FIXME - is this valid for both SECDED and S4ECD4ED? */
0166 static inline int e7xxx_find_channel(u16 syndrome)
0167 {
0168     edac_dbg(3, "\n");
0169 
0170     if ((syndrome & 0xff00) == 0)
0171         return 0;
0172 
0173     if ((syndrome & 0x00ff) == 0)
0174         return 1;
0175 
0176     if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
0177         return 0;
0178 
0179     return 1;
0180 }
0181 
0182 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
0183                 unsigned long page)
0184 {
0185     u32 remap;
0186     struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
0187 
0188     edac_dbg(3, "\n");
0189 
0190     if ((page < pvt->tolm) ||
0191         ((page >= 0x100000) && (page < pvt->remapbase)))
0192         return page;
0193 
0194     remap = (page - pvt->tolm) + pvt->remapbase;
0195 
0196     if (remap < pvt->remaplimit)
0197         return remap;
0198 
0199     e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
0200     return pvt->tolm - 1;
0201 }
0202 
0203 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
0204 {
0205     u32 error_1b, page;
0206     u16 syndrome;
0207     int row;
0208     int channel;
0209 
0210     edac_dbg(3, "\n");
0211     /* read the error address */
0212     error_1b = info->dram_celog_add;
0213     /* FIXME - should use PAGE_SHIFT */
0214     page = error_1b >> 6;   /* convert the address to 4k page */
0215     /* read the syndrome */
0216     syndrome = info->dram_celog_syndrome;
0217     /* FIXME - check for -1 */
0218     row = edac_mc_find_csrow_by_page(mci, page);
0219     /* convert syndrome to channel */
0220     channel = e7xxx_find_channel(syndrome);
0221     edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
0222                  row, channel, -1, "e7xxx CE", "");
0223 }
0224 
0225 static void process_ce_no_info(struct mem_ctl_info *mci)
0226 {
0227     edac_dbg(3, "\n");
0228     edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
0229                  "e7xxx CE log register overflow", "");
0230 }
0231 
0232 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
0233 {
0234     u32 error_2b, block_page;
0235     int row;
0236 
0237     edac_dbg(3, "\n");
0238     /* read the error address */
0239     error_2b = info->dram_uelog_add;
0240     /* FIXME - should use PAGE_SHIFT */
0241     block_page = error_2b >> 6; /* convert to 4k address */
0242     row = edac_mc_find_csrow_by_page(mci, block_page);
0243 
0244     edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
0245                  row, -1, -1, "e7xxx UE", "");
0246 }
0247 
0248 static void process_ue_no_info(struct mem_ctl_info *mci)
0249 {
0250     edac_dbg(3, "\n");
0251 
0252     edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
0253                  "e7xxx UE log register overflow", "");
0254 }
0255 
0256 static void e7xxx_get_error_info(struct mem_ctl_info *mci,
0257                  struct e7xxx_error_info *info)
0258 {
0259     struct e7xxx_pvt *pvt;
0260 
0261     pvt = (struct e7xxx_pvt *)mci->pvt_info;
0262     pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
0263     pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
0264 
0265     if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
0266         pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
0267                 &info->dram_celog_add);
0268         pci_read_config_word(pvt->bridge_ck,
0269                 E7XXX_DRAM_CELOG_SYNDROME,
0270                 &info->dram_celog_syndrome);
0271     }
0272 
0273     if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
0274         pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
0275                 &info->dram_uelog_add);
0276 
0277     if (info->dram_ferr & 3)
0278         pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
0279 
0280     if (info->dram_nerr & 3)
0281         pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
0282 }
0283 
0284 static int e7xxx_process_error_info(struct mem_ctl_info *mci,
0285                 struct e7xxx_error_info *info,
0286                 int handle_errors)
0287 {
0288     int error_found;
0289 
0290     error_found = 0;
0291 
0292     /* decode and report errors */
0293     if (info->dram_ferr & 1) {  /* check first error correctable */
0294         error_found = 1;
0295 
0296         if (handle_errors)
0297             process_ce(mci, info);
0298     }
0299 
0300     if (info->dram_ferr & 2) {  /* check first error uncorrectable */
0301         error_found = 1;
0302 
0303         if (handle_errors)
0304             process_ue(mci, info);
0305     }
0306 
0307     if (info->dram_nerr & 1) {  /* check next error correctable */
0308         error_found = 1;
0309 
0310         if (handle_errors) {
0311             if (info->dram_ferr & 1)
0312                 process_ce_no_info(mci);
0313             else
0314                 process_ce(mci, info);
0315         }
0316     }
0317 
0318     if (info->dram_nerr & 2) {  /* check next error uncorrectable */
0319         error_found = 1;
0320 
0321         if (handle_errors) {
0322             if (info->dram_ferr & 2)
0323                 process_ue_no_info(mci);
0324             else
0325                 process_ue(mci, info);
0326         }
0327     }
0328 
0329     return error_found;
0330 }
0331 
0332 static void e7xxx_check(struct mem_ctl_info *mci)
0333 {
0334     struct e7xxx_error_info info;
0335 
0336     e7xxx_get_error_info(mci, &info);
0337     e7xxx_process_error_info(mci, &info, 1);
0338 }
0339 
0340 /* Return 1 if dual channel mode is active.  Else return 0. */
0341 static inline int dual_channel_active(u32 drc, int dev_idx)
0342 {
0343     return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
0344 }
0345 
0346 /* Return DRB granularity (0=32mb, 1=64mb). */
0347 static inline int drb_granularity(u32 drc, int dev_idx)
0348 {
0349     /* only e7501 can be single channel */
0350     return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
0351 }
0352 
0353 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
0354             int dev_idx, u32 drc)
0355 {
0356     unsigned long last_cumul_size;
0357     int index, j;
0358     u8 value;
0359     u32 dra, cumul_size, nr_pages;
0360     int drc_chan, drc_drbg, drc_ddim, mem_dev;
0361     struct csrow_info *csrow;
0362     struct dimm_info *dimm;
0363     enum edac_type edac_mode;
0364 
0365     pci_read_config_dword(pdev, E7XXX_DRA, &dra);
0366     drc_chan = dual_channel_active(drc, dev_idx);
0367     drc_drbg = drb_granularity(drc, dev_idx);
0368     drc_ddim = (drc >> 20) & 0x3;
0369     last_cumul_size = 0;
0370 
0371     /* The dram row boundary (DRB) reg values are boundary address
0372      * for each DRAM row with a granularity of 32 or 64MB (single/dual
0373      * channel operation).  DRB regs are cumulative; therefore DRB7 will
0374      * contain the total memory contained in all eight rows.
0375      */
0376     for (index = 0; index < mci->nr_csrows; index++) {
0377         /* mem_dev 0=x8, 1=x4 */
0378         mem_dev = (dra >> (index * 4 + 3)) & 0x1;
0379         csrow = mci->csrows[index];
0380 
0381         pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
0382         /* convert a 64 or 32 MiB DRB to a page size. */
0383         cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
0384         edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
0385         if (cumul_size == last_cumul_size)
0386             continue;   /* not populated */
0387 
0388         csrow->first_page = last_cumul_size;
0389         csrow->last_page = cumul_size - 1;
0390         nr_pages = cumul_size - last_cumul_size;
0391         last_cumul_size = cumul_size;
0392 
0393         /*
0394         * if single channel or x8 devices then SECDED
0395         * if dual channel and x4 then S4ECD4ED
0396         */
0397         if (drc_ddim) {
0398             if (drc_chan && mem_dev) {
0399                 edac_mode = EDAC_S4ECD4ED;
0400                 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
0401             } else {
0402                 edac_mode = EDAC_SECDED;
0403                 mci->edac_cap |= EDAC_FLAG_SECDED;
0404             }
0405         } else
0406             edac_mode = EDAC_NONE;
0407 
0408         for (j = 0; j < drc_chan + 1; j++) {
0409             dimm = csrow->channels[j]->dimm;
0410 
0411             dimm->nr_pages = nr_pages / (drc_chan + 1);
0412             dimm->grain = 1 << 12;  /* 4KiB - resolution of CELOG */
0413             dimm->mtype = MEM_RDDR; /* only one type supported */
0414             dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
0415             dimm->edac_mode = edac_mode;
0416         }
0417     }
0418 }
0419 
0420 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
0421 {
0422     u16 pci_data;
0423     struct mem_ctl_info *mci = NULL;
0424     struct edac_mc_layer layers[2];
0425     struct e7xxx_pvt *pvt = NULL;
0426     u32 drc;
0427     int drc_chan;
0428     struct e7xxx_error_info discard;
0429 
0430     edac_dbg(0, "mci\n");
0431 
0432     pci_read_config_dword(pdev, E7XXX_DRC, &drc);
0433 
0434     drc_chan = dual_channel_active(drc, dev_idx);
0435     /*
0436      * According with the datasheet, this device has a maximum of
0437      * 4 DIMMS per channel, either single-rank or dual-rank. So, the
0438      * total amount of dimms is 8 (E7XXX_NR_DIMMS).
0439      * That means that the DIMM is mapped as CSROWs, and the channel
0440      * will map the rank. So, an error to either channel should be
0441      * attributed to the same dimm.
0442      */
0443     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0444     layers[0].size = E7XXX_NR_CSROWS;
0445     layers[0].is_virt_csrow = true;
0446     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0447     layers[1].size = drc_chan + 1;
0448     layers[1].is_virt_csrow = false;
0449     mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
0450     if (mci == NULL)
0451         return -ENOMEM;
0452 
0453     edac_dbg(3, "init mci\n");
0454     mci->mtype_cap = MEM_FLAG_RDDR;
0455     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
0456         EDAC_FLAG_S4ECD4ED;
0457     /* FIXME - what if different memory types are in different csrows? */
0458     mci->mod_name = EDAC_MOD_STR;
0459     mci->pdev = &pdev->dev;
0460     edac_dbg(3, "init pvt\n");
0461     pvt = (struct e7xxx_pvt *)mci->pvt_info;
0462     pvt->dev_info = &e7xxx_devs[dev_idx];
0463     pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
0464                     pvt->dev_info->err_dev, pvt->bridge_ck);
0465 
0466     if (!pvt->bridge_ck) {
0467         e7xxx_printk(KERN_ERR, "error reporting device not found:"
0468             "vendor %x device 0x%x (broken BIOS?)\n",
0469             PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
0470         goto fail0;
0471     }
0472 
0473     edac_dbg(3, "more mci init\n");
0474     mci->ctl_name = pvt->dev_info->ctl_name;
0475     mci->dev_name = pci_name(pdev);
0476     mci->edac_check = e7xxx_check;
0477     mci->ctl_page_to_phys = ctl_page_to_phys;
0478     e7xxx_init_csrows(mci, pdev, dev_idx, drc);
0479     mci->edac_cap |= EDAC_FLAG_NONE;
0480     edac_dbg(3, "tolm, remapbase, remaplimit\n");
0481     /* load the top of low memory, remap base, and remap limit vars */
0482     pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
0483     pvt->tolm = ((u32) pci_data) << 4;
0484     pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
0485     pvt->remapbase = ((u32) pci_data) << 14;
0486     pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
0487     pvt->remaplimit = ((u32) pci_data) << 14;
0488     e7xxx_printk(KERN_INFO,
0489         "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
0490         pvt->remapbase, pvt->remaplimit);
0491 
0492     /* clear any pending errors, or initial state bits */
0493     e7xxx_get_error_info(mci, &discard);
0494 
0495     /* Here we assume that we will never see multiple instances of this
0496      * type of memory controller.  The ID is therefore hardcoded to 0.
0497      */
0498     if (edac_mc_add_mc(mci)) {
0499         edac_dbg(3, "failed edac_mc_add_mc()\n");
0500         goto fail1;
0501     }
0502 
0503     /* allocating generic PCI control info */
0504     e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
0505     if (!e7xxx_pci) {
0506         printk(KERN_WARNING
0507             "%s(): Unable to create PCI control\n",
0508             __func__);
0509         printk(KERN_WARNING
0510             "%s(): PCI error report via EDAC not setup\n",
0511             __func__);
0512     }
0513 
0514     /* get this far and it's successful */
0515     edac_dbg(3, "success\n");
0516     return 0;
0517 
0518 fail1:
0519     pci_dev_put(pvt->bridge_ck);
0520 
0521 fail0:
0522     edac_mc_free(mci);
0523 
0524     return -ENODEV;
0525 }
0526 
0527 /* returns count (>= 0), or negative on error */
0528 static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0529 {
0530     edac_dbg(0, "\n");
0531 
0532     /* wake up and enable device */
0533     return pci_enable_device(pdev) ?
0534         -EIO : e7xxx_probe1(pdev, ent->driver_data);
0535 }
0536 
0537 static void e7xxx_remove_one(struct pci_dev *pdev)
0538 {
0539     struct mem_ctl_info *mci;
0540     struct e7xxx_pvt *pvt;
0541 
0542     edac_dbg(0, "\n");
0543 
0544     if (e7xxx_pci)
0545         edac_pci_release_generic_ctl(e7xxx_pci);
0546 
0547     if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0548         return;
0549 
0550     pvt = (struct e7xxx_pvt *)mci->pvt_info;
0551     pci_dev_put(pvt->bridge_ck);
0552     edac_mc_free(mci);
0553 }
0554 
0555 static const struct pci_device_id e7xxx_pci_tbl[] = {
0556     {
0557      PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0558      E7205},
0559     {
0560      PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0561      E7500},
0562     {
0563      PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0564      E7501},
0565     {
0566      PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
0567      E7505},
0568     {
0569      0,
0570      }          /* 0 terminated list. */
0571 };
0572 
0573 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
0574 
0575 static struct pci_driver e7xxx_driver = {
0576     .name = EDAC_MOD_STR,
0577     .probe = e7xxx_init_one,
0578     .remove = e7xxx_remove_one,
0579     .id_table = e7xxx_pci_tbl,
0580 };
0581 
0582 static int __init e7xxx_init(void)
0583 {
0584        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
0585        opstate_init();
0586 
0587     return pci_register_driver(&e7xxx_driver);
0588 }
0589 
0590 static void __exit e7xxx_exit(void)
0591 {
0592     pci_unregister_driver(&e7xxx_driver);
0593 }
0594 
0595 module_init(e7xxx_init);
0596 module_exit(e7xxx_exit);
0597 
0598 MODULE_LICENSE("GPL");
0599 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
0600         "Based on.work by Dan Hollis et al");
0601 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
0602 module_param(edac_op_state, int, 0444);
0603 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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