drivers/edac/dmc520_edac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * EDAC driver for DMC-520 memory controller.
0005  *
0006  * The driver supports 10 interrupt lines,
0007  * though only dram_ecc_errc and dram_ecc_errd are currently handled.
0008  *
0009  * Authors: Rui Zhao <ruizhao@microsoft.com>
0010  *      Lei Wang <lewan@microsoft.com>
0011  *      Shiping Ji <shji@microsoft.com>
0012  */
0013
0014 #include <linux/bitfield.h>
0015 #include <linux/edac.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/slab.h>
0022 #include <linux/spinlock.h>
0023 #include "edac_mc.h"
0024
0025 /* DMC-520 registers */
0026 #define REG_OFFSET_FEATURE_CONFIG           0x130
0027 #define REG_OFFSET_ECC_ERRC_COUNT_31_00     0x158
0028 #define REG_OFFSET_ECC_ERRC_COUNT_63_32     0x15C
0029 #define REG_OFFSET_ECC_ERRD_COUNT_31_00     0x160
0030 #define REG_OFFSET_ECC_ERRD_COUNT_63_32     0x164
0031 #define REG_OFFSET_INTERRUPT_CONTROL            0x500
0032 #define REG_OFFSET_INTERRUPT_CLR            0x508
0033 #define REG_OFFSET_INTERRUPT_STATUS         0x510
0034 #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 0x528
0035 #define REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 0x52C
0036 #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00 0x530
0037 #define REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32 0x534
0038 #define REG_OFFSET_ADDRESS_CONTROL_NOW          0x1010
0039 #define REG_OFFSET_MEMORY_TYPE_NOW          0x1128
0040 #define REG_OFFSET_SCRUB_CONTROL0_NOW           0x1170
0041 #define REG_OFFSET_FORMAT_CONTROL           0x18
0042
0043 /* DMC-520 types, masks and bitfields */
0044 #define RAM_ECC_INT_CE_BIT          BIT(0)
0045 #define RAM_ECC_INT_UE_BIT          BIT(1)
0046 #define DRAM_ECC_INT_CE_BIT         BIT(2)
0047 #define DRAM_ECC_INT_UE_BIT         BIT(3)
0048 #define FAILED_ACCESS_INT_BIT           BIT(4)
0049 #define FAILED_PROG_INT_BIT         BIT(5)
0050 #define LINK_ERR_INT_BIT            BIT(6)
0051 #define TEMPERATURE_EVENT_INT_BIT       BIT(7)
0052 #define ARCH_FSM_INT_BIT            BIT(8)
0053 #define PHY_REQUEST_INT_BIT         BIT(9)
0054 #define MEMORY_WIDTH_MASK           GENMASK(1, 0)
0055 #define SCRUB_TRIGGER0_NEXT_MASK        GENMASK(1, 0)
0056 #define REG_FIELD_DRAM_ECC_ENABLED      GENMASK(1, 0)
0057 #define REG_FIELD_MEMORY_TYPE           GENMASK(2, 0)
0058 #define REG_FIELD_DEVICE_WIDTH          GENMASK(9, 8)
0059 #define REG_FIELD_ADDRESS_CONTROL_COL       GENMASK(2,  0)
0060 #define REG_FIELD_ADDRESS_CONTROL_ROW       GENMASK(10, 8)
0061 #define REG_FIELD_ADDRESS_CONTROL_BANK      GENMASK(18, 16)
0062 #define REG_FIELD_ADDRESS_CONTROL_RANK      GENMASK(25, 24)
0063 #define REG_FIELD_ERR_INFO_LOW_VALID        BIT(0)
0064 #define REG_FIELD_ERR_INFO_LOW_COL      GENMASK(10, 1)
0065 #define REG_FIELD_ERR_INFO_LOW_ROW      GENMASK(28, 11)
0066 #define REG_FIELD_ERR_INFO_LOW_RANK     GENMASK(31, 29)
0067 #define REG_FIELD_ERR_INFO_HIGH_BANK        GENMASK(3, 0)
0068 #define REG_FIELD_ERR_INFO_HIGH_VALID       BIT(31)
0069
0070 #define DRAM_ADDRESS_CONTROL_MIN_COL_BITS   8
0071 #define DRAM_ADDRESS_CONTROL_MIN_ROW_BITS   11
0072
0073 #define DMC520_SCRUB_TRIGGER_ERR_DETECT 2
0074 #define DMC520_SCRUB_TRIGGER_IDLE       3
0075
0076 /* Driver settings */
0077 /*
0078  * The max-length message would be: "rank:7 bank:15 row:262143 col:1023".
0079  * Max length is 34. Using a 40-size buffer is enough.
0080  */
0081 #define DMC520_MSG_BUF_SIZE         40
0082 #define EDAC_MOD_NAME               "dmc520-edac"
0083 #define EDAC_CTL_NAME               "dmc520"
0084
0085 /* the data bus width for the attached memory chips. */
0086 enum dmc520_mem_width {
0087     MEM_WIDTH_X32 = 2,
0088     MEM_WIDTH_X64 = 3
0089 };
0090
0091 /* memory type */
0092 enum dmc520_mem_type {
0093     MEM_TYPE_DDR3 = 1,
0094     MEM_TYPE_DDR4 = 2
0095 };
0096
0097 /* memory device width */
0098 enum dmc520_dev_width {
0099     DEV_WIDTH_X4 = 0,
0100     DEV_WIDTH_X8 = 1,
0101     DEV_WIDTH_X16 = 2
0102 };
0103
0104 struct ecc_error_info {
0105     u32 col;
0106     u32 row;
0107     u32 bank;
0108     u32 rank;
0109 };
0110
0111 /* The interrupt config */
0112 struct dmc520_irq_config {
0113     char *name;
0114     int mask;
0115 };
0116
0117 /* The interrupt mappings */
0118 static struct dmc520_irq_config dmc520_irq_configs[] = {
0119     {
0120         .name = "ram_ecc_errc",
0121         .mask = RAM_ECC_INT_CE_BIT
0122     },
0123     {
0124         .name = "ram_ecc_errd",
0125         .mask = RAM_ECC_INT_UE_BIT
0126     },
0127     {
0128         .name = "dram_ecc_errc",
0129         .mask = DRAM_ECC_INT_CE_BIT
0130     },
0131     {
0132         .name = "dram_ecc_errd",
0133         .mask = DRAM_ECC_INT_UE_BIT
0134     },
0135     {
0136         .name = "failed_access",
0137         .mask = FAILED_ACCESS_INT_BIT
0138     },
0139     {
0140         .name = "failed_prog",
0141         .mask = FAILED_PROG_INT_BIT
0142     },
0143     {
0144         .name = "link_err",
0145         .mask = LINK_ERR_INT_BIT
0146     },
0147     {
0148         .name = "temperature_event",
0149         .mask = TEMPERATURE_EVENT_INT_BIT
0150     },
0151     {
0152         .name = "arch_fsm",
0153         .mask = ARCH_FSM_INT_BIT
0154     },
0155     {
0156         .name = "phy_request",
0157         .mask = PHY_REQUEST_INT_BIT
0158     }
0159 };
0160
0161 #define NUMBER_OF_IRQS              ARRAY_SIZE(dmc520_irq_configs)
0162
0163 /*
0164  * The EDAC driver private data.
0165  * error_lock is to protect concurrent writes to the mci->error_desc through
0166  * edac_mc_handle_error().
0167  */
0168 struct dmc520_edac {
0169     void __iomem *reg_base;
0170     spinlock_t error_lock;
0171     u32 mem_width_in_bytes;
0172     int irqs[NUMBER_OF_IRQS];
0173     int masks[NUMBER_OF_IRQS];
0174 };
0175
0176 static int dmc520_mc_idx;
0177
0178 static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset)
0179 {
0180     return readl(pvt->reg_base + offset);
0181 }
0182
0183 static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset)
0184 {
0185     writel(val, pvt->reg_base + offset);
0186 }
0187
0188 static u32 dmc520_calc_dram_ecc_error(u32 value)
0189 {
0190     u32 total = 0;
0191
0192     /* Each rank's error counter takes one byte. */
0193     while (value > 0) {
0194         total += (value & 0xFF);
0195         value >>= 8;
0196     }
0197     return total;
0198 }
0199
0200 static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt,
0201                         bool is_ce)
0202 {
0203     u32 reg_offset_low, reg_offset_high;
0204     u32 err_low, err_high;
0205     u32 err_count;
0206
0207     reg_offset_low = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_31_00 :
0208                  REG_OFFSET_ECC_ERRD_COUNT_31_00;
0209     reg_offset_high = is_ce ? REG_OFFSET_ECC_ERRC_COUNT_63_32 :
0210                   REG_OFFSET_ECC_ERRD_COUNT_63_32;
0211
0212     err_low = dmc520_read_reg(pvt, reg_offset_low);
0213     err_high = dmc520_read_reg(pvt, reg_offset_high);
0214     /* Reset error counters */
0215     dmc520_write_reg(pvt, 0, reg_offset_low);
0216     dmc520_write_reg(pvt, 0, reg_offset_high);
0217
0218     err_count = dmc520_calc_dram_ecc_error(err_low) +
0219            dmc520_calc_dram_ecc_error(err_high);
0220
0221     return err_count;
0222 }
0223
0224 static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt,
0225                         bool is_ce,
0226                         struct ecc_error_info *info)
0227 {
0228     u32 reg_offset_low, reg_offset_high;
0229     u32 reg_val_low, reg_val_high;
0230     bool valid;
0231
0232     reg_offset_low = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_31_00 :
0233                  REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_31_00;
0234     reg_offset_high = is_ce ? REG_OFFSET_DRAM_ECC_ERRC_INT_INFO_63_32 :
0235                   REG_OFFSET_DRAM_ECC_ERRD_INT_INFO_63_32;
0236
0237     reg_val_low = dmc520_read_reg(pvt, reg_offset_low);
0238     reg_val_high = dmc520_read_reg(pvt, reg_offset_high);
0239
0240     valid = (FIELD_GET(REG_FIELD_ERR_INFO_LOW_VALID, reg_val_low) != 0) &&
0241         (FIELD_GET(REG_FIELD_ERR_INFO_HIGH_VALID, reg_val_high) != 0);
0242
0243     if (valid) {
0244         info->col = FIELD_GET(REG_FIELD_ERR_INFO_LOW_COL, reg_val_low);
0245         info->row = FIELD_GET(REG_FIELD_ERR_INFO_LOW_ROW, reg_val_low);
0246         info->rank = FIELD_GET(REG_FIELD_ERR_INFO_LOW_RANK, reg_val_low);
0247         info->bank = FIELD_GET(REG_FIELD_ERR_INFO_HIGH_BANK, reg_val_high);
0248     } else {
0249         memset(info, 0, sizeof(*info));
0250     }
0251 }
0252
0253 static bool dmc520_is_ecc_enabled(void __iomem *reg_base)
0254 {
0255     u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG);
0256
0257     return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val);
0258 }
0259
0260 static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt)
0261 {
0262     enum scrub_type type = SCRUB_NONE;
0263     u32 reg_val, scrub_cfg;
0264
0265     reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);
0266     scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val);
0267
0268     if (scrub_cfg == DMC520_SCRUB_TRIGGER_ERR_DETECT ||
0269         scrub_cfg == DMC520_SCRUB_TRIGGER_IDLE)
0270         type = SCRUB_HW_PROG;
0271
0272     return type;
0273 }
0274
0275 /* Get the memory data bus width, in number of bytes. */
0276 static u32 dmc520_get_memory_width(struct dmc520_edac *pvt)
0277 {
0278     enum dmc520_mem_width mem_width_field;
0279     u32 mem_width_in_bytes = 0;
0280     u32 reg_val;
0281
0282     reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);
0283     mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val);
0284
0285     if (mem_width_field == MEM_WIDTH_X32)
0286         mem_width_in_bytes = 4;
0287     else if (mem_width_field == MEM_WIDTH_X64)
0288         mem_width_in_bytes = 8;
0289     return mem_width_in_bytes;
0290 }
0291
0292 static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt)
0293 {
0294     enum mem_type mt = MEM_UNKNOWN;
0295     enum dmc520_mem_type type;
0296     u32 reg_val;
0297
0298     reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
0299     type = FIELD_GET(REG_FIELD_MEMORY_TYPE, reg_val);
0300
0301     switch (type) {
0302     case MEM_TYPE_DDR3:
0303         mt = MEM_DDR3;
0304         break;
0305
0306     case MEM_TYPE_DDR4:
0307         mt = MEM_DDR4;
0308         break;
0309     }
0310
0311     return mt;
0312 }
0313
0314 static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt)
0315 {
0316     enum dmc520_dev_width device_width;
0317     enum dev_type dt = DEV_UNKNOWN;
0318     u32 reg_val;
0319
0320     reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
0321     device_width = FIELD_GET(REG_FIELD_DEVICE_WIDTH, reg_val);
0322
0323     switch (device_width) {
0324     case DEV_WIDTH_X4:
0325         dt = DEV_X4;
0326         break;
0327
0328     case DEV_WIDTH_X8:
0329         dt = DEV_X8;
0330         break;
0331
0332     case DEV_WIDTH_X16:
0333         dt = DEV_X16;
0334         break;
0335     }
0336
0337     return dt;
0338 }
0339
0340 static u32 dmc520_get_rank_count(void __iomem *reg_base)
0341 {
0342     u32 reg_val, rank_bits;
0343
0344     reg_val = readl(reg_base + REG_OFFSET_ADDRESS_CONTROL_NOW);
0345     rank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_RANK, reg_val);
0346
0347     return BIT(rank_bits);
0348 }
0349
0350 static u64 dmc520_get_rank_size(struct dmc520_edac *pvt)
0351 {
0352     u32 reg_val, col_bits, row_bits, bank_bits;
0353
0354     reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);
0355
0356     col_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_COL, reg_val) +
0357            DRAM_ADDRESS_CONTROL_MIN_COL_BITS;
0358     row_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_ROW, reg_val) +
0359            DRAM_ADDRESS_CONTROL_MIN_ROW_BITS;
0360     bank_bits = FIELD_GET(REG_FIELD_ADDRESS_CONTROL_BANK, reg_val);
0361
0362     return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits);
0363 }
0364
0365 static void dmc520_handle_dram_ecc_errors(struct mem_ctl_info *mci,
0366                        bool is_ce)
0367 {
0368     struct dmc520_edac *pvt = mci->pvt_info;
0369     char message[DMC520_MSG_BUF_SIZE];
0370     struct ecc_error_info info;
0371     u32 cnt;
0372
0373     dmc520_get_dram_ecc_error_info(pvt, is_ce, &info);
0374
0375     cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce);
0376     if (!cnt)
0377         return;
0378
0379     snprintf(message, ARRAY_SIZE(message),
0380          "rank:%d bank:%d row:%d col:%d",
0381          info.rank, info.bank,
0382          info.row, info.col);
0383
0384     spin_lock(&pvt->error_lock);
0385     edac_mc_handle_error((is_ce ? HW_EVENT_ERR_CORRECTED :
0386                  HW_EVENT_ERR_UNCORRECTED),
0387                  mci, cnt, 0, 0, 0, info.rank, -1, -1,
0388                  message, "");
0389     spin_unlock(&pvt->error_lock);
0390 }
0391
0392 static irqreturn_t dmc520_edac_dram_ecc_isr(int irq, struct mem_ctl_info *mci,
0393                          bool is_ce)
0394 {
0395     struct dmc520_edac *pvt = mci->pvt_info;
0396     u32 i_mask;
0397
0398     i_mask = is_ce ? DRAM_ECC_INT_CE_BIT : DRAM_ECC_INT_UE_BIT;
0399
0400     dmc520_handle_dram_ecc_errors(mci, is_ce);
0401
0402     dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR);
0403
0404     return IRQ_HANDLED;
0405 }
0406
0407 static irqreturn_t dmc520_edac_dram_all_isr(int irq, struct mem_ctl_info *mci,
0408                          u32 irq_mask)
0409 {
0410     struct dmc520_edac *pvt = mci->pvt_info;
0411     irqreturn_t irq_ret = IRQ_NONE;
0412     u32 status;
0413
0414     status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS);
0415
0416     if ((irq_mask & DRAM_ECC_INT_CE_BIT) &&
0417         (status & DRAM_ECC_INT_CE_BIT))
0418         irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, true);
0419
0420     if ((irq_mask & DRAM_ECC_INT_UE_BIT) &&
0421         (status & DRAM_ECC_INT_UE_BIT))
0422         irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, false);
0423
0424     return irq_ret;
0425 }
0426
0427 static irqreturn_t dmc520_isr(int irq, void *data)
0428 {
0429     struct mem_ctl_info *mci = data;
0430     struct dmc520_edac *pvt = mci->pvt_info;
0431     u32 mask = 0;
0432     int idx;
0433
0434     for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
0435         if (pvt->irqs[idx] == irq) {
0436             mask = pvt->masks[idx];
0437             break;
0438         }
0439     }
0440     return dmc520_edac_dram_all_isr(irq, mci, mask);
0441 }
0442
0443 static void dmc520_init_csrow(struct mem_ctl_info *mci)
0444 {
0445     struct dmc520_edac *pvt = mci->pvt_info;
0446     struct csrow_info *csi;
0447     struct dimm_info *dimm;
0448     u32 pages_per_rank;
0449     enum dev_type dt;
0450     enum mem_type mt;
0451     int row, ch;
0452     u64 rs;
0453
0454     dt = dmc520_get_dtype(pvt);
0455     mt = dmc520_get_mtype(pvt);
0456     rs = dmc520_get_rank_size(pvt);
0457     pages_per_rank = rs >> PAGE_SHIFT;
0458
0459     for (row = 0; row < mci->nr_csrows; row++) {
0460         csi = mci->csrows[row];
0461
0462         for (ch = 0; ch < csi->nr_channels; ch++) {
0463             dimm        = csi->channels[ch]->dimm;
0464             dimm->grain = pvt->mem_width_in_bytes;
0465             dimm->dtype = dt;
0466             dimm->mtype = mt;
0467             dimm->edac_mode = EDAC_SECDED;
0468             dimm->nr_pages  = pages_per_rank / csi->nr_channels;
0469         }
0470     }
0471 }
0472
0473 static int dmc520_edac_probe(struct platform_device *pdev)
0474 {
0475     bool registered[NUMBER_OF_IRQS] = { false };
0476     int irqs[NUMBER_OF_IRQS] = { -ENXIO };
0477     int masks[NUMBER_OF_IRQS] = { 0 };
0478     struct edac_mc_layer layers[1];
0479     struct dmc520_edac *pvt = NULL;
0480     struct mem_ctl_info *mci;
0481     void __iomem *reg_base;
0482     u32 irq_mask_all = 0;
0483     struct resource *res;
0484     struct device *dev;
0485     int ret, idx, irq;
0486     u32 reg_val;
0487
0488     /* Parse the device node */
0489     dev = &pdev->dev;
0490
0491     for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
0492         irq = platform_get_irq_byname_optional(pdev, dmc520_irq_configs[idx].name);
0493         irqs[idx] = irq;
0494         masks[idx] = dmc520_irq_configs[idx].mask;
0495         if (irq >= 0) {
0496             irq_mask_all |= dmc520_irq_configs[idx].mask;
0497             edac_dbg(0, "Discovered %s, irq: %d.\n", dmc520_irq_configs[idx].name, irq);
0498         }
0499     }
0500
0501     if (!irq_mask_all) {
0502         edac_printk(KERN_ERR, EDAC_MOD_NAME,
0503                 "At least one valid interrupt line is expected.\n");
0504         return -EINVAL;
0505     }
0506
0507     /* Initialize dmc520 edac */
0508     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0509     reg_base = devm_ioremap_resource(dev, res);
0510     if (IS_ERR(reg_base))
0511         return PTR_ERR(reg_base);
0512
0513     if (!dmc520_is_ecc_enabled(reg_base))
0514         return -ENXIO;
0515
0516     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0517     layers[0].size = dmc520_get_rank_count(reg_base);
0518     layers[0].is_virt_csrow = true;
0519
0520     mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt));
0521     if (!mci) {
0522         edac_printk(KERN_ERR, EDAC_MOD_NAME,
0523                 "Failed to allocate memory for mc instance\n");
0524         ret = -ENOMEM;
0525         goto err;
0526     }
0527
0528     pvt = mci->pvt_info;
0529
0530     pvt->reg_base = reg_base;
0531     spin_lock_init(&pvt->error_lock);
0532     memcpy(pvt->irqs, irqs, sizeof(irqs));
0533     memcpy(pvt->masks, masks, sizeof(masks));
0534
0535     platform_set_drvdata(pdev, mci);
0536
0537     mci->pdev = dev;
0538     mci->mtype_cap      = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
0539     mci->edac_ctl_cap   = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
0540     mci->edac_cap       = EDAC_FLAG_SECDED;
0541     mci->scrub_cap      = SCRUB_FLAG_HW_SRC;
0542     mci->scrub_mode     = dmc520_get_scrub_type(pvt);
0543     mci->ctl_name       = EDAC_CTL_NAME;
0544     mci->dev_name       = dev_name(mci->pdev);
0545     mci->mod_name       = EDAC_MOD_NAME;
0546
0547     edac_op_state = EDAC_OPSTATE_INT;
0548
0549     pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt);
0550
0551     dmc520_init_csrow(mci);
0552
0553     /* Clear interrupts, not affecting other unrelated interrupts */
0554     reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
0555     dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
0556              REG_OFFSET_INTERRUPT_CONTROL);
0557     dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);
0558
0559     for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
0560         irq = irqs[idx];
0561         if (irq >= 0) {
0562             ret = devm_request_irq(&pdev->dev, irq,
0563                            dmc520_isr, IRQF_SHARED,
0564                            dev_name(&pdev->dev), mci);
0565             if (ret < 0) {
0566                 edac_printk(KERN_ERR, EDAC_MC,
0567                         "Failed to request irq %d\n", irq);
0568                 goto err;
0569             }
0570             registered[idx] = true;
0571         }
0572     }
0573
0574     /* Reset DRAM CE/UE counters */
0575     if (irq_mask_all & DRAM_ECC_INT_CE_BIT)
0576         dmc520_get_dram_ecc_error_count(pvt, true);
0577
0578     if (irq_mask_all & DRAM_ECC_INT_UE_BIT)
0579         dmc520_get_dram_ecc_error_count(pvt, false);
0580
0581     ret = edac_mc_add_mc(mci);
0582     if (ret) {
0583         edac_printk(KERN_ERR, EDAC_MOD_NAME,
0584                 "Failed to register with EDAC core\n");
0585         goto err;
0586     }
0587
0588     /* Enable interrupts, not affecting other unrelated interrupts */
0589     dmc520_write_reg(pvt, reg_val | irq_mask_all,
0590              REG_OFFSET_INTERRUPT_CONTROL);
0591
0592     return 0;
0593
0594 err:
0595     for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
0596         if (registered[idx])
0597             devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
0598     }
0599     if (mci)
0600         edac_mc_free(mci);
0601
0602     return ret;
0603 }
0604
0605 static int dmc520_edac_remove(struct platform_device *pdev)
0606 {
0607     u32 reg_val, idx, irq_mask_all = 0;
0608     struct mem_ctl_info *mci;
0609     struct dmc520_edac *pvt;
0610
0611     mci = platform_get_drvdata(pdev);
0612     pvt = mci->pvt_info;
0613
0614     /* Disable interrupts */
0615     reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
0616     dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
0617              REG_OFFSET_INTERRUPT_CONTROL);
0618
0619     /* free irq's */
0620     for (idx = 0; idx < NUMBER_OF_IRQS; idx++) {
0621         if (pvt->irqs[idx] >= 0) {
0622             irq_mask_all |= pvt->masks[idx];
0623             devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
0624         }
0625     }
0626
0627     edac_mc_del_mc(&pdev->dev);
0628     edac_mc_free(mci);
0629
0630     return 0;
0631 }
0632
0633 static const struct of_device_id dmc520_edac_driver_id[] = {
0634     { .compatible = "arm,dmc-520", },
0635     { /* end of table */ }
0636 };
0637
0638 MODULE_DEVICE_TABLE(of, dmc520_edac_driver_id);
0639
0640 static struct platform_driver dmc520_edac_driver = {
0641     .driver = {
0642         .name = "dmc520",
0643         .of_match_table = dmc520_edac_driver_id,
0644     },
0645
0646     .probe = dmc520_edac_probe,
0647     .remove = dmc520_edac_remove
0648 };
0649
0650 module_platform_driver(dmc520_edac_driver);
0651
0652 MODULE_AUTHOR("Rui Zhao <ruizhao@microsoft.com>");
0653 MODULE_AUTHOR("Lei Wang <lewan@microsoft.com>");
0654 MODULE_AUTHOR("Shiping Ji <shji@microsoft.com>");
0655 MODULE_DESCRIPTION("DMC-520 ECC driver");
0656 MODULE_LICENSE("GPL v2");