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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller.
0004  *
0005  * Copyright (c) 2008 Wind River Systems, Inc.
0006  *
0007  * Authors: Cao Qingtao <qingtao.cao@windriver.com>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/edac.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/gfp.h>
0017 
0018 #include "edac_module.h"
0019 
0020 #define CPC925_EDAC_REVISION    " Ver: 1.0.0"
0021 #define CPC925_EDAC_MOD_STR "cpc925_edac"
0022 
0023 #define cpc925_printk(level, fmt, arg...) \
0024     edac_printk(level, "CPC925", fmt, ##arg)
0025 
0026 #define cpc925_mc_printk(mci, level, fmt, arg...) \
0027     edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg)
0028 
0029 /*
0030  * CPC925 registers are of 32 bits with bit0 defined at the
0031  * most significant bit and bit31 at that of least significant.
0032  */
0033 #define CPC925_BITS_PER_REG 32
0034 #define CPC925_BIT(nr)      (1UL << (CPC925_BITS_PER_REG - 1 - nr))
0035 
0036 /*
0037  * EDAC device names for the error detections of
0038  * CPU Interface and Hypertransport Link.
0039  */
0040 #define CPC925_CPU_ERR_DEV  "cpu"
0041 #define CPC925_HT_LINK_DEV  "htlink"
0042 
0043 /* Suppose DDR Refresh cycle is 15.6 microsecond */
0044 #define CPC925_REF_FREQ     0xFA69
0045 #define CPC925_SCRUB_BLOCK_SIZE 64  /* bytes */
0046 #define CPC925_NR_CSROWS    8
0047 
0048 /*
0049  * All registers and bits definitions are taken from
0050  * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02".
0051  */
0052 
0053 /*
0054  * CPU and Memory Controller Registers
0055  */
0056 /************************************************************
0057  *  Processor Interface Exception Mask Register (APIMASK)
0058  ************************************************************/
0059 #define REG_APIMASK_OFFSET  0x30070
0060 enum apimask_bits {
0061     APIMASK_DART    = CPC925_BIT(0), /* DART Exception */
0062     APIMASK_ADI0    = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
0063     APIMASK_ADI1    = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
0064     APIMASK_STAT    = CPC925_BIT(3), /* Status Exception */
0065     APIMASK_DERR    = CPC925_BIT(4), /* Data Error Exception */
0066     APIMASK_ADRS0   = CPC925_BIT(5), /* Addressing Exception on PI0 */
0067     APIMASK_ADRS1   = CPC925_BIT(6), /* Addressing Exception on PI1 */
0068                      /* BIT(7) Reserved */
0069     APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
0070     APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
0071     APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
0072     APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
0073 
0074     CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 |
0075                APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 |
0076                APIMASK_ADRS1),
0077     ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H |
0078                APIMASK_ECC_UE_L | APIMASK_ECC_CE_L),
0079 };
0080 #define APIMASK_ADI(n)      CPC925_BIT(((n)+1))
0081 
0082 /************************************************************
0083  *  Processor Interface Exception Register (APIEXCP)
0084  ************************************************************/
0085 #define REG_APIEXCP_OFFSET  0x30060
0086 enum apiexcp_bits {
0087     APIEXCP_DART    = CPC925_BIT(0), /* DART Exception */
0088     APIEXCP_ADI0    = CPC925_BIT(1), /* Handshake Error on PI0_ADI */
0089     APIEXCP_ADI1    = CPC925_BIT(2), /* Handshake Error on PI1_ADI */
0090     APIEXCP_STAT    = CPC925_BIT(3), /* Status Exception */
0091     APIEXCP_DERR    = CPC925_BIT(4), /* Data Error Exception */
0092     APIEXCP_ADRS0   = CPC925_BIT(5), /* Addressing Exception on PI0 */
0093     APIEXCP_ADRS1   = CPC925_BIT(6), /* Addressing Exception on PI1 */
0094                      /* BIT(7) Reserved */
0095     APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */
0096     APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */
0097     APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */
0098     APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */
0099 
0100     CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 |
0101                  APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 |
0102                  APIEXCP_ADRS1),
0103     UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L),
0104     CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L),
0105     ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED),
0106 };
0107 
0108 /************************************************************
0109  *  Memory Bus Configuration Register (MBCR)
0110 ************************************************************/
0111 #define REG_MBCR_OFFSET     0x2190
0112 #define MBCR_64BITCFG_SHIFT 23
0113 #define MBCR_64BITCFG_MASK  (1UL << MBCR_64BITCFG_SHIFT)
0114 #define MBCR_64BITBUS_SHIFT 22
0115 #define MBCR_64BITBUS_MASK  (1UL << MBCR_64BITBUS_SHIFT)
0116 
0117 /************************************************************
0118  *  Memory Bank Mode Register (MBMR)
0119 ************************************************************/
0120 #define REG_MBMR_OFFSET     0x21C0
0121 #define MBMR_MODE_MAX_VALUE 0xF
0122 #define MBMR_MODE_SHIFT     25
0123 #define MBMR_MODE_MASK      (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT)
0124 #define MBMR_BBA_SHIFT      24
0125 #define MBMR_BBA_MASK       (1UL << MBMR_BBA_SHIFT)
0126 
0127 /************************************************************
0128  *  Memory Bank Boundary Address Register (MBBAR)
0129  ************************************************************/
0130 #define REG_MBBAR_OFFSET    0x21D0
0131 #define MBBAR_BBA_MAX_VALUE 0xFF
0132 #define MBBAR_BBA_SHIFT     24
0133 #define MBBAR_BBA_MASK      (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT)
0134 
0135 /************************************************************
0136  *  Memory Scrub Control Register (MSCR)
0137  ************************************************************/
0138 #define REG_MSCR_OFFSET     0x2400
0139 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/
0140 #define MSCR_BACKGR_SCRUB   0x40000000 /* 01 */
0141 #define MSCR_SI_SHIFT       16  /* si - bit8:15*/
0142 #define MSCR_SI_MAX_VALUE   0xFF
0143 #define MSCR_SI_MASK        (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT)
0144 
0145 /************************************************************
0146  *  Memory Scrub Range Start Register (MSRSR)
0147  ************************************************************/
0148 #define REG_MSRSR_OFFSET    0x2410
0149 
0150 /************************************************************
0151  *  Memory Scrub Range End Register (MSRER)
0152  ************************************************************/
0153 #define REG_MSRER_OFFSET    0x2420
0154 
0155 /************************************************************
0156  *  Memory Scrub Pattern Register (MSPR)
0157  ************************************************************/
0158 #define REG_MSPR_OFFSET     0x2430
0159 
0160 /************************************************************
0161  *  Memory Check Control Register (MCCR)
0162  ************************************************************/
0163 #define REG_MCCR_OFFSET     0x2440
0164 enum mccr_bits {
0165     MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */
0166 };
0167 
0168 /************************************************************
0169  *  Memory Check Range End Register (MCRER)
0170  ************************************************************/
0171 #define REG_MCRER_OFFSET    0x2450
0172 
0173 /************************************************************
0174  *  Memory Error Address Register (MEAR)
0175  ************************************************************/
0176 #define REG_MEAR_OFFSET     0x2460
0177 #define MEAR_BCNT_MAX_VALUE 0x3
0178 #define MEAR_BCNT_SHIFT     30
0179 #define MEAR_BCNT_MASK      (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT)
0180 #define MEAR_RANK_MAX_VALUE 0x7
0181 #define MEAR_RANK_SHIFT     27
0182 #define MEAR_RANK_MASK      (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT)
0183 #define MEAR_COL_MAX_VALUE  0x7FF
0184 #define MEAR_COL_SHIFT      16
0185 #define MEAR_COL_MASK       (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT)
0186 #define MEAR_BANK_MAX_VALUE 0x3
0187 #define MEAR_BANK_SHIFT     14
0188 #define MEAR_BANK_MASK      (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT)
0189 #define MEAR_ROW_MASK       0x00003FFF
0190 
0191 /************************************************************
0192  *  Memory Error Syndrome Register (MESR)
0193  ************************************************************/
0194 #define REG_MESR_OFFSET     0x2470
0195 #define MESR_ECC_SYN_H_MASK 0xFF00
0196 #define MESR_ECC_SYN_L_MASK 0x00FF
0197 
0198 /************************************************************
0199  *  Memory Mode Control Register (MMCR)
0200  ************************************************************/
0201 #define REG_MMCR_OFFSET     0x2500
0202 enum mmcr_bits {
0203     MMCR_REG_DIMM_MODE = CPC925_BIT(3),
0204 };
0205 
0206 /*
0207  * HyperTransport Link Registers
0208  */
0209 /************************************************************
0210  *  Error Handling/Enumeration Scratch Pad Register (ERRCTRL)
0211  ************************************************************/
0212 #define REG_ERRCTRL_OFFSET  0x70140
0213 enum errctrl_bits {          /* nonfatal interrupts for */
0214     ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */
0215     ERRCTRL_CRC_NF  = CPC925_BIT(1), /* CRC error */
0216     ERRCTRL_RSP_NF  = CPC925_BIT(2), /* Response error */
0217     ERRCTRL_EOC_NF  = CPC925_BIT(3), /* End-Of-Chain error */
0218     ERRCTRL_OVF_NF  = CPC925_BIT(4), /* Overflow error */
0219     ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */
0220 
0221     ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */
0222     ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */
0223 
0224     HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF |
0225                  ERRCTRL_RSP_NF | ERRCTRL_EOC_NF |
0226                  ERRCTRL_OVF_NF | ERRCTRL_PROT_NF),
0227     HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL),
0228 };
0229 
0230 /************************************************************
0231  *  Link Configuration and Link Control Register (LINKCTRL)
0232  ************************************************************/
0233 #define REG_LINKCTRL_OFFSET 0x70110
0234 enum linkctrl_bits {
0235     LINKCTRL_CRC_ERR    = (CPC925_BIT(22) | CPC925_BIT(23)),
0236     LINKCTRL_LINK_FAIL  = CPC925_BIT(27),
0237 
0238     HT_LINKCTRL_DETECTED    = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL),
0239 };
0240 
0241 /************************************************************
0242  *  Link FreqCap/Error/Freq/Revision ID Register (LINKERR)
0243  ************************************************************/
0244 #define REG_LINKERR_OFFSET  0x70120
0245 enum linkerr_bits {
0246     LINKERR_EOC_ERR     = CPC925_BIT(17), /* End-Of-Chain error */
0247     LINKERR_OVF_ERR     = CPC925_BIT(18), /* Receive Buffer Overflow */
0248     LINKERR_PROT_ERR    = CPC925_BIT(19), /* Protocol error */
0249 
0250     HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR |
0251                    LINKERR_PROT_ERR),
0252 };
0253 
0254 /************************************************************
0255  *  Bridge Control Register (BRGCTRL)
0256  ************************************************************/
0257 #define REG_BRGCTRL_OFFSET  0x70300
0258 enum brgctrl_bits {
0259     BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */
0260     BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */
0261 };
0262 
0263 /* Private structure for edac memory controller */
0264 struct cpc925_mc_pdata {
0265     void __iomem *vbase;
0266     unsigned long total_mem;
0267     const char *name;
0268     int edac_idx;
0269 };
0270 
0271 /* Private structure for common edac device */
0272 struct cpc925_dev_info {
0273     void __iomem *vbase;
0274     struct platform_device *pdev;
0275     char *ctl_name;
0276     int edac_idx;
0277     struct edac_device_ctl_info *edac_dev;
0278     void (*init)(struct cpc925_dev_info *dev_info);
0279     void (*exit)(struct cpc925_dev_info *dev_info);
0280     void (*check)(struct edac_device_ctl_info *edac_dev);
0281 };
0282 
0283 /* Get total memory size from Open Firmware DTB */
0284 static void get_total_mem(struct cpc925_mc_pdata *pdata)
0285 {
0286     struct device_node *np = NULL;
0287     const unsigned int *reg, *reg_end;
0288     int len, sw, aw;
0289     unsigned long start, size;
0290 
0291     np = of_find_node_by_type(NULL, "memory");
0292     if (!np)
0293         return;
0294 
0295     aw = of_n_addr_cells(np);
0296     sw = of_n_size_cells(np);
0297     reg = (const unsigned int *)of_get_property(np, "reg", &len);
0298     reg_end = reg + len/4;
0299 
0300     pdata->total_mem = 0;
0301     do {
0302         start = of_read_number(reg, aw);
0303         reg += aw;
0304         size = of_read_number(reg, sw);
0305         reg += sw;
0306         edac_dbg(1, "start 0x%lx, size 0x%lx\n", start, size);
0307         pdata->total_mem += size;
0308     } while (reg < reg_end);
0309 
0310     of_node_put(np);
0311     edac_dbg(0, "total_mem 0x%lx\n", pdata->total_mem);
0312 }
0313 
0314 static void cpc925_init_csrows(struct mem_ctl_info *mci)
0315 {
0316     struct cpc925_mc_pdata *pdata = mci->pvt_info;
0317     struct csrow_info *csrow;
0318     struct dimm_info *dimm;
0319     enum dev_type dtype;
0320     int index, j;
0321     u32 mbmr, mbbar, bba, grain;
0322     unsigned long row_size, nr_pages, last_nr_pages = 0;
0323 
0324     get_total_mem(pdata);
0325 
0326     for (index = 0; index < mci->nr_csrows; index++) {
0327         mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET +
0328                    0x20 * index);
0329         mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET +
0330                    0x20 + index);
0331         bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) |
0332                ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT);
0333 
0334         if (bba == 0)
0335             continue; /* not populated */
0336 
0337         csrow = mci->csrows[index];
0338 
0339         row_size = bba * (1UL << 28);   /* 256M */
0340         csrow->first_page = last_nr_pages;
0341         nr_pages = row_size >> PAGE_SHIFT;
0342         csrow->last_page = csrow->first_page + nr_pages - 1;
0343         last_nr_pages = csrow->last_page + 1;
0344 
0345         switch (csrow->nr_channels) {
0346         case 1: /* Single channel */
0347             grain = 32; /* four-beat burst of 32 bytes */
0348             break;
0349         case 2: /* Dual channel */
0350         default:
0351             grain = 64; /* four-beat burst of 64 bytes */
0352             break;
0353         }
0354         switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) {
0355         case 6: /* 0110, no way to differentiate X8 VS X16 */
0356         case 5: /* 0101 */
0357         case 8: /* 1000 */
0358             dtype = DEV_X16;
0359             break;
0360         case 7: /* 0111 */
0361         case 9: /* 1001 */
0362             dtype = DEV_X8;
0363             break;
0364         default:
0365             dtype = DEV_UNKNOWN;
0366         break;
0367         }
0368         for (j = 0; j < csrow->nr_channels; j++) {
0369             dimm = csrow->channels[j]->dimm;
0370             dimm->nr_pages = nr_pages / csrow->nr_channels;
0371             dimm->mtype = MEM_RDDR;
0372             dimm->edac_mode = EDAC_SECDED;
0373             dimm->grain = grain;
0374             dimm->dtype = dtype;
0375         }
0376     }
0377 }
0378 
0379 /* Enable memory controller ECC detection */
0380 static void cpc925_mc_init(struct mem_ctl_info *mci)
0381 {
0382     struct cpc925_mc_pdata *pdata = mci->pvt_info;
0383     u32 apimask;
0384     u32 mccr;
0385 
0386     /* Enable various ECC error exceptions */
0387     apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET);
0388     if ((apimask & ECC_MASK_ENABLE) == 0) {
0389         apimask |= ECC_MASK_ENABLE;
0390         __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET);
0391     }
0392 
0393     /* Enable ECC detection */
0394     mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET);
0395     if ((mccr & MCCR_ECC_EN) == 0) {
0396         mccr |= MCCR_ECC_EN;
0397         __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET);
0398     }
0399 }
0400 
0401 /* Disable memory controller ECC detection */
0402 static void cpc925_mc_exit(struct mem_ctl_info *mci)
0403 {
0404     /*
0405      * WARNING:
0406      * We are supposed to clear the ECC error detection bits,
0407      * and it will be no problem to do so. However, once they
0408      * are cleared here if we want to re-install CPC925 EDAC
0409      * module later, setting them up in cpc925_mc_init() will
0410      * trigger machine check exception.
0411      * Also, it's ok to leave ECC error detection bits enabled,
0412      * since they are reset to 1 by default or by boot loader.
0413      */
0414 
0415     return;
0416 }
0417 
0418 /*
0419  * Revert DDR column/row/bank addresses into page frame number and
0420  * offset in page.
0421  *
0422  * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs),
0423  * physical address(PA) bits to column address(CA) bits mappings are:
0424  * CA   0   1   2   3   4   5   6   7   8   9   10
0425  * PA   59  58  57  56  55  54  53  52  51  50  49
0426  *
0427  * physical address(PA) bits to bank address(BA) bits mappings are:
0428  * BA   0   1
0429  * PA   43  44
0430  *
0431  * physical address(PA) bits to row address(RA) bits mappings are:
0432  * RA   0   1   2   3   4   5   6   7   8   9   10   11   12
0433  * PA   36  35  34  48  47  46  45  40  41  42  39   38   37
0434  */
0435 static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
0436         unsigned long *pfn, unsigned long *offset, int *csrow)
0437 {
0438     u32 bcnt, rank, col, bank, row;
0439     u32 c;
0440     unsigned long pa;
0441     int i;
0442 
0443     bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT;
0444     rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT;
0445     col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT;
0446     bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT;
0447     row = mear & MEAR_ROW_MASK;
0448 
0449     *csrow = rank;
0450 
0451 #ifdef CONFIG_EDAC_DEBUG
0452     if (mci->csrows[rank]->first_page == 0) {
0453         cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a "
0454             "non-populated csrow, broken hardware?\n");
0455         return;
0456     }
0457 #endif
0458 
0459     /* Revert csrow number */
0460     pa = mci->csrows[rank]->first_page << PAGE_SHIFT;
0461 
0462     /* Revert column address */
0463     col += bcnt;
0464     for (i = 0; i < 11; i++) {
0465         c = col & 0x1;
0466         col >>= 1;
0467         pa |= c << (14 - i);
0468     }
0469 
0470     /* Revert bank address */
0471     pa |= bank << 19;
0472 
0473     /* Revert row address, in 4 steps */
0474     for (i = 0; i < 3; i++) {
0475         c = row & 0x1;
0476         row >>= 1;
0477         pa |= c << (26 - i);
0478     }
0479 
0480     for (i = 0; i < 3; i++) {
0481         c = row & 0x1;
0482         row >>= 1;
0483         pa |= c << (21 + i);
0484     }
0485 
0486     for (i = 0; i < 4; i++) {
0487         c = row & 0x1;
0488         row >>= 1;
0489         pa |= c << (18 - i);
0490     }
0491 
0492     for (i = 0; i < 3; i++) {
0493         c = row & 0x1;
0494         row >>= 1;
0495         pa |= c << (29 - i);
0496     }
0497 
0498     *offset = pa & (PAGE_SIZE - 1);
0499     *pfn = pa >> PAGE_SHIFT;
0500 
0501     edac_dbg(0, "ECC physical address 0x%lx\n", pa);
0502 }
0503 
0504 static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
0505 {
0506     if ((syndrome & MESR_ECC_SYN_H_MASK) == 0)
0507         return 0;
0508 
0509     if ((syndrome & MESR_ECC_SYN_L_MASK) == 0)
0510         return 1;
0511 
0512     cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n",
0513              syndrome);
0514     return 1;
0515 }
0516 
0517 /* Check memory controller registers for ECC errors */
0518 static void cpc925_mc_check(struct mem_ctl_info *mci)
0519 {
0520     struct cpc925_mc_pdata *pdata = mci->pvt_info;
0521     u32 apiexcp;
0522     u32 mear;
0523     u32 mesr;
0524     u16 syndrome;
0525     unsigned long pfn = 0, offset = 0;
0526     int csrow = 0, channel = 0;
0527 
0528     /* APIEXCP is cleared when read */
0529     apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET);
0530     if ((apiexcp & ECC_EXCP_DETECTED) == 0)
0531         return;
0532 
0533     mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET);
0534     syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK);
0535 
0536     mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET);
0537 
0538     /* Revert column/row addresses into page frame number, etc */
0539     cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow);
0540 
0541     if (apiexcp & CECC_EXCP_DETECTED) {
0542         cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n");
0543         channel = cpc925_mc_find_channel(mci, syndrome);
0544         edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0545                      pfn, offset, syndrome,
0546                      csrow, channel, -1,
0547                      mci->ctl_name, "");
0548     }
0549 
0550     if (apiexcp & UECC_EXCP_DETECTED) {
0551         cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n");
0552         edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0553                      pfn, offset, 0,
0554                      csrow, -1, -1,
0555                      mci->ctl_name, "");
0556     }
0557 
0558     cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n");
0559     cpc925_mc_printk(mci, KERN_INFO, "APIMASK       0x%08x\n",
0560         __raw_readl(pdata->vbase + REG_APIMASK_OFFSET));
0561     cpc925_mc_printk(mci, KERN_INFO, "APIEXCP       0x%08x\n",
0562         apiexcp);
0563     cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl    0x%08x\n",
0564         __raw_readl(pdata->vbase + REG_MSCR_OFFSET));
0565     cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start   0x%08x\n",
0566         __raw_readl(pdata->vbase + REG_MSRSR_OFFSET));
0567     cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n",
0568         __raw_readl(pdata->vbase + REG_MSRER_OFFSET));
0569     cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n",
0570         __raw_readl(pdata->vbase + REG_MSPR_OFFSET));
0571     cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl      0x%08x\n",
0572         __raw_readl(pdata->vbase + REG_MCCR_OFFSET));
0573     cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End   0x%08x\n",
0574         __raw_readl(pdata->vbase + REG_MCRER_OFFSET));
0575     cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address   0x%08x\n",
0576         mesr);
0577     cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome  0x%08x\n",
0578         syndrome);
0579 }
0580 
0581 /******************** CPU err device********************************/
0582 static u32 cpc925_cpu_mask_disabled(void)
0583 {
0584     struct device_node *cpunode;
0585     static u32 mask = 0;
0586 
0587     /* use cached value if available */
0588     if (mask != 0)
0589         return mask;
0590 
0591     mask = APIMASK_ADI0 | APIMASK_ADI1;
0592 
0593     for_each_of_cpu_node(cpunode) {
0594         const u32 *reg = of_get_property(cpunode, "reg", NULL);
0595         if (reg == NULL || *reg > 2) {
0596             cpc925_printk(KERN_ERR, "Bad reg value at %pOF\n", cpunode);
0597             continue;
0598         }
0599 
0600         mask &= ~APIMASK_ADI(*reg);
0601     }
0602 
0603     if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) {
0604         /* We assume that each CPU sits on it's own PI and that
0605          * for present CPUs the reg property equals to the PI
0606          * interface id */
0607         cpc925_printk(KERN_WARNING,
0608                 "Assuming PI id is equal to CPU MPIC id!\n");
0609     }
0610 
0611     return mask;
0612 }
0613 
0614 /* Enable CPU Errors detection */
0615 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info)
0616 {
0617     u32 apimask;
0618     u32 cpumask;
0619 
0620     apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
0621 
0622     cpumask = cpc925_cpu_mask_disabled();
0623     if (apimask & cpumask) {
0624         cpc925_printk(KERN_WARNING, "CPU(s) not present, "
0625                 "but enabled in APIMASK, disabling\n");
0626         apimask &= ~cpumask;
0627     }
0628 
0629     if ((apimask & CPU_MASK_ENABLE) == 0)
0630         apimask |= CPU_MASK_ENABLE;
0631 
0632     __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET);
0633 }
0634 
0635 /* Disable CPU Errors detection */
0636 static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info)
0637 {
0638     /*
0639      * WARNING:
0640      * We are supposed to clear the CPU error detection bits,
0641      * and it will be no problem to do so. However, once they
0642      * are cleared here if we want to re-install CPC925 EDAC
0643      * module later, setting them up in cpc925_cpu_init() will
0644      * trigger machine check exception.
0645      * Also, it's ok to leave CPU error detection bits enabled,
0646      * since they are reset to 1 by default.
0647      */
0648 
0649     return;
0650 }
0651 
0652 /* Check for CPU Errors */
0653 static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev)
0654 {
0655     struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
0656     u32 apiexcp;
0657     u32 apimask;
0658 
0659     /* APIEXCP is cleared when read */
0660     apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET);
0661     if ((apiexcp & CPU_EXCP_DETECTED) == 0)
0662         return;
0663 
0664     if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0)
0665         return;
0666 
0667     apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET);
0668     cpc925_printk(KERN_INFO, "Processor Interface Fault\n"
0669                  "Processor Interface register dump:\n");
0670     cpc925_printk(KERN_INFO, "APIMASK       0x%08x\n", apimask);
0671     cpc925_printk(KERN_INFO, "APIEXCP       0x%08x\n", apiexcp);
0672 
0673     edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
0674 }
0675 
0676 /******************** HT Link err device****************************/
0677 /* Enable HyperTransport Link Error detection */
0678 static void cpc925_htlink_init(struct cpc925_dev_info *dev_info)
0679 {
0680     u32 ht_errctrl;
0681 
0682     ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
0683     if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) {
0684         ht_errctrl |= HT_ERRCTRL_ENABLE;
0685         __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
0686     }
0687 }
0688 
0689 /* Disable HyperTransport Link Error detection */
0690 static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info)
0691 {
0692     u32 ht_errctrl;
0693 
0694     ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
0695     ht_errctrl &= ~HT_ERRCTRL_ENABLE;
0696     __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET);
0697 }
0698 
0699 /* Check for HyperTransport Link errors */
0700 static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev)
0701 {
0702     struct cpc925_dev_info *dev_info = edac_dev->pvt_info;
0703     u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET);
0704     u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET);
0705     u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET);
0706     u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET);
0707 
0708     if (!((brgctrl & BRGCTRL_DETSERR) ||
0709           (linkctrl & HT_LINKCTRL_DETECTED) ||
0710           (errctrl & HT_ERRCTRL_DETECTED) ||
0711           (linkerr & HT_LINKERR_DETECTED)))
0712         return;
0713 
0714     cpc925_printk(KERN_INFO, "HT Link Fault\n"
0715                  "HT register dump:\n");
0716     cpc925_printk(KERN_INFO, "Bridge Ctrl           0x%08x\n",
0717               brgctrl);
0718     cpc925_printk(KERN_INFO, "Link Config Ctrl      0x%08x\n",
0719               linkctrl);
0720     cpc925_printk(KERN_INFO, "Error Enum and Ctrl       0x%08x\n",
0721               errctrl);
0722     cpc925_printk(KERN_INFO, "Link Error            0x%08x\n",
0723               linkerr);
0724 
0725     /* Clear by write 1 */
0726     if (brgctrl & BRGCTRL_DETSERR)
0727         __raw_writel(BRGCTRL_DETSERR,
0728                 dev_info->vbase + REG_BRGCTRL_OFFSET);
0729 
0730     if (linkctrl & HT_LINKCTRL_DETECTED)
0731         __raw_writel(HT_LINKCTRL_DETECTED,
0732                 dev_info->vbase + REG_LINKCTRL_OFFSET);
0733 
0734     /* Initiate Secondary Bus Reset to clear the chain failure */
0735     if (errctrl & ERRCTRL_CHN_FAL)
0736         __raw_writel(BRGCTRL_SECBUSRESET,
0737                 dev_info->vbase + REG_BRGCTRL_OFFSET);
0738 
0739     if (errctrl & ERRCTRL_RSP_ERR)
0740         __raw_writel(ERRCTRL_RSP_ERR,
0741                 dev_info->vbase + REG_ERRCTRL_OFFSET);
0742 
0743     if (linkerr & HT_LINKERR_DETECTED)
0744         __raw_writel(HT_LINKERR_DETECTED,
0745                 dev_info->vbase + REG_LINKERR_OFFSET);
0746 
0747     edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
0748 }
0749 
0750 static struct cpc925_dev_info cpc925_devs[] = {
0751     {
0752     .ctl_name = CPC925_CPU_ERR_DEV,
0753     .init = cpc925_cpu_init,
0754     .exit = cpc925_cpu_exit,
0755     .check = cpc925_cpu_check,
0756     },
0757     {
0758     .ctl_name = CPC925_HT_LINK_DEV,
0759     .init = cpc925_htlink_init,
0760     .exit = cpc925_htlink_exit,
0761     .check = cpc925_htlink_check,
0762     },
0763     { }
0764 };
0765 
0766 /*
0767  * Add CPU Err detection and HyperTransport Link Err detection
0768  * as common "edac_device", they have no corresponding device
0769  * nodes in the Open Firmware DTB and we have to add platform
0770  * devices for them. Also, they will share the MMIO with that
0771  * of memory controller.
0772  */
0773 static void cpc925_add_edac_devices(void __iomem *vbase)
0774 {
0775     struct cpc925_dev_info *dev_info;
0776 
0777     if (!vbase) {
0778         cpc925_printk(KERN_ERR, "MMIO not established yet\n");
0779         return;
0780     }
0781 
0782     for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
0783         dev_info->vbase = vbase;
0784         dev_info->pdev = platform_device_register_simple(
0785                     dev_info->ctl_name, 0, NULL, 0);
0786         if (IS_ERR(dev_info->pdev)) {
0787             cpc925_printk(KERN_ERR,
0788                 "Can't register platform device for %s\n",
0789                 dev_info->ctl_name);
0790             continue;
0791         }
0792 
0793         /*
0794          * Don't have to allocate private structure but
0795          * make use of cpc925_devs[] instead.
0796          */
0797         dev_info->edac_idx = edac_device_alloc_index();
0798         dev_info->edac_dev =
0799             edac_device_alloc_ctl_info(0, dev_info->ctl_name,
0800                 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx);
0801         if (!dev_info->edac_dev) {
0802             cpc925_printk(KERN_ERR, "No memory for edac device\n");
0803             goto err1;
0804         }
0805 
0806         dev_info->edac_dev->pvt_info = dev_info;
0807         dev_info->edac_dev->dev = &dev_info->pdev->dev;
0808         dev_info->edac_dev->ctl_name = dev_info->ctl_name;
0809         dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR;
0810         dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev);
0811 
0812         if (edac_op_state == EDAC_OPSTATE_POLL)
0813             dev_info->edac_dev->edac_check = dev_info->check;
0814 
0815         if (dev_info->init)
0816             dev_info->init(dev_info);
0817 
0818         if (edac_device_add_device(dev_info->edac_dev) > 0) {
0819             cpc925_printk(KERN_ERR,
0820                 "Unable to add edac device for %s\n",
0821                 dev_info->ctl_name);
0822             goto err2;
0823         }
0824 
0825         edac_dbg(0, "Successfully added edac device for %s\n",
0826              dev_info->ctl_name);
0827 
0828         continue;
0829 
0830 err2:
0831         if (dev_info->exit)
0832             dev_info->exit(dev_info);
0833         edac_device_free_ctl_info(dev_info->edac_dev);
0834 err1:
0835         platform_device_unregister(dev_info->pdev);
0836     }
0837 }
0838 
0839 /*
0840  * Delete the common "edac_device" for CPU Err Detection
0841  * and HyperTransport Link Err Detection
0842  */
0843 static void cpc925_del_edac_devices(void)
0844 {
0845     struct cpc925_dev_info *dev_info;
0846 
0847     for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) {
0848         if (dev_info->edac_dev) {
0849             edac_device_del_device(dev_info->edac_dev->dev);
0850             edac_device_free_ctl_info(dev_info->edac_dev);
0851             platform_device_unregister(dev_info->pdev);
0852         }
0853 
0854         if (dev_info->exit)
0855             dev_info->exit(dev_info);
0856 
0857         edac_dbg(0, "Successfully deleted edac device for %s\n",
0858              dev_info->ctl_name);
0859     }
0860 }
0861 
0862 /* Convert current back-ground scrub rate into byte/sec bandwidth */
0863 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
0864 {
0865     struct cpc925_mc_pdata *pdata = mci->pvt_info;
0866     int bw;
0867     u32 mscr;
0868     u8 si;
0869 
0870     mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
0871     si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
0872 
0873     edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr);
0874 
0875     if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
0876         (si == 0)) {
0877         cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
0878         bw = 0;
0879     } else
0880         bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
0881 
0882     return bw;
0883 }
0884 
0885 /* Return 0 for single channel; 1 for dual channel */
0886 static int cpc925_mc_get_channels(void __iomem *vbase)
0887 {
0888     int dual = 0;
0889     u32 mbcr;
0890 
0891     mbcr = __raw_readl(vbase + REG_MBCR_OFFSET);
0892 
0893     /*
0894      * Dual channel only when 128-bit wide physical bus
0895      * and 128-bit configuration.
0896      */
0897     if (((mbcr & MBCR_64BITCFG_MASK) == 0) &&
0898         ((mbcr & MBCR_64BITBUS_MASK) == 0))
0899         dual = 1;
0900 
0901     edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single");
0902 
0903     return dual;
0904 }
0905 
0906 static int cpc925_probe(struct platform_device *pdev)
0907 {
0908     static int edac_mc_idx;
0909     struct mem_ctl_info *mci;
0910     struct edac_mc_layer layers[2];
0911     void __iomem *vbase;
0912     struct cpc925_mc_pdata *pdata;
0913     struct resource *r;
0914     int res = 0, nr_channels;
0915 
0916     edac_dbg(0, "%s platform device found!\n", pdev->name);
0917 
0918     if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
0919         res = -ENOMEM;
0920         goto out;
0921     }
0922 
0923     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0924     if (!r) {
0925         cpc925_printk(KERN_ERR, "Unable to get resource\n");
0926         res = -ENOENT;
0927         goto err1;
0928     }
0929 
0930     if (!devm_request_mem_region(&pdev->dev,
0931                      r->start,
0932                      resource_size(r),
0933                      pdev->name)) {
0934         cpc925_printk(KERN_ERR, "Unable to request mem region\n");
0935         res = -EBUSY;
0936         goto err1;
0937     }
0938 
0939     vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0940     if (!vbase) {
0941         cpc925_printk(KERN_ERR, "Unable to ioremap device\n");
0942         res = -ENOMEM;
0943         goto err2;
0944     }
0945 
0946     nr_channels = cpc925_mc_get_channels(vbase) + 1;
0947 
0948     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0949     layers[0].size = CPC925_NR_CSROWS;
0950     layers[0].is_virt_csrow = true;
0951     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0952     layers[1].size = nr_channels;
0953     layers[1].is_virt_csrow = false;
0954     mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
0955                 sizeof(struct cpc925_mc_pdata));
0956     if (!mci) {
0957         cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n");
0958         res = -ENOMEM;
0959         goto err2;
0960     }
0961 
0962     pdata = mci->pvt_info;
0963     pdata->vbase = vbase;
0964     pdata->edac_idx = edac_mc_idx++;
0965     pdata->name = pdev->name;
0966 
0967     mci->pdev = &pdev->dev;
0968     platform_set_drvdata(pdev, mci);
0969     mci->dev_name = dev_name(&pdev->dev);
0970     mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
0971     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
0972     mci->edac_cap = EDAC_FLAG_SECDED;
0973     mci->mod_name = CPC925_EDAC_MOD_STR;
0974     mci->ctl_name = pdev->name;
0975 
0976     if (edac_op_state == EDAC_OPSTATE_POLL)
0977         mci->edac_check = cpc925_mc_check;
0978 
0979     mci->ctl_page_to_phys = NULL;
0980     mci->scrub_mode = SCRUB_SW_SRC;
0981     mci->set_sdram_scrub_rate = NULL;
0982     mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate;
0983 
0984     cpc925_init_csrows(mci);
0985 
0986     /* Setup memory controller registers */
0987     cpc925_mc_init(mci);
0988 
0989     if (edac_mc_add_mc(mci) > 0) {
0990         cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n");
0991         goto err3;
0992     }
0993 
0994     cpc925_add_edac_devices(vbase);
0995 
0996     /* get this far and it's successful */
0997     edac_dbg(0, "success\n");
0998 
0999     res = 0;
1000     goto out;
1001 
1002 err3:
1003     cpc925_mc_exit(mci);
1004     edac_mc_free(mci);
1005 err2:
1006     devm_release_mem_region(&pdev->dev, r->start, resource_size(r));
1007 err1:
1008     devres_release_group(&pdev->dev, cpc925_probe);
1009 out:
1010     return res;
1011 }
1012 
1013 static int cpc925_remove(struct platform_device *pdev)
1014 {
1015     struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1016 
1017     /*
1018      * Delete common edac devices before edac mc, because
1019      * the former share the MMIO of the latter.
1020      */
1021     cpc925_del_edac_devices();
1022     cpc925_mc_exit(mci);
1023 
1024     edac_mc_del_mc(&pdev->dev);
1025     edac_mc_free(mci);
1026 
1027     return 0;
1028 }
1029 
1030 static struct platform_driver cpc925_edac_driver = {
1031     .probe = cpc925_probe,
1032     .remove = cpc925_remove,
1033     .driver = {
1034            .name = "cpc925_edac",
1035     }
1036 };
1037 
1038 static int __init cpc925_edac_init(void)
1039 {
1040     int ret = 0;
1041 
1042     printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n");
1043     printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n");
1044 
1045     /* Only support POLL mode so far */
1046     edac_op_state = EDAC_OPSTATE_POLL;
1047 
1048     ret = platform_driver_register(&cpc925_edac_driver);
1049     if (ret) {
1050         printk(KERN_WARNING "Failed to register %s\n",
1051             CPC925_EDAC_MOD_STR);
1052     }
1053 
1054     return ret;
1055 }
1056 
1057 static void __exit cpc925_edac_exit(void)
1058 {
1059     platform_driver_unregister(&cpc925_edac_driver);
1060 }
1061 
1062 module_init(cpc925_edac_init);
1063 module_exit(cpc925_edac_exit);
1064 
1065 MODULE_LICENSE("GPL");
1066 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>");
1067 MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module");
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