Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Cell MIC driver for ECC counting
0003  *
0004  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
0005  *                <benh@kernel.crashing.org>
0006  *
0007  * This file may be distributed under the terms of the
0008  * GNU General Public License.
0009  */
0010 #undef DEBUG
0011 
0012 #include <linux/edac.h>
0013 #include <linux/module.h>
0014 #include <linux/init.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/stop_machine.h>
0017 #include <linux/io.h>
0018 #include <linux/of_address.h>
0019 #include <asm/machdep.h>
0020 #include <asm/cell-regs.h>
0021 
0022 #include "edac_module.h"
0023 
0024 struct cell_edac_priv
0025 {
0026     struct cbe_mic_tm_regs __iomem  *regs;
0027     int             node;
0028     int             chanmask;
0029 #ifdef DEBUG
0030     u64             prev_fir;
0031 #endif
0032 };
0033 
0034 static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
0035 {
0036     struct cell_edac_priv       *priv = mci->pvt_info;
0037     struct csrow_info       *csrow = mci->csrows[0];
0038     unsigned long           address, pfn, offset, syndrome;
0039 
0040     dev_dbg(mci->pdev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
0041         priv->node, chan, ar);
0042 
0043     /* Address decoding is likely a bit bogus, to dbl check */
0044     address = (ar & 0xffffffffe0000000ul) >> 29;
0045     if (priv->chanmask == 0x3)
0046         address = (address << 1) | chan;
0047     pfn = address >> PAGE_SHIFT;
0048     offset = address & ~PAGE_MASK;
0049     syndrome = (ar & 0x000000001fe00000ul) >> 21;
0050 
0051     /* TODO: Decoding of the error address */
0052     edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
0053                  csrow->first_page + pfn, offset, syndrome,
0054                  0, chan, -1, "", "");
0055 }
0056 
0057 static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
0058 {
0059     struct cell_edac_priv       *priv = mci->pvt_info;
0060     struct csrow_info       *csrow = mci->csrows[0];
0061     unsigned long           address, pfn, offset;
0062 
0063     dev_dbg(mci->pdev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
0064         priv->node, chan, ar);
0065 
0066     /* Address decoding is likely a bit bogus, to dbl check */
0067     address = (ar & 0xffffffffe0000000ul) >> 29;
0068     if (priv->chanmask == 0x3)
0069         address = (address << 1) | chan;
0070     pfn = address >> PAGE_SHIFT;
0071     offset = address & ~PAGE_MASK;
0072 
0073     /* TODO: Decoding of the error address */
0074     edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
0075                  csrow->first_page + pfn, offset, 0,
0076                  0, chan, -1, "", "");
0077 }
0078 
0079 static void cell_edac_check(struct mem_ctl_info *mci)
0080 {
0081     struct cell_edac_priv       *priv = mci->pvt_info;
0082     u64             fir, addreg, clear = 0;
0083 
0084     fir = in_be64(&priv->regs->mic_fir);
0085 #ifdef DEBUG
0086     if (fir != priv->prev_fir) {
0087         dev_dbg(mci->pdev, "fir change : 0x%016lx\n", fir);
0088         priv->prev_fir = fir;
0089     }
0090 #endif
0091     if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
0092         addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
0093         clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
0094         cell_edac_count_ce(mci, 0, addreg);
0095     }
0096     if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
0097         addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
0098         clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
0099         cell_edac_count_ce(mci, 1, addreg);
0100     }
0101     if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
0102         addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
0103         clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
0104         cell_edac_count_ue(mci, 0, addreg);
0105     }
0106     if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
0107         addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
0108         clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
0109         cell_edac_count_ue(mci, 1, addreg);
0110     }
0111 
0112     /* The procedure for clearing FIR bits is a bit ... weird */
0113     if (clear) {
0114         fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
0115         fir |= CBE_MIC_FIR_ECC_RESET_MASK;
0116         fir &= ~clear;
0117         out_be64(&priv->regs->mic_fir, fir);
0118         (void)in_be64(&priv->regs->mic_fir);
0119 
0120         mb();   /* sync up */
0121 #ifdef DEBUG
0122         fir = in_be64(&priv->regs->mic_fir);
0123         dev_dbg(mci->pdev, "fir clear  : 0x%016lx\n", fir);
0124 #endif
0125     }
0126 }
0127 
0128 static void cell_edac_init_csrows(struct mem_ctl_info *mci)
0129 {
0130     struct csrow_info       *csrow = mci->csrows[0];
0131     struct dimm_info        *dimm;
0132     struct cell_edac_priv       *priv = mci->pvt_info;
0133     struct device_node      *np;
0134     int             j;
0135     u32             nr_pages;
0136 
0137     for_each_node_by_name(np, "memory") {
0138         struct resource r;
0139 
0140         /* We "know" that the Cell firmware only creates one entry
0141          * in the "memory" nodes. If that changes, this code will
0142          * need to be adapted.
0143          */
0144         if (of_address_to_resource(np, 0, &r))
0145             continue;
0146         if (of_node_to_nid(np) != priv->node)
0147             continue;
0148         csrow->first_page = r.start >> PAGE_SHIFT;
0149         nr_pages = resource_size(&r) >> PAGE_SHIFT;
0150         csrow->last_page = csrow->first_page + nr_pages - 1;
0151 
0152         for (j = 0; j < csrow->nr_channels; j++) {
0153             dimm = csrow->channels[j]->dimm;
0154             dimm->mtype = MEM_XDR;
0155             dimm->edac_mode = EDAC_SECDED;
0156             dimm->nr_pages = nr_pages / csrow->nr_channels;
0157         }
0158         dev_dbg(mci->pdev,
0159             "Initialized on node %d, chanmask=0x%x,"
0160             " first_page=0x%lx, nr_pages=0x%x\n",
0161             priv->node, priv->chanmask,
0162             csrow->first_page, nr_pages);
0163         break;
0164     }
0165     of_node_put(np);
0166 }
0167 
0168 static int cell_edac_probe(struct platform_device *pdev)
0169 {
0170     struct cbe_mic_tm_regs __iomem  *regs;
0171     struct mem_ctl_info     *mci;
0172     struct edac_mc_layer        layers[2];
0173     struct cell_edac_priv       *priv;
0174     u64             reg;
0175     int             rc, chanmask, num_chans;
0176 
0177     regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
0178     if (regs == NULL)
0179         return -ENODEV;
0180 
0181     edac_op_state = EDAC_OPSTATE_POLL;
0182 
0183     /* Get channel population */
0184     reg = in_be64(&regs->mic_mnt_cfg);
0185     dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
0186     chanmask = 0;
0187     if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
0188         chanmask |= 0x1;
0189     if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
0190         chanmask |= 0x2;
0191     if (chanmask == 0) {
0192         dev_warn(&pdev->dev,
0193              "Yuck ! No channel populated ? Aborting !\n");
0194         return -ENODEV;
0195     }
0196     dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
0197         in_be64(&regs->mic_fir));
0198 
0199     /* Allocate & init EDAC MC data structure */
0200     num_chans = chanmask == 3 ? 2 : 1;
0201 
0202     layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
0203     layers[0].size = 1;
0204     layers[0].is_virt_csrow = true;
0205     layers[1].type = EDAC_MC_LAYER_CHANNEL;
0206     layers[1].size = num_chans;
0207     layers[1].is_virt_csrow = false;
0208     mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
0209                 sizeof(struct cell_edac_priv));
0210     if (mci == NULL)
0211         return -ENOMEM;
0212     priv = mci->pvt_info;
0213     priv->regs = regs;
0214     priv->node = pdev->id;
0215     priv->chanmask = chanmask;
0216     mci->pdev = &pdev->dev;
0217     mci->mtype_cap = MEM_FLAG_XDR;
0218     mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
0219     mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
0220     mci->mod_name = "cell_edac";
0221     mci->ctl_name = "MIC";
0222     mci->dev_name = dev_name(&pdev->dev);
0223     mci->edac_check = cell_edac_check;
0224     cell_edac_init_csrows(mci);
0225 
0226     /* Register with EDAC core */
0227     rc = edac_mc_add_mc(mci);
0228     if (rc) {
0229         dev_err(&pdev->dev, "failed to register with EDAC core\n");
0230         edac_mc_free(mci);
0231         return rc;
0232     }
0233 
0234     return 0;
0235 }
0236 
0237 static int cell_edac_remove(struct platform_device *pdev)
0238 {
0239     struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
0240     if (mci)
0241         edac_mc_free(mci);
0242     return 0;
0243 }
0244 
0245 static struct platform_driver cell_edac_driver = {
0246     .driver     = {
0247         .name   = "cbe-mic",
0248     },
0249     .probe      = cell_edac_probe,
0250     .remove     = cell_edac_remove,
0251 };
0252 
0253 static int __init cell_edac_init(void)
0254 {
0255     /* Sanity check registers data structure */
0256     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0257                   mic_df_ecc_address_0) != 0xf8);
0258     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0259                   mic_df_ecc_address_1) != 0x1b8);
0260     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0261                   mic_df_config) != 0x218);
0262     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0263                   mic_fir) != 0x230);
0264     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0265                   mic_mnt_cfg) != 0x210);
0266     BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
0267                   mic_exc) != 0x208);
0268 
0269     return platform_driver_register(&cell_edac_driver);
0270 }
0271 
0272 static void __exit cell_edac_exit(void)
0273 {
0274     platform_driver_unregister(&cell_edac_driver);
0275 }
0276 
0277 module_init(cell_edac_init);
0278 module_exit(cell_edac_exit);
0279 
0280 MODULE_LICENSE("GPL");
0281 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
0282 MODULE_DESCRIPTION("ECC counting for Cell MIC");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!