drivers/edac/bluefield_edac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Bluefield-specific EDAC driver.
0004  *
0005  * Copyright (c) 2019 Mellanox Technologies.
0006  */
0007
0008 #include <linux/acpi.h>
0009 #include <linux/arm-smccc.h>
0010 #include <linux/bitfield.h>
0011 #include <linux/edac.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015
0016 #include "edac_module.h"
0017
0018 #define DRIVER_NAME     "bluefield-edac"
0019
0020 /*
0021  * Mellanox BlueField EMI (External Memory Interface) register definitions.
0022  */
0023
0024 #define MLXBF_ECC_CNT 0x340
0025 #define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)
0026 #define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)
0027
0028 #define MLXBF_ECC_ERR 0x348
0029 #define MLXBF_ECC_ERR__SECC BIT(0)
0030 #define MLXBF_ECC_ERR__DECC BIT(16)
0031
0032 #define MLXBF_ECC_LATCH_SEL 0x354
0033 #define MLXBF_ECC_LATCH_SEL__START BIT(24)
0034
0035 #define MLXBF_ERR_ADDR_0 0x358
0036
0037 #define MLXBF_ERR_ADDR_1 0x37c
0038
0039 #define MLXBF_SYNDROM 0x35c
0040 #define MLXBF_SYNDROM__DERR BIT(0)
0041 #define MLXBF_SYNDROM__SERR BIT(1)
0042 #define MLXBF_SYNDROM__SYN GENMASK(25, 16)
0043
0044 #define MLXBF_ADD_INFO 0x364
0045 #define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)
0046
0047 #define MLXBF_EDAC_MAX_DIMM_PER_MC  2
0048 #define MLXBF_EDAC_ERROR_GRAIN      8
0049
0050 /*
0051  * Request MLNX_SIP_GET_DIMM_INFO
0052  *
0053  * Retrieve information about DIMM on a certain slot.
0054  *
0055  * Call register usage:
0056  * a0: MLNX_SIP_GET_DIMM_INFO
0057  * a1: (Memory controller index) << 16 | (Dimm index in memory controller)
0058  * a2-7: not used.
0059  *
0060  * Return status:
0061  * a0: MLXBF_DIMM_INFO defined below describing the DIMM.
0062  * a1-3: not used.
0063  */
0064 #define MLNX_SIP_GET_DIMM_INFO      0x82000008
0065
0066 /* Format for the SMC response about the memory information */
0067 #define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0)
0068 #define MLXBF_DIMM_INFO__IS_RDIMM BIT(16)
0069 #define MLXBF_DIMM_INFO__IS_LRDIMM BIT(17)
0070 #define MLXBF_DIMM_INFO__IS_NVDIMM BIT(18)
0071 #define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21)
0072 #define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24)
0073
0074 struct bluefield_edac_priv {
0075     int dimm_ranks[MLXBF_EDAC_MAX_DIMM_PER_MC];
0076     void __iomem *emi_base;
0077     int dimm_per_mc;
0078 };
0079
0080 static u64 smc_call1(u64 smc_op, u64 smc_arg)
0081 {
0082     struct arm_smccc_res res;
0083
0084     arm_smccc_smc(smc_op, smc_arg, 0, 0, 0, 0, 0, 0, &res);
0085
0086     return res.a0;
0087 }
0088
0089 /*
0090  * Gather the ECC information from the External Memory Interface registers
0091  * and report it to the edac handler.
0092  */
0093 static void bluefield_gather_report_ecc(struct mem_ctl_info *mci,
0094                     int error_cnt,
0095                     int is_single_ecc)
0096 {
0097     struct bluefield_edac_priv *priv = mci->pvt_info;
0098     u32 dram_additional_info, err_prank, edea0, edea1;
0099     u32 ecc_latch_select, dram_syndrom, serr, derr, syndrom;
0100     enum hw_event_mc_err_type ecc_type;
0101     u64 ecc_dimm_addr;
0102     int ecc_dimm;
0103
0104     ecc_type = is_single_ecc ? HW_EVENT_ERR_CORRECTED :
0105                    HW_EVENT_ERR_UNCORRECTED;
0106
0107     /*
0108      * Tell the External Memory Interface to populate the relevant
0109      * registers with information about the last ECC error occurrence.
0110      */
0111     ecc_latch_select = MLXBF_ECC_LATCH_SEL__START;
0112     writel(ecc_latch_select, priv->emi_base + MLXBF_ECC_LATCH_SEL);
0113
0114     /*
0115      * Verify that the ECC reported info in the registers is of the
0116      * same type as the one asked to report. If not, just report the
0117      * error without the detailed information.
0118      */
0119     dram_syndrom = readl(priv->emi_base + MLXBF_SYNDROM);
0120     serr = FIELD_GET(MLXBF_SYNDROM__SERR, dram_syndrom);
0121     derr = FIELD_GET(MLXBF_SYNDROM__DERR, dram_syndrom);
0122     syndrom = FIELD_GET(MLXBF_SYNDROM__SYN, dram_syndrom);
0123
0124     if ((is_single_ecc && !serr) || (!is_single_ecc && !derr)) {
0125         edac_mc_handle_error(ecc_type, mci, error_cnt, 0, 0, 0,
0126                      0, 0, -1, mci->ctl_name, "");
0127         return;
0128     }
0129
0130     dram_additional_info = readl(priv->emi_base + MLXBF_ADD_INFO);
0131     err_prank = FIELD_GET(MLXBF_ADD_INFO__ERR_PRANK, dram_additional_info);
0132
0133     ecc_dimm = (err_prank >= 2 && priv->dimm_ranks[0] <= 2) ? 1 : 0;
0134
0135     edea0 = readl(priv->emi_base + MLXBF_ERR_ADDR_0);
0136     edea1 = readl(priv->emi_base + MLXBF_ERR_ADDR_1);
0137
0138     ecc_dimm_addr = ((u64)edea1 << 32) | edea0;
0139
0140     edac_mc_handle_error(ecc_type, mci, error_cnt,
0141                  PFN_DOWN(ecc_dimm_addr),
0142                  offset_in_page(ecc_dimm_addr),
0143                  syndrom, ecc_dimm, 0, 0, mci->ctl_name, "");
0144 }
0145
0146 static void bluefield_edac_check(struct mem_ctl_info *mci)
0147 {
0148     struct bluefield_edac_priv *priv = mci->pvt_info;
0149     u32 ecc_count, single_error_count, double_error_count, ecc_error = 0;
0150
0151     /*
0152      * The memory controller might not be initialized by the firmware
0153      * when there isn't memory, which may lead to bad register readings.
0154      */
0155     if (mci->edac_cap == EDAC_FLAG_NONE)
0156         return;
0157
0158     ecc_count = readl(priv->emi_base + MLXBF_ECC_CNT);
0159     single_error_count = FIELD_GET(MLXBF_ECC_CNT__SERR_CNT, ecc_count);
0160     double_error_count = FIELD_GET(MLXBF_ECC_CNT__DERR_CNT, ecc_count);
0161
0162     if (single_error_count) {
0163         ecc_error |= MLXBF_ECC_ERR__SECC;
0164
0165         bluefield_gather_report_ecc(mci, single_error_count, 1);
0166     }
0167
0168     if (double_error_count) {
0169         ecc_error |= MLXBF_ECC_ERR__DECC;
0170
0171         bluefield_gather_report_ecc(mci, double_error_count, 0);
0172     }
0173
0174     /* Write to clear reported errors. */
0175     if (ecc_count)
0176         writel(ecc_error, priv->emi_base + MLXBF_ECC_ERR);
0177 }
0178
0179 /* Initialize the DIMMs information for the given memory controller. */
0180 static void bluefield_edac_init_dimms(struct mem_ctl_info *mci)
0181 {
0182     struct bluefield_edac_priv *priv = mci->pvt_info;
0183     int mem_ctrl_idx = mci->mc_idx;
0184     struct dimm_info *dimm;
0185     u64 smc_info, smc_arg;
0186     int is_empty = 1, i;
0187
0188     for (i = 0; i < priv->dimm_per_mc; i++) {
0189         dimm = mci->dimms[i];
0190
0191         smc_arg = mem_ctrl_idx << 16 | i;
0192         smc_info = smc_call1(MLNX_SIP_GET_DIMM_INFO, smc_arg);
0193
0194         if (!FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info)) {
0195             dimm->mtype = MEM_EMPTY;
0196             continue;
0197         }
0198
0199         is_empty = 0;
0200
0201         dimm->edac_mode = EDAC_SECDED;
0202
0203         if (FIELD_GET(MLXBF_DIMM_INFO__IS_NVDIMM, smc_info))
0204             dimm->mtype = MEM_NVDIMM;
0205         else if (FIELD_GET(MLXBF_DIMM_INFO__IS_LRDIMM, smc_info))
0206             dimm->mtype = MEM_LRDDR4;
0207         else if (FIELD_GET(MLXBF_DIMM_INFO__IS_RDIMM, smc_info))
0208             dimm->mtype = MEM_RDDR4;
0209         else
0210             dimm->mtype = MEM_DDR4;
0211
0212         dimm->nr_pages =
0213             FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info) *
0214             (SZ_1G / PAGE_SIZE);
0215         dimm->grain = MLXBF_EDAC_ERROR_GRAIN;
0216
0217         /* Mem controller for BlueField only supports x4, x8 and x16 */
0218         switch (FIELD_GET(MLXBF_DIMM_INFO__PACKAGE_X, smc_info)) {
0219         case 4:
0220             dimm->dtype = DEV_X4;
0221             break;
0222         case 8:
0223             dimm->dtype = DEV_X8;
0224             break;
0225         case 16:
0226             dimm->dtype = DEV_X16;
0227             break;
0228         default:
0229             dimm->dtype = DEV_UNKNOWN;
0230         }
0231
0232         priv->dimm_ranks[i] =
0233             FIELD_GET(MLXBF_DIMM_INFO__RANKS, smc_info);
0234     }
0235
0236     if (is_empty)
0237         mci->edac_cap = EDAC_FLAG_NONE;
0238     else
0239         mci->edac_cap = EDAC_FLAG_SECDED;
0240 }
0241
0242 static int bluefield_edac_mc_probe(struct platform_device *pdev)
0243 {
0244     struct bluefield_edac_priv *priv;
0245     struct device *dev = &pdev->dev;
0246     struct edac_mc_layer layers[1];
0247     struct mem_ctl_info *mci;
0248     struct resource *emi_res;
0249     unsigned int mc_idx, dimm_count;
0250     int rc, ret;
0251
0252     /* Read the MSS (Memory SubSystem) index from ACPI table. */
0253     if (device_property_read_u32(dev, "mss_number", &mc_idx)) {
0254         dev_warn(dev, "bf_edac: MSS number unknown\n");
0255         return -EINVAL;
0256     }
0257
0258     /* Read the DIMMs per MC from ACPI table. */
0259     if (device_property_read_u32(dev, "dimm_per_mc", &dimm_count)) {
0260         dev_warn(dev, "bf_edac: DIMMs per MC unknown\n");
0261         return -EINVAL;
0262     }
0263
0264     if (dimm_count > MLXBF_EDAC_MAX_DIMM_PER_MC) {
0265         dev_warn(dev, "bf_edac: DIMMs per MC not valid\n");
0266         return -EINVAL;
0267     }
0268
0269     emi_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0270     if (!emi_res)
0271         return -EINVAL;
0272
0273     layers[0].type = EDAC_MC_LAYER_SLOT;
0274     layers[0].size = dimm_count;
0275     layers[0].is_virt_csrow = true;
0276
0277     mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv));
0278     if (!mci)
0279         return -ENOMEM;
0280
0281     priv = mci->pvt_info;
0282
0283     priv->dimm_per_mc = dimm_count;
0284     priv->emi_base = devm_ioremap_resource(dev, emi_res);
0285     if (IS_ERR(priv->emi_base)) {
0286         dev_err(dev, "failed to map EMI IO resource\n");
0287         ret = PTR_ERR(priv->emi_base);
0288         goto err;
0289     }
0290
0291     mci->pdev = dev;
0292     mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 |
0293              MEM_FLAG_LRDDR4 | MEM_FLAG_NVDIMM;
0294     mci->edac_ctl_cap = EDAC_FLAG_SECDED;
0295
0296     mci->mod_name = DRIVER_NAME;
0297     mci->ctl_name = "BlueField_Memory_Controller";
0298     mci->dev_name = dev_name(dev);
0299     mci->edac_check = bluefield_edac_check;
0300
0301     /* Initialize mci with the actual populated DIMM information. */
0302     bluefield_edac_init_dimms(mci);
0303
0304     platform_set_drvdata(pdev, mci);
0305
0306     /* Register with EDAC core */
0307     rc = edac_mc_add_mc(mci);
0308     if (rc) {
0309         dev_err(dev, "failed to register with EDAC core\n");
0310         ret = rc;
0311         goto err;
0312     }
0313
0314     /* Only POLL mode supported so far. */
0315     edac_op_state = EDAC_OPSTATE_POLL;
0316
0317     return 0;
0318
0319 err:
0320     edac_mc_free(mci);
0321
0322     return ret;
0323
0324 }
0325
0326 static int bluefield_edac_mc_remove(struct platform_device *pdev)
0327 {
0328     struct mem_ctl_info *mci = platform_get_drvdata(pdev);
0329
0330     edac_mc_del_mc(&pdev->dev);
0331     edac_mc_free(mci);
0332
0333     return 0;
0334 }
0335
0336 static const struct acpi_device_id bluefield_mc_acpi_ids[] = {
0337     {"MLNXBF08", 0},
0338     {}
0339 };
0340
0341 MODULE_DEVICE_TABLE(acpi, bluefield_mc_acpi_ids);
0342
0343 static struct platform_driver bluefield_edac_mc_driver = {
0344     .driver = {
0345         .name = DRIVER_NAME,
0346         .acpi_match_table = bluefield_mc_acpi_ids,
0347     },
0348     .probe = bluefield_edac_mc_probe,
0349     .remove = bluefield_edac_mc_remove,
0350 };
0351
0352 module_platform_driver(bluefield_edac_mc_driver);
0353
0354 MODULE_DESCRIPTION("Mellanox BlueField memory edac driver");
0355 MODULE_AUTHOR("Mellanox Technologies");
0356 MODULE_LICENSE("GPL v2");