drivers/edac/amd8131_edac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
0004  *
0005  * Copyright (c) 2008 Wind River Systems, Inc.
0006  *
0007  * Authors: Cao Qingtao <qingtao.cao@windriver.com>
0008  *      Benjamin Walsh <benjamin.walsh@windriver.com>
0009  *      Hu Yongqi <yongqi.hu@windriver.com>
0010  */
0011
0012 #ifndef _AMD8131_EDAC_H_
0013 #define _AMD8131_EDAC_H_
0014
0015 #define DEVFN_PCIX_BRIDGE_NORTH_A   8
0016 #define DEVFN_PCIX_BRIDGE_NORTH_B   16
0017 #define DEVFN_PCIX_BRIDGE_SOUTH_A   24
0018 #define DEVFN_PCIX_BRIDGE_SOUTH_B   32
0019
0020 /************************************************************
0021  *  PCI-X Bridge Status and Command Register, DevA:0x04
0022  ************************************************************/
0023 #define REG_STS_CMD 0x04
0024 enum sts_cmd_bits {
0025     STS_CMD_SSE = BIT(30),
0026     STS_CMD_SERREN  = BIT(8)
0027 };
0028
0029 /************************************************************
0030  *  PCI-X Bridge Interrupt and Bridge Control Register,
0031  ************************************************************/
0032 #define REG_INT_CTLR    0x3c
0033 enum int_ctlr_bits {
0034     INT_CTLR_DTSE   = BIT(27),
0035     INT_CTLR_DTS    = BIT(26),
0036     INT_CTLR_SERR   = BIT(17),
0037     INT_CTLR_PERR   = BIT(16)
0038 };
0039
0040 /************************************************************
0041  *  PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
0042  ************************************************************/
0043 #define REG_MEM_LIM 0x1c
0044 enum mem_limit_bits {
0045     MEM_LIMIT_DPE   = BIT(31),
0046     MEM_LIMIT_RSE   = BIT(30),
0047     MEM_LIMIT_RMA   = BIT(29),
0048     MEM_LIMIT_RTA   = BIT(28),
0049     MEM_LIMIT_STA   = BIT(27),
0050     MEM_LIMIT_MDPE  = BIT(24),
0051     MEM_LIMIT_MASK  = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
0052                 MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
0053 };
0054
0055 /************************************************************
0056  *  Link Configuration And Control Register, side A
0057  ************************************************************/
0058 #define REG_LNK_CTRL_A  0xc4
0059
0060 /************************************************************
0061  *  Link Configuration And Control Register, side B
0062  ************************************************************/
0063 #define REG_LNK_CTRL_B  0xc8
0064
0065 enum lnk_ctrl_bits {
0066     LNK_CTRL_CRCERR_A   = BIT(9),
0067     LNK_CTRL_CRCERR_B   = BIT(8),
0068     LNK_CTRL_CRCFEN     = BIT(1)
0069 };
0070
0071 enum pcix_bridge_inst {
0072     NORTH_A = 0,
0073     NORTH_B = 1,
0074     SOUTH_A = 2,
0075     SOUTH_B = 3,
0076     NO_BRIDGE = 4
0077 };
0078
0079 struct amd8131_dev_info {
0080     int devfn;
0081     enum pcix_bridge_inst inst;
0082     struct pci_dev *dev;
0083     int edac_idx;   /* pci device index */
0084     char *ctl_name;
0085     struct edac_pci_ctl_info *edac_dev;
0086 };
0087
0088 /*
0089  * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
0090  * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
0091  * four PCIX Bridges on ATCA-6101 altogether.
0092  *
0093  * These PCIX Bridges share the same PCI Device ID and are all of
0094  * Function Zero, they could be discrimated by their pci_dev->devfn.
0095  * They share the same set of init/check/exit methods, and their
0096  * private structures are collected in the devices[] array.
0097  */
0098 struct amd8131_info {
0099     u16 err_dev;    /* PCI Device ID for AMD8131 APIC*/
0100     struct amd8131_dev_info *devices;
0101     void (*init)(struct amd8131_dev_info *dev_info);
0102     void (*exit)(struct amd8131_dev_info *dev_info);
0103     void (*check)(struct edac_pci_ctl_info *edac_dev);
0104 };
0105
0106 #endif /* _AMD8131_EDAC_H_ */
0107