drivers/edac/amd8131_edac.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
0004  *
0005  * Copyright (c) 2008 Wind River Systems, Inc.
0006  *
0007  * Authors: Cao Qingtao <qingtao.cao@windriver.com>
0008  *      Benjamin Walsh <benjamin.walsh@windriver.com>
0009  *      Hu Yongqi <yongqi.hu@windriver.com>
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/bitops.h>
0017 #include <linux/edac.h>
0018 #include <linux/pci_ids.h>
0019
0020 #include "edac_module.h"
0021 #include "amd8131_edac.h"
0022
0023 #define AMD8131_EDAC_REVISION   " Ver: 1.0.0"
0024 #define AMD8131_EDAC_MOD_STR    "amd8131_edac"
0025
0026 /* Wrapper functions for accessing PCI configuration space */
0027 static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
0028 {
0029     int ret;
0030
0031     ret = pci_read_config_dword(dev, reg, val32);
0032     if (ret != 0)
0033         printk(KERN_ERR AMD8131_EDAC_MOD_STR
0034             " PCI Access Read Error at 0x%x\n", reg);
0035 }
0036
0037 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
0038 {
0039     int ret;
0040
0041     ret = pci_write_config_dword(dev, reg, val32);
0042     if (ret != 0)
0043         printk(KERN_ERR AMD8131_EDAC_MOD_STR
0044             " PCI Access Write Error at 0x%x\n", reg);
0045 }
0046
0047 /* Support up to two AMD8131 chipsets on a platform */
0048 static struct amd8131_dev_info amd8131_devices[] = {
0049     {
0050     .inst = NORTH_A,
0051     .devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
0052     .ctl_name = "AMD8131_PCIX_NORTH_A",
0053     },
0054     {
0055     .inst = NORTH_B,
0056     .devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
0057     .ctl_name = "AMD8131_PCIX_NORTH_B",
0058     },
0059     {
0060     .inst = SOUTH_A,
0061     .devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
0062     .ctl_name = "AMD8131_PCIX_SOUTH_A",
0063     },
0064     {
0065     .inst = SOUTH_B,
0066     .devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
0067     .ctl_name = "AMD8131_PCIX_SOUTH_B",
0068     },
0069     {.inst = NO_BRIDGE,},
0070 };
0071
0072 static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
0073 {
0074     u32 val32;
0075     struct pci_dev *dev = dev_info->dev;
0076
0077     /* First clear error detection flags */
0078     edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
0079     if (val32 & MEM_LIMIT_MASK)
0080         edac_pci_write_dword(dev, REG_MEM_LIM, val32);
0081
0082     /* Clear Discard Timer Timedout flag */
0083     edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
0084     if (val32 & INT_CTLR_DTS)
0085         edac_pci_write_dword(dev, REG_INT_CTLR, val32);
0086
0087     /* Clear CRC Error flag on link side A */
0088     edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
0089     if (val32 & LNK_CTRL_CRCERR_A)
0090         edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
0091
0092     /* Clear CRC Error flag on link side B */
0093     edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
0094     if (val32 & LNK_CTRL_CRCERR_B)
0095         edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
0096
0097     /*
0098      * Then enable all error detections.
0099      *
0100      * Setup Discard Timer Sync Flood Enable,
0101      * System Error Enable and Parity Error Enable.
0102      */
0103     edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
0104     val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
0105     edac_pci_write_dword(dev, REG_INT_CTLR, val32);
0106
0107     /* Enable overall SERR Error detection */
0108     edac_pci_read_dword(dev, REG_STS_CMD, &val32);
0109     val32 |= STS_CMD_SERREN;
0110     edac_pci_write_dword(dev, REG_STS_CMD, val32);
0111
0112     /* Setup CRC Flood Enable for link side A */
0113     edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
0114     val32 |= LNK_CTRL_CRCFEN;
0115     edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
0116
0117     /* Setup CRC Flood Enable for link side B */
0118     edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
0119     val32 |= LNK_CTRL_CRCFEN;
0120     edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
0121 }
0122
0123 static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
0124 {
0125     u32 val32;
0126     struct pci_dev *dev = dev_info->dev;
0127
0128     /* Disable SERR, PERR and DTSE Error detection */
0129     edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
0130     val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
0131     edac_pci_write_dword(dev, REG_INT_CTLR, val32);
0132
0133     /* Disable overall System Error detection */
0134     edac_pci_read_dword(dev, REG_STS_CMD, &val32);
0135     val32 &= ~STS_CMD_SERREN;
0136     edac_pci_write_dword(dev, REG_STS_CMD, val32);
0137
0138     /* Disable CRC Sync Flood on link side A */
0139     edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
0140     val32 &= ~LNK_CTRL_CRCFEN;
0141     edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
0142
0143     /* Disable CRC Sync Flood on link side B */
0144     edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
0145     val32 &= ~LNK_CTRL_CRCFEN;
0146     edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
0147 }
0148
0149 static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
0150 {
0151     struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
0152     struct pci_dev *dev = dev_info->dev;
0153     u32 val32;
0154
0155     /* Check PCI-X Bridge Memory Base-Limit Register for errors */
0156     edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
0157     if (val32 & MEM_LIMIT_MASK) {
0158         printk(KERN_INFO "Error(s) in mem limit register "
0159             "on %s bridge\n", dev_info->ctl_name);
0160         printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
0161             "RTA: %d, STA: %d, MDPE: %d\n",
0162             val32 & MEM_LIMIT_DPE,
0163             val32 & MEM_LIMIT_RSE,
0164             val32 & MEM_LIMIT_RMA,
0165             val32 & MEM_LIMIT_RTA,
0166             val32 & MEM_LIMIT_STA,
0167             val32 & MEM_LIMIT_MDPE);
0168
0169         val32 |= MEM_LIMIT_MASK;
0170         edac_pci_write_dword(dev, REG_MEM_LIM, val32);
0171
0172         edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
0173     }
0174
0175     /* Check if Discard Timer timed out */
0176     edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
0177     if (val32 & INT_CTLR_DTS) {
0178         printk(KERN_INFO "Error(s) in interrupt and control register "
0179             "on %s bridge\n", dev_info->ctl_name);
0180         printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
0181
0182         val32 |= INT_CTLR_DTS;
0183         edac_pci_write_dword(dev, REG_INT_CTLR, val32);
0184
0185         edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
0186     }
0187
0188     /* Check if CRC error happens on link side A */
0189     edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
0190     if (val32 & LNK_CTRL_CRCERR_A) {
0191         printk(KERN_INFO "Error(s) in link conf and control register "
0192             "on %s bridge\n", dev_info->ctl_name);
0193         printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
0194
0195         val32 |= LNK_CTRL_CRCERR_A;
0196         edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
0197
0198         edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
0199     }
0200
0201     /* Check if CRC error happens on link side B */
0202     edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
0203     if (val32 & LNK_CTRL_CRCERR_B) {
0204         printk(KERN_INFO "Error(s) in link conf and control register "
0205             "on %s bridge\n", dev_info->ctl_name);
0206         printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
0207
0208         val32 |= LNK_CTRL_CRCERR_B;
0209         edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
0210
0211         edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
0212     }
0213 }
0214
0215 static struct amd8131_info amd8131_chipset = {
0216     .err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
0217     .devices = amd8131_devices,
0218     .init = amd8131_pcix_init,
0219     .exit = amd8131_pcix_exit,
0220     .check = amd8131_pcix_check,
0221 };
0222
0223 /*
0224  * There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
0225  * so amd8131_probe() would be called by kernel 4 times, with different
0226  * address of pci_dev for each of them each time.
0227  */
0228 static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
0229 {
0230     struct amd8131_dev_info *dev_info;
0231
0232     for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
0233         dev_info++)
0234         if (dev_info->devfn == dev->devfn)
0235             break;
0236
0237     if (dev_info->inst == NO_BRIDGE) /* should never happen */
0238         return -ENODEV;
0239
0240     /*
0241      * We can't call pci_get_device() as we are used to do because
0242      * there are 4 of them but pci_dev_get() instead.
0243      */
0244     dev_info->dev = pci_dev_get(dev);
0245
0246     if (pci_enable_device(dev_info->dev)) {
0247         pci_dev_put(dev_info->dev);
0248         printk(KERN_ERR "failed to enable:"
0249             "vendor %x, device %x, devfn %x, name %s\n",
0250             PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
0251             dev_info->devfn, dev_info->ctl_name);
0252         return -ENODEV;
0253     }
0254
0255     /*
0256      * we do not allocate extra private structure for
0257      * edac_pci_ctl_info, but make use of existing
0258      * one instead.
0259      */
0260     dev_info->edac_idx = edac_pci_alloc_index();
0261     dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
0262     if (!dev_info->edac_dev)
0263         return -ENOMEM;
0264
0265     dev_info->edac_dev->pvt_info = dev_info;
0266     dev_info->edac_dev->dev = &dev_info->dev->dev;
0267     dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
0268     dev_info->edac_dev->ctl_name = dev_info->ctl_name;
0269     dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
0270
0271     if (edac_op_state == EDAC_OPSTATE_POLL)
0272         dev_info->edac_dev->edac_check = amd8131_chipset.check;
0273
0274     if (amd8131_chipset.init)
0275         amd8131_chipset.init(dev_info);
0276
0277     if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
0278         printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
0279             dev_info->ctl_name);
0280         edac_pci_free_ctl_info(dev_info->edac_dev);
0281         return -ENODEV;
0282     }
0283
0284     printk(KERN_INFO "added one device on AMD8131 "
0285         "vendor %x, device %x, devfn %x, name %s\n",
0286         PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
0287         dev_info->devfn, dev_info->ctl_name);
0288
0289     return 0;
0290 }
0291
0292 static void amd8131_remove(struct pci_dev *dev)
0293 {
0294     struct amd8131_dev_info *dev_info;
0295
0296     for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
0297         dev_info++)
0298         if (dev_info->devfn == dev->devfn)
0299             break;
0300
0301     if (dev_info->inst == NO_BRIDGE) /* should never happen */
0302         return;
0303
0304     if (dev_info->edac_dev) {
0305         edac_pci_del_device(dev_info->edac_dev->dev);
0306         edac_pci_free_ctl_info(dev_info->edac_dev);
0307     }
0308
0309     if (amd8131_chipset.exit)
0310         amd8131_chipset.exit(dev_info);
0311
0312     pci_dev_put(dev_info->dev);
0313 }
0314
0315 static const struct pci_device_id amd8131_edac_pci_tbl[] = {
0316     {
0317     PCI_VEND_DEV(AMD, 8131_BRIDGE),
0318     .subvendor = PCI_ANY_ID,
0319     .subdevice = PCI_ANY_ID,
0320     .class = 0,
0321     .class_mask = 0,
0322     .driver_data = 0,
0323     },
0324     {
0325     0,
0326     }           /* table is NULL-terminated */
0327 };
0328 MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
0329
0330 static struct pci_driver amd8131_edac_driver = {
0331     .name = AMD8131_EDAC_MOD_STR,
0332     .probe = amd8131_probe,
0333     .remove = amd8131_remove,
0334     .id_table = amd8131_edac_pci_tbl,
0335 };
0336
0337 static int __init amd8131_edac_init(void)
0338 {
0339     printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
0340     printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
0341
0342     /* Only POLL mode supported so far */
0343     edac_op_state = EDAC_OPSTATE_POLL;
0344
0345     return pci_register_driver(&amd8131_edac_driver);
0346 }
0347
0348 static void __exit amd8131_edac_exit(void)
0349 {
0350     pci_unregister_driver(&amd8131_edac_driver);
0351 }
0352
0353 module_init(amd8131_edac_init);
0354 module_exit(amd8131_edac_exit);
0355
0356 MODULE_LICENSE("GPL");
0357 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
0358 MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");