drivers/edac/amd8111_edac.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * amd8111_edac.h, EDAC defs for AMD8111 hypertransport chip
0004  *
0005  * Copyright (c) 2008 Wind River Systems, Inc.
0006  *
0007  * Authors: Cao Qingtao <qingtao.cao@windriver.com>
0008  *      Benjamin Walsh <benjamin.walsh@windriver.com>
0009  *      Hu Yongqi <yongqi.hu@windriver.com>
0010  */
0011
0012 #ifndef _AMD8111_EDAC_H_
0013 #define _AMD8111_EDAC_H_
0014
0015 /************************************************************
0016  *  PCI Bridge Status and Command Register, DevA:0x04
0017  ************************************************************/
0018 #define REG_PCI_STSCMD  0x04
0019 enum pci_stscmd_bits {
0020     PCI_STSCMD_SSE      = BIT(30),
0021     PCI_STSCMD_RMA      = BIT(29),
0022     PCI_STSCMD_RTA      = BIT(28),
0023     PCI_STSCMD_SERREN   = BIT(8),
0024     PCI_STSCMD_CLEAR_MASK   = (PCI_STSCMD_SSE |
0025                    PCI_STSCMD_RMA |
0026                    PCI_STSCMD_RTA)
0027 };
0028
0029 /************************************************************
0030  *  PCI Bridge Memory Base-Limit Register, DevA:0x1c
0031  ************************************************************/
0032 #define REG_MEM_LIM     0x1c
0033 enum mem_limit_bits {
0034     MEM_LIMIT_DPE   = BIT(31),
0035     MEM_LIMIT_RSE   = BIT(30),
0036     MEM_LIMIT_RMA   = BIT(29),
0037     MEM_LIMIT_RTA   = BIT(28),
0038     MEM_LIMIT_STA   = BIT(27),
0039     MEM_LIMIT_MDPE  = BIT(24),
0040     MEM_LIMIT_CLEAR_MASK  = (MEM_LIMIT_DPE |
0041                  MEM_LIMIT_RSE |
0042                  MEM_LIMIT_RMA |
0043                  MEM_LIMIT_RTA |
0044                  MEM_LIMIT_STA |
0045                  MEM_LIMIT_MDPE)
0046 };
0047
0048 /************************************************************
0049  *  HyperTransport Link Control Register, DevA:0xc4
0050  ************************************************************/
0051 #define REG_HT_LINK 0xc4
0052 enum ht_link_bits {
0053     HT_LINK_LKFAIL  = BIT(4),
0054     HT_LINK_CRCFEN  = BIT(1),
0055     HT_LINK_CLEAR_MASK = (HT_LINK_LKFAIL)
0056 };
0057
0058 /************************************************************
0059  *  PCI Bridge Interrupt and Bridge Control, DevA:0x3c
0060  ************************************************************/
0061 #define REG_PCI_INTBRG_CTRL 0x3c
0062 enum pci_intbrg_ctrl_bits {
0063     PCI_INTBRG_CTRL_DTSERREN    = BIT(27),
0064     PCI_INTBRG_CTRL_DTSTAT      = BIT(26),
0065     PCI_INTBRG_CTRL_MARSP       = BIT(21),
0066     PCI_INTBRG_CTRL_SERREN      = BIT(17),
0067     PCI_INTBRG_CTRL_PEREN       = BIT(16),
0068     PCI_INTBRG_CTRL_CLEAR_MASK  = (PCI_INTBRG_CTRL_DTSTAT),
0069     PCI_INTBRG_CTRL_POLL_MASK   = (PCI_INTBRG_CTRL_DTSERREN |
0070                        PCI_INTBRG_CTRL_MARSP |
0071                        PCI_INTBRG_CTRL_SERREN)
0072 };
0073
0074 /************************************************************
0075  *      I/O Control 1 Register, DevB:0x40
0076  ************************************************************/
0077 #define REG_IO_CTRL_1 0x40
0078 enum io_ctrl_1_bits {
0079     IO_CTRL_1_NMIONERR  = BIT(7),
0080     IO_CTRL_1_LPC_ERR   = BIT(6),
0081     IO_CTRL_1_PW2LPC    = BIT(1),
0082     IO_CTRL_1_CLEAR_MASK    = (IO_CTRL_1_LPC_ERR | IO_CTRL_1_PW2LPC)
0083 };
0084
0085 /************************************************************
0086  *      Legacy I/O Space Registers
0087  ************************************************************/
0088 #define REG_AT_COMPAT 0x61
0089 enum at_compat_bits {
0090     AT_COMPAT_SERR      = BIT(7),
0091     AT_COMPAT_IOCHK     = BIT(6),
0092     AT_COMPAT_CLRIOCHK  = BIT(3),
0093     AT_COMPAT_CLRSERR   = BIT(2),
0094 };
0095
0096 struct amd8111_dev_info {
0097     u16 err_dev;    /* PCI Device ID */
0098     struct pci_dev *dev;
0099     int edac_idx;   /* device index */
0100     char *ctl_name;
0101     struct edac_device_ctl_info *edac_dev;
0102     void (*init)(struct amd8111_dev_info *dev_info);
0103     void (*exit)(struct amd8111_dev_info *dev_info);
0104     void (*check)(struct edac_device_ctl_info *edac_dev);
0105 };
0106
0107 struct amd8111_pci_info {
0108     u16 err_dev;    /* PCI Device ID */
0109     struct pci_dev *dev;
0110     int edac_idx;   /* pci index */
0111     const char *ctl_name;
0112     struct edac_pci_ctl_info *edac_dev;
0113     void (*init)(struct amd8111_pci_info *dev_info);
0114     void (*exit)(struct amd8111_pci_info *dev_info);
0115     void (*check)(struct edac_pci_ctl_info *edac_dev);
0116 };
0117
0118 #endif /* _AMD8111_EDAC_H_ */