0001 #
0002 # EDAC Kconfig
0003 # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
0004 # Licensed and distributed under the GPL
0005
0006 config EDAC_ATOMIC_SCRUB
0007 bool
0008
0009 config EDAC_SUPPORT
0010 bool
0011
0012 menuconfig EDAC
0013 tristate "EDAC (Error Detection And Correction) reporting"
0014 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
0015 help
0016 EDAC is a subsystem along with hardware-specific drivers designed to
0017 report hardware errors. These are low-level errors that are reported
0018 in the CPU or supporting chipset or other subsystems:
0019 memory errors, cache errors, PCI errors, thermal throttling, etc..
0020 If unsure, select 'Y'.
0021
0022 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
0023
0024 if EDAC
0025
0026 config EDAC_LEGACY_SYSFS
0027 bool "EDAC legacy sysfs"
0028 default y
0029 help
0030 Enable the compatibility sysfs nodes.
0031 Use 'Y' if your edac utilities aren't ported to work with the newer
0032 structures.
0033
0034 config EDAC_DEBUG
0035 bool "Debugging"
0036 select DEBUG_FS
0037 help
0038 This turns on debugging information for the entire EDAC subsystem.
0039 You do so by inserting edac_module with "edac_debug_level=x." Valid
0040 levels are 0-4 (from low to high) and by default it is set to 2.
0041 Usually you should select 'N' here.
0042
0043 config EDAC_DECODE_MCE
0044 tristate "Decode MCEs in human-readable form (only on AMD for now)"
0045 depends on CPU_SUP_AMD && X86_MCE_AMD
0046 default y
0047 help
0048 Enable this option if you want to decode Machine Check Exceptions
0049 occurring on your machine in human-readable form.
0050
0051 You should definitely say Y here in case you want to decode MCEs
0052 which occur really early upon boot, before the module infrastructure
0053 has been initialized.
0054
0055 config EDAC_GHES
0056 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
0057 depends on ACPI_APEI_GHES && (EDAC=y)
0058 select UEFI_CPER
0059 help
0060 Not all machines support hardware-driven error report. Some of those
0061 provide a BIOS-driven error report mechanism via ACPI, using the
0062 APEI/GHES driver. By enabling this option, the error reports provided
0063 by GHES are sent to userspace via the EDAC API.
0064
0065 When this option is enabled, it will disable the hardware-driven
0066 mechanisms, if a GHES BIOS is detected, entering into the
0067 "Firmware First" mode.
0068
0069 It should be noticed that keeping both GHES and a hardware-driven
0070 error mechanism won't work well, as BIOS will race with OS, while
0071 reading the error registers. So, if you want to not use "Firmware
0072 first" GHES error mechanism, you should disable GHES either at
0073 compilation time or by passing "ghes.disable=1" Kernel parameter
0074 at boot time.
0075
0076 In doubt, say 'Y'.
0077
0078 config EDAC_AMD64
0079 tristate "AMD64 (Opteron, Athlon64)"
0080 depends on AMD_NB && EDAC_DECODE_MCE
0081 help
0082 Support for error detection and correction of DRAM ECC errors on
0083 the AMD64 families (>= K8) of memory controllers.
0084
0085 When EDAC_DEBUG is enabled, hardware error injection facilities
0086 through sysfs are available:
0087
0088 AMD CPUs up to and excluding family 0x17 provide for Memory
0089 Error Injection into the ECC detection circuits. The amd64_edac
0090 module allows the operator/user to inject Uncorrectable and
0091 Correctable errors into DRAM.
0092
0093 When enabled, in each of the respective memory controller directories
0094 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
0095
0096 - inject_section (0..3, 16-byte section of 64-byte cacheline),
0097 - inject_word (0..8, 16-bit word of 16-byte section),
0098 - inject_ecc_vector (hex ecc vector: select bits of inject word)
0099
0100 In addition, there are two control files, inject_read and inject_write,
0101 which trigger the DRAM ECC Read and Write respectively.
0102
0103 config EDAC_AL_MC
0104 tristate "Amazon's Annapurna Lab Memory Controller"
0105 depends on (ARCH_ALPINE || COMPILE_TEST)
0106 help
0107 Support for error detection and correction for Amazon's Annapurna
0108 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
0109
0110 config EDAC_AMD76X
0111 tristate "AMD 76x (760, 762, 768)"
0112 depends on PCI && X86_32
0113 help
0114 Support for error detection and correction on the AMD 76x
0115 series of chipsets used with the Athlon processor.
0116
0117 config EDAC_E7XXX
0118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
0119 depends on PCI && X86_32
0120 help
0121 Support for error detection and correction on the Intel
0122 E7205, E7500, E7501 and E7505 server chipsets.
0123
0124 config EDAC_E752X
0125 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
0126 depends on PCI && X86
0127 help
0128 Support for error detection and correction on the Intel
0129 E7520, E7525, E7320 server chipsets.
0130
0131 config EDAC_I82443BXGX
0132 tristate "Intel 82443BX/GX (440BX/GX)"
0133 depends on PCI && X86_32
0134 depends on BROKEN
0135 help
0136 Support for error detection and correction on the Intel
0137 82443BX/GX memory controllers (440BX/GX chipsets).
0138
0139 config EDAC_I82875P
0140 tristate "Intel 82875p (D82875P, E7210)"
0141 depends on PCI && X86_32
0142 help
0143 Support for error detection and correction on the Intel
0144 DP82785P and E7210 server chipsets.
0145
0146 config EDAC_I82975X
0147 tristate "Intel 82975x (D82975x)"
0148 depends on PCI && X86
0149 help
0150 Support for error detection and correction on the Intel
0151 DP82975x server chipsets.
0152
0153 config EDAC_I3000
0154 tristate "Intel 3000/3010"
0155 depends on PCI && X86
0156 help
0157 Support for error detection and correction on the Intel
0158 3000 and 3010 server chipsets.
0159
0160 config EDAC_I3200
0161 tristate "Intel 3200"
0162 depends on PCI && X86
0163 help
0164 Support for error detection and correction on the Intel
0165 3200 and 3210 server chipsets.
0166
0167 config EDAC_IE31200
0168 tristate "Intel e312xx"
0169 depends on PCI && X86
0170 help
0171 Support for error detection and correction on the Intel
0172 E3-1200 based DRAM controllers.
0173
0174 config EDAC_X38
0175 tristate "Intel X38"
0176 depends on PCI && X86
0177 help
0178 Support for error detection and correction on the Intel
0179 X38 server chipsets.
0180
0181 config EDAC_I5400
0182 tristate "Intel 5400 (Seaburg) chipsets"
0183 depends on PCI && X86
0184 help
0185 Support for error detection and correction the Intel
0186 i5400 MCH chipset (Seaburg).
0187
0188 config EDAC_I7CORE
0189 tristate "Intel i7 Core (Nehalem) processors"
0190 depends on PCI && X86 && X86_MCE_INTEL
0191 help
0192 Support for error detection and correction the Intel
0193 i7 Core (Nehalem) Integrated Memory Controller that exists on
0194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
0195 and Xeon 55xx processors.
0196
0197 config EDAC_I82860
0198 tristate "Intel 82860"
0199 depends on PCI && X86_32
0200 help
0201 Support for error detection and correction on the Intel
0202 82860 chipset.
0203
0204 config EDAC_R82600
0205 tristate "Radisys 82600 embedded chipset"
0206 depends on PCI && X86_32
0207 help
0208 Support for error detection and correction on the Radisys
0209 82600 embedded chipset.
0210
0211 config EDAC_I5000
0212 tristate "Intel Greencreek/Blackford chipset"
0213 depends on X86 && PCI
0214 help
0215 Support for error detection and correction the Intel
0216 Greekcreek/Blackford chipsets.
0217
0218 config EDAC_I5100
0219 tristate "Intel San Clemente MCH"
0220 depends on X86 && PCI
0221 help
0222 Support for error detection and correction the Intel
0223 San Clemente MCH.
0224
0225 config EDAC_I7300
0226 tristate "Intel Clarksboro MCH"
0227 depends on X86 && PCI
0228 help
0229 Support for error detection and correction the Intel
0230 Clarksboro MCH (Intel 7300 chipset).
0231
0232 config EDAC_SBRIDGE
0233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
0234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
0235 help
0236 Support for error detection and correction the Intel
0237 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
0238
0239 config EDAC_SKX
0240 tristate "Intel Skylake server Integrated MC"
0241 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
0242 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
0243 select DMI
0244 select ACPI_ADXL
0245 help
0246 Support for error detection and correction the Intel
0247 Skylake server Integrated Memory Controllers. If your
0248 system has non-volatile DIMMs you should also manually
0249 select CONFIG_ACPI_NFIT.
0250
0251 config EDAC_I10NM
0252 tristate "Intel 10nm server Integrated MC"
0253 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
0254 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
0255 select DMI
0256 select ACPI_ADXL
0257 help
0258 Support for error detection and correction the Intel
0259 10nm server Integrated Memory Controllers. If your
0260 system has non-volatile DIMMs you should also manually
0261 select CONFIG_ACPI_NFIT.
0262
0263 config EDAC_PND2
0264 tristate "Intel Pondicherry2"
0265 depends on PCI && X86_64 && X86_MCE_INTEL
0266 select P2SB if X86
0267 help
0268 Support for error detection and correction on the Intel
0269 Pondicherry2 Integrated Memory Controller. This SoC IP is
0270 first used on the Apollo Lake platform and Denverton
0271 micro-server but may appear on others in the future.
0272
0273 config EDAC_IGEN6
0274 tristate "Intel client SoC Integrated MC"
0275 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG
0276 depends on X86_64 && X86_MCE_INTEL
0277 help
0278 Support for error detection and correction on the Intel
0279 client SoC Integrated Memory Controller using In-Band ECC IP.
0280 This In-Band ECC is first used on the Elkhart Lake SoC but
0281 may appear on others in the future.
0282
0283 config EDAC_MPC85XX
0284 bool "Freescale MPC83xx / MPC85xx"
0285 depends on FSL_SOC && EDAC=y
0286 help
0287 Support for error detection and correction on the Freescale
0288 MPC8349, MPC8560, MPC8540, MPC8548, T4240
0289
0290 config EDAC_LAYERSCAPE
0291 tristate "Freescale Layerscape DDR"
0292 depends on ARCH_LAYERSCAPE || SOC_LS1021A
0293 help
0294 Support for error detection and correction on Freescale memory
0295 controllers on Layerscape SoCs.
0296
0297 config EDAC_PASEMI
0298 tristate "PA Semi PWRficient"
0299 depends on PPC_PASEMI && PCI
0300 help
0301 Support for error detection and correction on PA Semi
0302 PWRficient.
0303
0304 config EDAC_CELL
0305 tristate "Cell Broadband Engine memory controller"
0306 depends on PPC_CELL_COMMON
0307 help
0308 Support for error detection and correction on the
0309 Cell Broadband Engine internal memory controller
0310 on platform without a hypervisor
0311
0312 config EDAC_PPC4XX
0313 tristate "PPC4xx IBM DDR2 Memory Controller"
0314 depends on 4xx
0315 help
0316 This enables support for EDAC on the ECC memory used
0317 with the IBM DDR2 memory controller found in various
0318 PowerPC 4xx embedded processors such as the 405EX[r],
0319 440SP, 440SPe, 460EX, 460GT and 460SX.
0320
0321 config EDAC_AMD8131
0322 tristate "AMD8131 HyperTransport PCI-X Tunnel"
0323 depends on PCI && PPC_MAPLE
0324 help
0325 Support for error detection and correction on the
0326 AMD8131 HyperTransport PCI-X Tunnel chip.
0327 Note, add more Kconfig dependency if it's adopted
0328 on some machine other than Maple.
0329
0330 config EDAC_AMD8111
0331 tristate "AMD8111 HyperTransport I/O Hub"
0332 depends on PCI && PPC_MAPLE
0333 help
0334 Support for error detection and correction on the
0335 AMD8111 HyperTransport I/O Hub chip.
0336 Note, add more Kconfig dependency if it's adopted
0337 on some machine other than Maple.
0338
0339 config EDAC_CPC925
0340 tristate "IBM CPC925 Memory Controller (PPC970FX)"
0341 depends on PPC64
0342 help
0343 Support for error detection and correction on the
0344 IBM CPC925 Bridge and Memory Controller, which is
0345 a companion chip to the PowerPC 970 family of
0346 processors.
0347
0348 config EDAC_HIGHBANK_MC
0349 tristate "Highbank Memory Controller"
0350 depends on ARCH_HIGHBANK
0351 help
0352 Support for error detection and correction on the
0353 Calxeda Highbank memory controller.
0354
0355 config EDAC_HIGHBANK_L2
0356 tristate "Highbank L2 Cache"
0357 depends on ARCH_HIGHBANK
0358 help
0359 Support for error detection and correction on the
0360 Calxeda Highbank memory controller.
0361
0362 config EDAC_OCTEON_PC
0363 tristate "Cavium Octeon Primary Caches"
0364 depends on CPU_CAVIUM_OCTEON
0365 help
0366 Support for error detection and correction on the primary caches of
0367 the cnMIPS cores of Cavium Octeon family SOCs.
0368
0369 config EDAC_OCTEON_L2C
0370 tristate "Cavium Octeon Secondary Caches (L2C)"
0371 depends on CAVIUM_OCTEON_SOC
0372 help
0373 Support for error detection and correction on the
0374 Cavium Octeon family of SOCs.
0375
0376 config EDAC_OCTEON_LMC
0377 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
0378 depends on CAVIUM_OCTEON_SOC
0379 help
0380 Support for error detection and correction on the
0381 Cavium Octeon family of SOCs.
0382
0383 config EDAC_OCTEON_PCI
0384 tristate "Cavium Octeon PCI Controller"
0385 depends on PCI && CAVIUM_OCTEON_SOC
0386 help
0387 Support for error detection and correction on the
0388 Cavium Octeon family of SOCs.
0389
0390 config EDAC_THUNDERX
0391 tristate "Cavium ThunderX EDAC"
0392 depends on ARM64
0393 depends on PCI
0394 help
0395 Support for error detection and correction on the
0396 Cavium ThunderX memory controllers (LMC), Cache
0397 Coherent Processor Interconnect (CCPI) and L2 cache
0398 blocks (TAD, CBC, MCI).
0399
0400 config EDAC_ALTERA
0401 bool "Altera SOCFPGA ECC"
0402 depends on EDAC=y && ARCH_INTEL_SOCFPGA
0403 help
0404 Support for error detection and correction on the
0405 Altera SOCs. This is the global enable for the
0406 various Altera peripherals.
0407
0408 config EDAC_ALTERA_SDRAM
0409 bool "Altera SDRAM ECC"
0410 depends on EDAC_ALTERA=y
0411 help
0412 Support for error detection and correction on the
0413 Altera SDRAM Memory for Altera SoCs. Note that the
0414 preloader must initialize the SDRAM before loading
0415 the kernel.
0416
0417 config EDAC_ALTERA_L2C
0418 bool "Altera L2 Cache ECC"
0419 depends on EDAC_ALTERA=y && CACHE_L2X0
0420 help
0421 Support for error detection and correction on the
0422 Altera L2 cache Memory for Altera SoCs. This option
0423 requires L2 cache.
0424
0425 config EDAC_ALTERA_OCRAM
0426 bool "Altera On-Chip RAM ECC"
0427 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
0428 help
0429 Support for error detection and correction on the
0430 Altera On-Chip RAM Memory for Altera SoCs.
0431
0432 config EDAC_ALTERA_ETHERNET
0433 bool "Altera Ethernet FIFO ECC"
0434 depends on EDAC_ALTERA=y
0435 help
0436 Support for error detection and correction on the
0437 Altera Ethernet FIFO Memory for Altera SoCs.
0438
0439 config EDAC_ALTERA_NAND
0440 bool "Altera NAND FIFO ECC"
0441 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
0442 help
0443 Support for error detection and correction on the
0444 Altera NAND FIFO Memory for Altera SoCs.
0445
0446 config EDAC_ALTERA_DMA
0447 bool "Altera DMA FIFO ECC"
0448 depends on EDAC_ALTERA=y && PL330_DMA=y
0449 help
0450 Support for error detection and correction on the
0451 Altera DMA FIFO Memory for Altera SoCs.
0452
0453 config EDAC_ALTERA_USB
0454 bool "Altera USB FIFO ECC"
0455 depends on EDAC_ALTERA=y && USB_DWC2
0456 help
0457 Support for error detection and correction on the
0458 Altera USB FIFO Memory for Altera SoCs.
0459
0460 config EDAC_ALTERA_QSPI
0461 bool "Altera QSPI FIFO ECC"
0462 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
0463 help
0464 Support for error detection and correction on the
0465 Altera QSPI FIFO Memory for Altera SoCs.
0466
0467 config EDAC_ALTERA_SDMMC
0468 bool "Altera SDMMC FIFO ECC"
0469 depends on EDAC_ALTERA=y && MMC_DW
0470 help
0471 Support for error detection and correction on the
0472 Altera SDMMC FIFO Memory for Altera SoCs.
0473
0474 config EDAC_SIFIVE
0475 bool "Sifive platform EDAC driver"
0476 depends on EDAC=y && SIFIVE_L2
0477 help
0478 Support for error detection and correction on the SiFive SoCs.
0479
0480 config EDAC_ARMADA_XP
0481 bool "Marvell Armada XP DDR and L2 Cache ECC"
0482 depends on MACH_MVEBU_V7
0483 help
0484 Support for error correction and detection on the Marvell Aramada XP
0485 DDR RAM and L2 cache controllers.
0486
0487 config EDAC_SYNOPSYS
0488 tristate "Synopsys DDR Memory Controller"
0489 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC
0490 help
0491 Support for error detection and correction on the Synopsys DDR
0492 memory controller.
0493
0494 config EDAC_XGENE
0495 tristate "APM X-Gene SoC"
0496 depends on (ARM64 || COMPILE_TEST)
0497 help
0498 Support for error detection and correction on the
0499 APM X-Gene family of SOCs.
0500
0501 config EDAC_TI
0502 tristate "Texas Instruments DDR3 ECC Controller"
0503 depends on ARCH_KEYSTONE || SOC_DRA7XX
0504 help
0505 Support for error detection and correction on the TI SoCs.
0506
0507 config EDAC_QCOM
0508 tristate "QCOM EDAC Controller"
0509 depends on ARCH_QCOM && QCOM_LLCC
0510 help
0511 Support for error detection and correction on the
0512 Qualcomm Technologies, Inc. SoCs.
0513
0514 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
0515 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
0516 of Tag RAM and Data RAM.
0517
0518 For debugging issues having to do with stability and overall system
0519 health, you should probably say 'Y' here.
0520
0521 config EDAC_ASPEED
0522 tristate "Aspeed AST BMC SoC"
0523 depends on ARCH_ASPEED
0524 help
0525 Support for error detection and correction on the Aspeed AST BMC SoC.
0526
0527 First, ECC must be configured in the bootloader. Then, this driver
0528 will expose error counters via the EDAC kernel framework.
0529
0530 config EDAC_BLUEFIELD
0531 tristate "Mellanox BlueField Memory ECC"
0532 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
0533 help
0534 Support for error detection and correction on the
0535 Mellanox BlueField SoCs.
0536
0537 config EDAC_DMC520
0538 tristate "ARM DMC-520 ECC"
0539 depends on ARM64
0540 help
0541 Support for error detection and correction on the
0542 SoCs with ARM DMC-520 DRAM controller.
0543
0544 endif # EDAC
