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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the TXx9 SoC DMA Controller
0004  *
0005  * Copyright (C) 2009 Atsushi Nemoto
0006  */
0007 #include <linux/dma-mapping.h>
0008 #include <linux/init.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/slab.h>
0014 #include <linux/scatterlist.h>
0015 
0016 #include "dmaengine.h"
0017 #include "txx9dmac.h"
0018 
0019 static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
0020 {
0021     return container_of(chan, struct txx9dmac_chan, chan);
0022 }
0023 
0024 static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
0025 {
0026     return dc->ch_regs;
0027 }
0028 
0029 static struct txx9dmac_cregs32 __iomem *__dma_regs32(
0030     const struct txx9dmac_chan *dc)
0031 {
0032     return dc->ch_regs;
0033 }
0034 
0035 #define channel64_readq(dc, name) \
0036     __raw_readq(&(__dma_regs(dc)->name))
0037 #define channel64_writeq(dc, name, val) \
0038     __raw_writeq((val), &(__dma_regs(dc)->name))
0039 #define channel64_readl(dc, name) \
0040     __raw_readl(&(__dma_regs(dc)->name))
0041 #define channel64_writel(dc, name, val) \
0042     __raw_writel((val), &(__dma_regs(dc)->name))
0043 
0044 #define channel32_readl(dc, name) \
0045     __raw_readl(&(__dma_regs32(dc)->name))
0046 #define channel32_writel(dc, name, val) \
0047     __raw_writel((val), &(__dma_regs32(dc)->name))
0048 
0049 #define channel_readq(dc, name) channel64_readq(dc, name)
0050 #define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
0051 #define channel_readl(dc, name) \
0052     (is_dmac64(dc) ? \
0053      channel64_readl(dc, name) : channel32_readl(dc, name))
0054 #define channel_writel(dc, name, val) \
0055     (is_dmac64(dc) ? \
0056      channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
0057 
0058 static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
0059 {
0060     if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
0061         return channel64_readq(dc, CHAR);
0062     else
0063         return channel64_readl(dc, CHAR);
0064 }
0065 
0066 static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
0067 {
0068     if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
0069         channel64_writeq(dc, CHAR, val);
0070     else
0071         channel64_writel(dc, CHAR, val);
0072 }
0073 
0074 static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
0075 {
0076 #if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
0077     channel64_writel(dc, CHAR, 0);
0078     channel64_writel(dc, __pad_CHAR, 0);
0079 #else
0080     channel64_writeq(dc, CHAR, 0);
0081 #endif
0082 }
0083 
0084 static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
0085 {
0086     if (is_dmac64(dc))
0087         return channel64_read_CHAR(dc);
0088     else
0089         return channel32_readl(dc, CHAR);
0090 }
0091 
0092 static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
0093 {
0094     if (is_dmac64(dc))
0095         channel64_write_CHAR(dc, val);
0096     else
0097         channel32_writel(dc, CHAR, val);
0098 }
0099 
0100 static struct txx9dmac_regs __iomem *__txx9dmac_regs(
0101     const struct txx9dmac_dev *ddev)
0102 {
0103     return ddev->regs;
0104 }
0105 
0106 static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
0107     const struct txx9dmac_dev *ddev)
0108 {
0109     return ddev->regs;
0110 }
0111 
0112 #define dma64_readl(ddev, name) \
0113     __raw_readl(&(__txx9dmac_regs(ddev)->name))
0114 #define dma64_writel(ddev, name, val) \
0115     __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
0116 
0117 #define dma32_readl(ddev, name) \
0118     __raw_readl(&(__txx9dmac_regs32(ddev)->name))
0119 #define dma32_writel(ddev, name, val) \
0120     __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
0121 
0122 #define dma_readl(ddev, name) \
0123     (__is_dmac64(ddev) ? \
0124     dma64_readl(ddev, name) : dma32_readl(ddev, name))
0125 #define dma_writel(ddev, name, val) \
0126     (__is_dmac64(ddev) ? \
0127     dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
0128 
0129 static struct device *chan2dev(struct dma_chan *chan)
0130 {
0131     return &chan->dev->device;
0132 }
0133 static struct device *chan2parent(struct dma_chan *chan)
0134 {
0135     return chan->dev->device.parent;
0136 }
0137 
0138 static struct txx9dmac_desc *
0139 txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
0140 {
0141     return container_of(txd, struct txx9dmac_desc, txd);
0142 }
0143 
0144 static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
0145                  const struct txx9dmac_desc *desc)
0146 {
0147     return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
0148 }
0149 
0150 static void desc_write_CHAR(const struct txx9dmac_chan *dc,
0151                 struct txx9dmac_desc *desc, dma_addr_t val)
0152 {
0153     if (is_dmac64(dc))
0154         desc->hwdesc.CHAR = val;
0155     else
0156         desc->hwdesc32.CHAR = val;
0157 }
0158 
0159 #define TXX9_DMA_MAX_COUNT  0x04000000
0160 
0161 #define TXX9_DMA_INITIAL_DESC_COUNT 64
0162 
0163 static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
0164 {
0165     return list_entry(dc->active_list.next,
0166               struct txx9dmac_desc, desc_node);
0167 }
0168 
0169 static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
0170 {
0171     return list_entry(dc->active_list.prev,
0172               struct txx9dmac_desc, desc_node);
0173 }
0174 
0175 static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
0176 {
0177     return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
0178 }
0179 
0180 static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
0181 {
0182     if (!list_empty(&desc->tx_list))
0183         desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
0184     return desc;
0185 }
0186 
0187 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
0188 
0189 static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
0190                          gfp_t flags)
0191 {
0192     struct txx9dmac_dev *ddev = dc->ddev;
0193     struct txx9dmac_desc *desc;
0194 
0195     desc = kzalloc(sizeof(*desc), flags);
0196     if (!desc)
0197         return NULL;
0198     INIT_LIST_HEAD(&desc->tx_list);
0199     dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
0200     desc->txd.tx_submit = txx9dmac_tx_submit;
0201     /* txd.flags will be overwritten in prep funcs */
0202     desc->txd.flags = DMA_CTRL_ACK;
0203     desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
0204                     ddev->descsize, DMA_TO_DEVICE);
0205     return desc;
0206 }
0207 
0208 static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
0209 {
0210     struct txx9dmac_desc *desc, *_desc;
0211     struct txx9dmac_desc *ret = NULL;
0212     unsigned int i = 0;
0213 
0214     spin_lock_bh(&dc->lock);
0215     list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
0216         if (async_tx_test_ack(&desc->txd)) {
0217             list_del(&desc->desc_node);
0218             ret = desc;
0219             break;
0220         }
0221         dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
0222         i++;
0223     }
0224     spin_unlock_bh(&dc->lock);
0225 
0226     dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
0227          i);
0228     if (!ret) {
0229         ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
0230         if (ret) {
0231             spin_lock_bh(&dc->lock);
0232             dc->descs_allocated++;
0233             spin_unlock_bh(&dc->lock);
0234         } else
0235             dev_err(chan2dev(&dc->chan),
0236                 "not enough descriptors available\n");
0237     }
0238     return ret;
0239 }
0240 
0241 static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
0242                        struct txx9dmac_desc *desc)
0243 {
0244     struct txx9dmac_dev *ddev = dc->ddev;
0245     struct txx9dmac_desc *child;
0246 
0247     list_for_each_entry(child, &desc->tx_list, desc_node)
0248         dma_sync_single_for_cpu(chan2parent(&dc->chan),
0249                 child->txd.phys, ddev->descsize,
0250                 DMA_TO_DEVICE);
0251     dma_sync_single_for_cpu(chan2parent(&dc->chan),
0252             desc->txd.phys, ddev->descsize,
0253             DMA_TO_DEVICE);
0254 }
0255 
0256 /*
0257  * Move a descriptor, including any children, to the free list.
0258  * `desc' must not be on any lists.
0259  */
0260 static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
0261                   struct txx9dmac_desc *desc)
0262 {
0263     if (desc) {
0264         struct txx9dmac_desc *child;
0265 
0266         txx9dmac_sync_desc_for_cpu(dc, desc);
0267 
0268         spin_lock_bh(&dc->lock);
0269         list_for_each_entry(child, &desc->tx_list, desc_node)
0270             dev_vdbg(chan2dev(&dc->chan),
0271                  "moving child desc %p to freelist\n",
0272                  child);
0273         list_splice_init(&desc->tx_list, &dc->free_list);
0274         dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
0275              desc);
0276         list_add(&desc->desc_node, &dc->free_list);
0277         spin_unlock_bh(&dc->lock);
0278     }
0279 }
0280 
0281 /*----------------------------------------------------------------------*/
0282 
0283 static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
0284 {
0285     if (is_dmac64(dc))
0286         dev_err(chan2dev(&dc->chan),
0287             "  CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
0288             " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
0289             (u64)channel64_read_CHAR(dc),
0290             channel64_readq(dc, SAR),
0291             channel64_readq(dc, DAR),
0292             channel64_readl(dc, CNTR),
0293             channel64_readl(dc, SAIR),
0294             channel64_readl(dc, DAIR),
0295             channel64_readl(dc, CCR),
0296             channel64_readl(dc, CSR));
0297     else
0298         dev_err(chan2dev(&dc->chan),
0299             "  CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
0300             " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
0301             channel32_readl(dc, CHAR),
0302             channel32_readl(dc, SAR),
0303             channel32_readl(dc, DAR),
0304             channel32_readl(dc, CNTR),
0305             channel32_readl(dc, SAIR),
0306             channel32_readl(dc, DAIR),
0307             channel32_readl(dc, CCR),
0308             channel32_readl(dc, CSR));
0309 }
0310 
0311 static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
0312 {
0313     channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
0314     if (is_dmac64(dc)) {
0315         channel64_clear_CHAR(dc);
0316         channel_writeq(dc, SAR, 0);
0317         channel_writeq(dc, DAR, 0);
0318     } else {
0319         channel_writel(dc, CHAR, 0);
0320         channel_writel(dc, SAR, 0);
0321         channel_writel(dc, DAR, 0);
0322     }
0323     channel_writel(dc, CNTR, 0);
0324     channel_writel(dc, SAIR, 0);
0325     channel_writel(dc, DAIR, 0);
0326     channel_writel(dc, CCR, 0);
0327 }
0328 
0329 /* Called with dc->lock held and bh disabled */
0330 static void txx9dmac_dostart(struct txx9dmac_chan *dc,
0331                  struct txx9dmac_desc *first)
0332 {
0333     struct txx9dmac_slave *ds = dc->chan.private;
0334     u32 sai, dai;
0335 
0336     dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
0337          first->txd.cookie, first);
0338     /* ASSERT:  channel is idle */
0339     if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
0340         dev_err(chan2dev(&dc->chan),
0341             "BUG: Attempted to start non-idle channel\n");
0342         txx9dmac_dump_regs(dc);
0343         /* The tasklet will hopefully advance the queue... */
0344         return;
0345     }
0346 
0347     if (is_dmac64(dc)) {
0348         channel64_writel(dc, CNTR, 0);
0349         channel64_writel(dc, CSR, 0xffffffff);
0350         if (ds) {
0351             if (ds->tx_reg) {
0352                 sai = ds->reg_width;
0353                 dai = 0;
0354             } else {
0355                 sai = 0;
0356                 dai = ds->reg_width;
0357             }
0358         } else {
0359             sai = 8;
0360             dai = 8;
0361         }
0362         channel64_writel(dc, SAIR, sai);
0363         channel64_writel(dc, DAIR, dai);
0364         /* All 64-bit DMAC supports SMPCHN */
0365         channel64_writel(dc, CCR, dc->ccr);
0366         /* Writing a non zero value to CHAR will assert XFACT */
0367         channel64_write_CHAR(dc, first->txd.phys);
0368     } else {
0369         channel32_writel(dc, CNTR, 0);
0370         channel32_writel(dc, CSR, 0xffffffff);
0371         if (ds) {
0372             if (ds->tx_reg) {
0373                 sai = ds->reg_width;
0374                 dai = 0;
0375             } else {
0376                 sai = 0;
0377                 dai = ds->reg_width;
0378             }
0379         } else {
0380             sai = 4;
0381             dai = 4;
0382         }
0383         channel32_writel(dc, SAIR, sai);
0384         channel32_writel(dc, DAIR, dai);
0385         if (txx9_dma_have_SMPCHN()) {
0386             channel32_writel(dc, CCR, dc->ccr);
0387             /* Writing a non zero value to CHAR will assert XFACT */
0388             channel32_writel(dc, CHAR, first->txd.phys);
0389         } else {
0390             channel32_writel(dc, CHAR, first->txd.phys);
0391             channel32_writel(dc, CCR, dc->ccr);
0392         }
0393     }
0394 }
0395 
0396 /*----------------------------------------------------------------------*/
0397 
0398 static void
0399 txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
0400                  struct txx9dmac_desc *desc)
0401 {
0402     struct dmaengine_desc_callback cb;
0403     struct dma_async_tx_descriptor *txd = &desc->txd;
0404 
0405     dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
0406          txd->cookie, desc);
0407 
0408     dma_cookie_complete(txd);
0409     dmaengine_desc_get_callback(txd, &cb);
0410 
0411     txx9dmac_sync_desc_for_cpu(dc, desc);
0412     list_splice_init(&desc->tx_list, &dc->free_list);
0413     list_move(&desc->desc_node, &dc->free_list);
0414 
0415     dma_descriptor_unmap(txd);
0416     /*
0417      * The API requires that no submissions are done from a
0418      * callback, so we don't need to drop the lock here
0419      */
0420     dmaengine_desc_callback_invoke(&cb, NULL);
0421     dma_run_dependencies(txd);
0422 }
0423 
0424 static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
0425 {
0426     struct txx9dmac_dev *ddev = dc->ddev;
0427     struct txx9dmac_desc *desc;
0428     struct txx9dmac_desc *prev = NULL;
0429 
0430     BUG_ON(!list_empty(list));
0431     do {
0432         desc = txx9dmac_first_queued(dc);
0433         if (prev) {
0434             desc_write_CHAR(dc, prev, desc->txd.phys);
0435             dma_sync_single_for_device(chan2parent(&dc->chan),
0436                 prev->txd.phys, ddev->descsize,
0437                 DMA_TO_DEVICE);
0438         }
0439         prev = txx9dmac_last_child(desc);
0440         list_move_tail(&desc->desc_node, list);
0441         /* Make chain-completion interrupt happen */
0442         if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
0443             !txx9dmac_chan_INTENT(dc))
0444             break;
0445     } while (!list_empty(&dc->queue));
0446 }
0447 
0448 static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
0449 {
0450     struct txx9dmac_desc *desc, *_desc;
0451     LIST_HEAD(list);
0452 
0453     /*
0454      * Submit queued descriptors ASAP, i.e. before we go through
0455      * the completed ones.
0456      */
0457     list_splice_init(&dc->active_list, &list);
0458     if (!list_empty(&dc->queue)) {
0459         txx9dmac_dequeue(dc, &dc->active_list);
0460         txx9dmac_dostart(dc, txx9dmac_first_active(dc));
0461     }
0462 
0463     list_for_each_entry_safe(desc, _desc, &list, desc_node)
0464         txx9dmac_descriptor_complete(dc, desc);
0465 }
0466 
0467 static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
0468                    struct txx9dmac_hwdesc *desc)
0469 {
0470     if (is_dmac64(dc)) {
0471 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
0472         dev_crit(chan2dev(&dc->chan),
0473              "  desc: ch%#llx s%#llx d%#llx c%#x\n",
0474              (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
0475 #else
0476         dev_crit(chan2dev(&dc->chan),
0477              "  desc: ch%#llx s%#llx d%#llx c%#x"
0478              " si%#x di%#x cc%#x cs%#x\n",
0479              (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
0480              desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
0481 #endif
0482     } else {
0483         struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
0484 #ifdef TXX9_DMA_USE_SIMPLE_CHAIN
0485         dev_crit(chan2dev(&dc->chan),
0486              "  desc: ch%#x s%#x d%#x c%#x\n",
0487              d->CHAR, d->SAR, d->DAR, d->CNTR);
0488 #else
0489         dev_crit(chan2dev(&dc->chan),
0490              "  desc: ch%#x s%#x d%#x c%#x"
0491              " si%#x di%#x cc%#x cs%#x\n",
0492              d->CHAR, d->SAR, d->DAR, d->CNTR,
0493              d->SAIR, d->DAIR, d->CCR, d->CSR);
0494 #endif
0495     }
0496 }
0497 
0498 static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
0499 {
0500     struct txx9dmac_desc *bad_desc;
0501     struct txx9dmac_desc *child;
0502     u32 errors;
0503 
0504     /*
0505      * The descriptor currently at the head of the active list is
0506      * borked. Since we don't have any way to report errors, we'll
0507      * just have to scream loudly and try to carry on.
0508      */
0509     dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
0510     txx9dmac_dump_regs(dc);
0511 
0512     bad_desc = txx9dmac_first_active(dc);
0513     list_del_init(&bad_desc->desc_node);
0514 
0515     /* Clear all error flags and try to restart the controller */
0516     errors = csr & (TXX9_DMA_CSR_ABCHC |
0517             TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
0518             TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
0519     channel_writel(dc, CSR, errors);
0520 
0521     if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
0522         txx9dmac_dequeue(dc, &dc->active_list);
0523     if (!list_empty(&dc->active_list))
0524         txx9dmac_dostart(dc, txx9dmac_first_active(dc));
0525 
0526     dev_crit(chan2dev(&dc->chan),
0527          "Bad descriptor submitted for DMA! (cookie: %d)\n",
0528          bad_desc->txd.cookie);
0529     txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
0530     list_for_each_entry(child, &bad_desc->tx_list, desc_node)
0531         txx9dmac_dump_desc(dc, &child->hwdesc);
0532     /* Pretend the descriptor completed successfully */
0533     txx9dmac_descriptor_complete(dc, bad_desc);
0534 }
0535 
0536 static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
0537 {
0538     dma_addr_t chain;
0539     struct txx9dmac_desc *desc, *_desc;
0540     struct txx9dmac_desc *child;
0541     u32 csr;
0542 
0543     if (is_dmac64(dc)) {
0544         chain = channel64_read_CHAR(dc);
0545         csr = channel64_readl(dc, CSR);
0546         channel64_writel(dc, CSR, csr);
0547     } else {
0548         chain = channel32_readl(dc, CHAR);
0549         csr = channel32_readl(dc, CSR);
0550         channel32_writel(dc, CSR, csr);
0551     }
0552     /* For dynamic chain, we should look at XFACT instead of NCHNC */
0553     if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
0554         /* Everything we've submitted is done */
0555         txx9dmac_complete_all(dc);
0556         return;
0557     }
0558     if (!(csr & TXX9_DMA_CSR_CHNEN))
0559         chain = 0;  /* last descriptor of this chain */
0560 
0561     dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
0562          (u64)chain);
0563 
0564     list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
0565         if (desc_read_CHAR(dc, desc) == chain) {
0566             /* This one is currently in progress */
0567             if (csr & TXX9_DMA_CSR_ABCHC)
0568                 goto scan_done;
0569             return;
0570         }
0571 
0572         list_for_each_entry(child, &desc->tx_list, desc_node)
0573             if (desc_read_CHAR(dc, child) == chain) {
0574                 /* Currently in progress */
0575                 if (csr & TXX9_DMA_CSR_ABCHC)
0576                     goto scan_done;
0577                 return;
0578             }
0579 
0580         /*
0581          * No descriptors so far seem to be in progress, i.e.
0582          * this one must be done.
0583          */
0584         txx9dmac_descriptor_complete(dc, desc);
0585     }
0586 scan_done:
0587     if (csr & TXX9_DMA_CSR_ABCHC) {
0588         txx9dmac_handle_error(dc, csr);
0589         return;
0590     }
0591 
0592     dev_err(chan2dev(&dc->chan),
0593         "BUG: All descriptors done, but channel not idle!\n");
0594 
0595     /* Try to continue after resetting the channel... */
0596     txx9dmac_reset_chan(dc);
0597 
0598     if (!list_empty(&dc->queue)) {
0599         txx9dmac_dequeue(dc, &dc->active_list);
0600         txx9dmac_dostart(dc, txx9dmac_first_active(dc));
0601     }
0602 }
0603 
0604 static void txx9dmac_chan_tasklet(struct tasklet_struct *t)
0605 {
0606     int irq;
0607     u32 csr;
0608     struct txx9dmac_chan *dc;
0609 
0610     dc = from_tasklet(dc, t, tasklet);
0611     csr = channel_readl(dc, CSR);
0612     dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
0613 
0614     spin_lock(&dc->lock);
0615     if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
0616            TXX9_DMA_CSR_NTRNFC))
0617         txx9dmac_scan_descriptors(dc);
0618     spin_unlock(&dc->lock);
0619     irq = dc->irq;
0620 
0621     enable_irq(irq);
0622 }
0623 
0624 static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
0625 {
0626     struct txx9dmac_chan *dc = dev_id;
0627 
0628     dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
0629             channel_readl(dc, CSR));
0630 
0631     tasklet_schedule(&dc->tasklet);
0632     /*
0633      * Just disable the interrupts. We'll turn them back on in the
0634      * softirq handler.
0635      */
0636     disable_irq_nosync(irq);
0637 
0638     return IRQ_HANDLED;
0639 }
0640 
0641 static void txx9dmac_tasklet(struct tasklet_struct *t)
0642 {
0643     int irq;
0644     u32 csr;
0645     struct txx9dmac_chan *dc;
0646 
0647     struct txx9dmac_dev *ddev = from_tasklet(ddev, t, tasklet);
0648     u32 mcr;
0649     int i;
0650 
0651     mcr = dma_readl(ddev, MCR);
0652     dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
0653     for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
0654         if ((mcr >> (24 + i)) & 0x11) {
0655             dc = ddev->chan[i];
0656             csr = channel_readl(dc, CSR);
0657             dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
0658                  csr);
0659             spin_lock(&dc->lock);
0660             if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
0661                    TXX9_DMA_CSR_NTRNFC))
0662                 txx9dmac_scan_descriptors(dc);
0663             spin_unlock(&dc->lock);
0664         }
0665     }
0666     irq = ddev->irq;
0667 
0668     enable_irq(irq);
0669 }
0670 
0671 static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
0672 {
0673     struct txx9dmac_dev *ddev = dev_id;
0674 
0675     dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
0676             dma_readl(ddev, MCR));
0677 
0678     tasklet_schedule(&ddev->tasklet);
0679     /*
0680      * Just disable the interrupts. We'll turn them back on in the
0681      * softirq handler.
0682      */
0683     disable_irq_nosync(irq);
0684 
0685     return IRQ_HANDLED;
0686 }
0687 
0688 /*----------------------------------------------------------------------*/
0689 
0690 static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
0691 {
0692     struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
0693     struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
0694     dma_cookie_t cookie;
0695 
0696     spin_lock_bh(&dc->lock);
0697     cookie = dma_cookie_assign(tx);
0698 
0699     dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
0700          desc->txd.cookie, desc);
0701 
0702     list_add_tail(&desc->desc_node, &dc->queue);
0703     spin_unlock_bh(&dc->lock);
0704 
0705     return cookie;
0706 }
0707 
0708 static struct dma_async_tx_descriptor *
0709 txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
0710         size_t len, unsigned long flags)
0711 {
0712     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0713     struct txx9dmac_dev *ddev = dc->ddev;
0714     struct txx9dmac_desc *desc;
0715     struct txx9dmac_desc *first;
0716     struct txx9dmac_desc *prev;
0717     size_t xfer_count;
0718     size_t offset;
0719 
0720     dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
0721          (u64)dest, (u64)src, len, flags);
0722 
0723     if (unlikely(!len)) {
0724         dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
0725         return NULL;
0726     }
0727 
0728     prev = first = NULL;
0729 
0730     for (offset = 0; offset < len; offset += xfer_count) {
0731         xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
0732         /*
0733          * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
0734          * ERT-TX49H4-016 (slightly conservative)
0735          */
0736         if (__is_dmac64(ddev)) {
0737             if (xfer_count > 0x100 &&
0738                 (xfer_count & 0xff) >= 0xfa &&
0739                 (xfer_count & 0xff) <= 0xff)
0740                 xfer_count -= 0x20;
0741         } else {
0742             if (xfer_count > 0x80 &&
0743                 (xfer_count & 0x7f) >= 0x7e &&
0744                 (xfer_count & 0x7f) <= 0x7f)
0745                 xfer_count -= 0x20;
0746         }
0747 
0748         desc = txx9dmac_desc_get(dc);
0749         if (!desc) {
0750             txx9dmac_desc_put(dc, first);
0751             return NULL;
0752         }
0753 
0754         if (__is_dmac64(ddev)) {
0755             desc->hwdesc.SAR = src + offset;
0756             desc->hwdesc.DAR = dest + offset;
0757             desc->hwdesc.CNTR = xfer_count;
0758             txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
0759                     dc->ccr | TXX9_DMA_CCR_XFACT);
0760         } else {
0761             desc->hwdesc32.SAR = src + offset;
0762             desc->hwdesc32.DAR = dest + offset;
0763             desc->hwdesc32.CNTR = xfer_count;
0764             txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
0765                     dc->ccr | TXX9_DMA_CCR_XFACT);
0766         }
0767 
0768         /*
0769          * The descriptors on tx_list are not reachable from
0770          * the dc->queue list or dc->active_list after a
0771          * submit.  If we put all descriptors on active_list,
0772          * calling of callback on the completion will be more
0773          * complex.
0774          */
0775         if (!first) {
0776             first = desc;
0777         } else {
0778             desc_write_CHAR(dc, prev, desc->txd.phys);
0779             dma_sync_single_for_device(chan2parent(&dc->chan),
0780                     prev->txd.phys, ddev->descsize,
0781                     DMA_TO_DEVICE);
0782             list_add_tail(&desc->desc_node, &first->tx_list);
0783         }
0784         prev = desc;
0785     }
0786 
0787     /* Trigger interrupt after last block */
0788     if (flags & DMA_PREP_INTERRUPT)
0789         txx9dmac_desc_set_INTENT(ddev, prev);
0790 
0791     desc_write_CHAR(dc, prev, 0);
0792     dma_sync_single_for_device(chan2parent(&dc->chan),
0793             prev->txd.phys, ddev->descsize,
0794             DMA_TO_DEVICE);
0795 
0796     first->txd.flags = flags;
0797     first->len = len;
0798 
0799     return &first->txd;
0800 }
0801 
0802 static struct dma_async_tx_descriptor *
0803 txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
0804         unsigned int sg_len, enum dma_transfer_direction direction,
0805         unsigned long flags, void *context)
0806 {
0807     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0808     struct txx9dmac_dev *ddev = dc->ddev;
0809     struct txx9dmac_slave *ds = chan->private;
0810     struct txx9dmac_desc *prev;
0811     struct txx9dmac_desc *first;
0812     unsigned int i;
0813     struct scatterlist *sg;
0814 
0815     dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
0816 
0817     BUG_ON(!ds || !ds->reg_width);
0818     if (ds->tx_reg)
0819         BUG_ON(direction != DMA_MEM_TO_DEV);
0820     else
0821         BUG_ON(direction != DMA_DEV_TO_MEM);
0822     if (unlikely(!sg_len))
0823         return NULL;
0824 
0825     prev = first = NULL;
0826 
0827     for_each_sg(sgl, sg, sg_len, i) {
0828         struct txx9dmac_desc *desc;
0829         dma_addr_t mem;
0830         u32 sai, dai;
0831 
0832         desc = txx9dmac_desc_get(dc);
0833         if (!desc) {
0834             txx9dmac_desc_put(dc, first);
0835             return NULL;
0836         }
0837 
0838         mem = sg_dma_address(sg);
0839 
0840         if (__is_dmac64(ddev)) {
0841             if (direction == DMA_MEM_TO_DEV) {
0842                 desc->hwdesc.SAR = mem;
0843                 desc->hwdesc.DAR = ds->tx_reg;
0844             } else {
0845                 desc->hwdesc.SAR = ds->rx_reg;
0846                 desc->hwdesc.DAR = mem;
0847             }
0848             desc->hwdesc.CNTR = sg_dma_len(sg);
0849         } else {
0850             if (direction == DMA_MEM_TO_DEV) {
0851                 desc->hwdesc32.SAR = mem;
0852                 desc->hwdesc32.DAR = ds->tx_reg;
0853             } else {
0854                 desc->hwdesc32.SAR = ds->rx_reg;
0855                 desc->hwdesc32.DAR = mem;
0856             }
0857             desc->hwdesc32.CNTR = sg_dma_len(sg);
0858         }
0859         if (direction == DMA_MEM_TO_DEV) {
0860             sai = ds->reg_width;
0861             dai = 0;
0862         } else {
0863             sai = 0;
0864             dai = ds->reg_width;
0865         }
0866         txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
0867                     dc->ccr | TXX9_DMA_CCR_XFACT);
0868 
0869         if (!first) {
0870             first = desc;
0871         } else {
0872             desc_write_CHAR(dc, prev, desc->txd.phys);
0873             dma_sync_single_for_device(chan2parent(&dc->chan),
0874                     prev->txd.phys,
0875                     ddev->descsize,
0876                     DMA_TO_DEVICE);
0877             list_add_tail(&desc->desc_node, &first->tx_list);
0878         }
0879         prev = desc;
0880     }
0881 
0882     /* Trigger interrupt after last block */
0883     if (flags & DMA_PREP_INTERRUPT)
0884         txx9dmac_desc_set_INTENT(ddev, prev);
0885 
0886     desc_write_CHAR(dc, prev, 0);
0887     dma_sync_single_for_device(chan2parent(&dc->chan),
0888             prev->txd.phys, ddev->descsize,
0889             DMA_TO_DEVICE);
0890 
0891     first->txd.flags = flags;
0892     first->len = 0;
0893 
0894     return &first->txd;
0895 }
0896 
0897 static int txx9dmac_terminate_all(struct dma_chan *chan)
0898 {
0899     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0900     struct txx9dmac_desc *desc, *_desc;
0901     LIST_HEAD(list);
0902 
0903     dev_vdbg(chan2dev(chan), "terminate_all\n");
0904     spin_lock_bh(&dc->lock);
0905 
0906     txx9dmac_reset_chan(dc);
0907 
0908     /* active_list entries will end up before queued entries */
0909     list_splice_init(&dc->queue, &list);
0910     list_splice_init(&dc->active_list, &list);
0911 
0912     spin_unlock_bh(&dc->lock);
0913 
0914     /* Flush all pending and queued descriptors */
0915     list_for_each_entry_safe(desc, _desc, &list, desc_node)
0916         txx9dmac_descriptor_complete(dc, desc);
0917 
0918     return 0;
0919 }
0920 
0921 static enum dma_status
0922 txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
0923            struct dma_tx_state *txstate)
0924 {
0925     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0926     enum dma_status ret;
0927 
0928     ret = dma_cookie_status(chan, cookie, txstate);
0929     if (ret == DMA_COMPLETE)
0930         return DMA_COMPLETE;
0931 
0932     spin_lock_bh(&dc->lock);
0933     txx9dmac_scan_descriptors(dc);
0934     spin_unlock_bh(&dc->lock);
0935 
0936     return dma_cookie_status(chan, cookie, txstate);
0937 }
0938 
0939 static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
0940                    struct txx9dmac_desc *prev)
0941 {
0942     struct txx9dmac_dev *ddev = dc->ddev;
0943     struct txx9dmac_desc *desc;
0944     LIST_HEAD(list);
0945 
0946     prev = txx9dmac_last_child(prev);
0947     txx9dmac_dequeue(dc, &list);
0948     desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
0949     desc_write_CHAR(dc, prev, desc->txd.phys);
0950     dma_sync_single_for_device(chan2parent(&dc->chan),
0951                    prev->txd.phys, ddev->descsize,
0952                    DMA_TO_DEVICE);
0953     if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
0954         channel_read_CHAR(dc) == prev->txd.phys)
0955         /* Restart chain DMA */
0956         channel_write_CHAR(dc, desc->txd.phys);
0957     list_splice_tail(&list, &dc->active_list);
0958 }
0959 
0960 static void txx9dmac_issue_pending(struct dma_chan *chan)
0961 {
0962     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0963 
0964     spin_lock_bh(&dc->lock);
0965 
0966     if (!list_empty(&dc->active_list))
0967         txx9dmac_scan_descriptors(dc);
0968     if (!list_empty(&dc->queue)) {
0969         if (list_empty(&dc->active_list)) {
0970             txx9dmac_dequeue(dc, &dc->active_list);
0971             txx9dmac_dostart(dc, txx9dmac_first_active(dc));
0972         } else if (txx9_dma_have_SMPCHN()) {
0973             struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
0974 
0975             if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
0976                 txx9dmac_chan_INTENT(dc))
0977                 txx9dmac_chain_dynamic(dc, prev);
0978         }
0979     }
0980 
0981     spin_unlock_bh(&dc->lock);
0982 }
0983 
0984 static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
0985 {
0986     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
0987     struct txx9dmac_slave *ds = chan->private;
0988     struct txx9dmac_desc *desc;
0989     int i;
0990 
0991     dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
0992 
0993     /* ASSERT:  channel is idle */
0994     if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
0995         dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
0996         return -EIO;
0997     }
0998 
0999     dma_cookie_init(chan);
1000 
1001     dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1002     txx9dmac_chan_set_SMPCHN(dc);
1003     if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1004         dc->ccr |= TXX9_DMA_CCR_INTENC;
1005     if (chan->device->device_prep_dma_memcpy) {
1006         if (ds)
1007             return -EINVAL;
1008         dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1009     } else {
1010         if (!ds ||
1011             (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1012             return -EINVAL;
1013         dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1014             TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1015         txx9dmac_chan_set_INTENT(dc);
1016     }
1017 
1018     spin_lock_bh(&dc->lock);
1019     i = dc->descs_allocated;
1020     while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1021         spin_unlock_bh(&dc->lock);
1022 
1023         desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1024         if (!desc) {
1025             dev_info(chan2dev(chan),
1026                 "only allocated %d descriptors\n", i);
1027             spin_lock_bh(&dc->lock);
1028             break;
1029         }
1030         txx9dmac_desc_put(dc, desc);
1031 
1032         spin_lock_bh(&dc->lock);
1033         i = ++dc->descs_allocated;
1034     }
1035     spin_unlock_bh(&dc->lock);
1036 
1037     dev_dbg(chan2dev(chan),
1038         "alloc_chan_resources allocated %d descriptors\n", i);
1039 
1040     return i;
1041 }
1042 
1043 static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1044 {
1045     struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1046     struct txx9dmac_dev *ddev = dc->ddev;
1047     struct txx9dmac_desc *desc, *_desc;
1048     LIST_HEAD(list);
1049 
1050     dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1051             dc->descs_allocated);
1052 
1053     /* ASSERT:  channel is idle */
1054     BUG_ON(!list_empty(&dc->active_list));
1055     BUG_ON(!list_empty(&dc->queue));
1056     BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1057 
1058     spin_lock_bh(&dc->lock);
1059     list_splice_init(&dc->free_list, &list);
1060     dc->descs_allocated = 0;
1061     spin_unlock_bh(&dc->lock);
1062 
1063     list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1064         dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1065         dma_unmap_single(chan2parent(chan), desc->txd.phys,
1066                  ddev->descsize, DMA_TO_DEVICE);
1067         kfree(desc);
1068     }
1069 
1070     dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1071 }
1072 
1073 /*----------------------------------------------------------------------*/
1074 
1075 static void txx9dmac_off(struct txx9dmac_dev *ddev)
1076 {
1077     dma_writel(ddev, MCR, 0);
1078 }
1079 
1080 static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1081 {
1082     struct txx9dmac_chan_platform_data *cpdata =
1083             dev_get_platdata(&pdev->dev);
1084     struct platform_device *dmac_dev = cpdata->dmac_dev;
1085     struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1086     struct txx9dmac_chan *dc;
1087     int err;
1088     int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1089     int irq;
1090 
1091     dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1092     if (!dc)
1093         return -ENOMEM;
1094 
1095     dc->dma.dev = &pdev->dev;
1096     dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1097     dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1098     dc->dma.device_terminate_all = txx9dmac_terminate_all;
1099     dc->dma.device_tx_status = txx9dmac_tx_status;
1100     dc->dma.device_issue_pending = txx9dmac_issue_pending;
1101     if (pdata && pdata->memcpy_chan == ch) {
1102         dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1103         dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1104     } else {
1105         dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1106         dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1107         dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1108     }
1109 
1110     INIT_LIST_HEAD(&dc->dma.channels);
1111     dc->ddev = platform_get_drvdata(dmac_dev);
1112     if (dc->ddev->irq < 0) {
1113         irq = platform_get_irq(pdev, 0);
1114         if (irq < 0)
1115             return irq;
1116         tasklet_setup(&dc->tasklet, txx9dmac_chan_tasklet);
1117         dc->irq = irq;
1118         err = devm_request_irq(&pdev->dev, dc->irq,
1119             txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1120         if (err)
1121             return err;
1122     } else
1123         dc->irq = -1;
1124     dc->ddev->chan[ch] = dc;
1125     dc->chan.device = &dc->dma;
1126     list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1127     dma_cookie_init(&dc->chan);
1128 
1129     if (is_dmac64(dc))
1130         dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1131     else
1132         dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1133     spin_lock_init(&dc->lock);
1134 
1135     INIT_LIST_HEAD(&dc->active_list);
1136     INIT_LIST_HEAD(&dc->queue);
1137     INIT_LIST_HEAD(&dc->free_list);
1138 
1139     txx9dmac_reset_chan(dc);
1140 
1141     platform_set_drvdata(pdev, dc);
1142 
1143     err = dma_async_device_register(&dc->dma);
1144     if (err)
1145         return err;
1146     dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1147         dc->dma.dev_id,
1148         dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1149         dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1150 
1151     return 0;
1152 }
1153 
1154 static int txx9dmac_chan_remove(struct platform_device *pdev)
1155 {
1156     struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1157 
1158 
1159     dma_async_device_unregister(&dc->dma);
1160     if (dc->irq >= 0) {
1161         devm_free_irq(&pdev->dev, dc->irq, dc);
1162         tasklet_kill(&dc->tasklet);
1163     }
1164     dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1165     return 0;
1166 }
1167 
1168 static int __init txx9dmac_probe(struct platform_device *pdev)
1169 {
1170     struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1171     struct resource *io;
1172     struct txx9dmac_dev *ddev;
1173     u32 mcr;
1174     int err;
1175 
1176     io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177     if (!io)
1178         return -EINVAL;
1179 
1180     ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1181     if (!ddev)
1182         return -ENOMEM;
1183 
1184     if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1185                      dev_name(&pdev->dev)))
1186         return -EBUSY;
1187 
1188     ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1189     if (!ddev->regs)
1190         return -ENOMEM;
1191     ddev->have_64bit_regs = pdata->have_64bit_regs;
1192     if (__is_dmac64(ddev))
1193         ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1194     else
1195         ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1196 
1197     /* force dma off, just in case */
1198     txx9dmac_off(ddev);
1199 
1200     ddev->irq = platform_get_irq(pdev, 0);
1201     if (ddev->irq >= 0) {
1202         tasklet_setup(&ddev->tasklet, txx9dmac_tasklet);
1203         err = devm_request_irq(&pdev->dev, ddev->irq,
1204             txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1205         if (err)
1206             return err;
1207     }
1208 
1209     mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1210     if (pdata && pdata->memcpy_chan >= 0)
1211         mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1212     dma_writel(ddev, MCR, mcr);
1213 
1214     platform_set_drvdata(pdev, ddev);
1215     return 0;
1216 }
1217 
1218 static int txx9dmac_remove(struct platform_device *pdev)
1219 {
1220     struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1221 
1222     txx9dmac_off(ddev);
1223     if (ddev->irq >= 0) {
1224         devm_free_irq(&pdev->dev, ddev->irq, ddev);
1225         tasklet_kill(&ddev->tasklet);
1226     }
1227     return 0;
1228 }
1229 
1230 static void txx9dmac_shutdown(struct platform_device *pdev)
1231 {
1232     struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1233 
1234     txx9dmac_off(ddev);
1235 }
1236 
1237 static int txx9dmac_suspend_noirq(struct device *dev)
1238 {
1239     struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
1240 
1241     txx9dmac_off(ddev);
1242     return 0;
1243 }
1244 
1245 static int txx9dmac_resume_noirq(struct device *dev)
1246 {
1247     struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
1248     struct txx9dmac_platform_data *pdata = dev_get_platdata(dev);
1249     u32 mcr;
1250 
1251     mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1252     if (pdata && pdata->memcpy_chan >= 0)
1253         mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1254     dma_writel(ddev, MCR, mcr);
1255     return 0;
1256 
1257 }
1258 
1259 static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1260     .suspend_noirq = txx9dmac_suspend_noirq,
1261     .resume_noirq = txx9dmac_resume_noirq,
1262 };
1263 
1264 static struct platform_driver txx9dmac_chan_driver = {
1265     .remove     = txx9dmac_chan_remove,
1266     .driver = {
1267         .name   = "txx9dmac-chan",
1268     },
1269 };
1270 
1271 static struct platform_driver txx9dmac_driver = {
1272     .remove     = txx9dmac_remove,
1273     .shutdown   = txx9dmac_shutdown,
1274     .driver = {
1275         .name   = "txx9dmac",
1276         .pm = &txx9dmac_dev_pm_ops,
1277     },
1278 };
1279 
1280 static int __init txx9dmac_init(void)
1281 {
1282     int rc;
1283 
1284     rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1285     if (!rc) {
1286         rc = platform_driver_probe(&txx9dmac_chan_driver,
1287                        txx9dmac_chan_probe);
1288         if (rc)
1289             platform_driver_unregister(&txx9dmac_driver);
1290     }
1291     return rc;
1292 }
1293 module_init(txx9dmac_init);
1294 
1295 static void __exit txx9dmac_exit(void)
1296 {
1297     platform_driver_unregister(&txx9dmac_chan_driver);
1298     platform_driver_unregister(&txx9dmac_driver);
1299 }
1300 module_exit(txx9dmac_exit);
1301 
1302 MODULE_LICENSE("GPL");
1303 MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1304 MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1305 MODULE_ALIAS("platform:txx9dmac");
1306 MODULE_ALIAS("platform:txx9dmac-chan");
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