dma/ti/k3-psil-j721e.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
0004  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0005  */
0006
0007 #include <linux/kernel.h>
0008
0009 #include "k3-psil-priv.h"
0010
0011 #define PSIL_PDMA_XY_TR(x)              \
0012     {                       \
0013         .thread_id = x,             \
0014         .ep_config = {              \
0015             .ep_type = PSIL_EP_PDMA_XY, \
0016         },                  \
0017     }
0018
0019 #define PSIL_PDMA_XY_PKT(x)             \
0020     {                       \
0021         .thread_id = x,             \
0022         .ep_config = {              \
0023             .ep_type = PSIL_EP_PDMA_XY, \
0024             .pkt_mode = 1,          \
0025         },                  \
0026     }
0027
0028 #define PSIL_PDMA_MCASP(x)              \
0029     {                       \
0030         .thread_id = x,             \
0031         .ep_config = {              \
0032             .ep_type = PSIL_EP_PDMA_XY, \
0033             .pdma_acc32 = 1,        \
0034             .pdma_burst = 1,        \
0035         },                  \
0036     }
0037
0038 #define PSIL_ETHERNET(x)                \
0039     {                       \
0040         .thread_id = x,             \
0041         .ep_config = {              \
0042             .ep_type = PSIL_EP_NATIVE,  \
0043             .pkt_mode = 1,          \
0044             .needs_epib = 1,        \
0045             .psd_size = 16,         \
0046         },                  \
0047     }
0048
0049 #define PSIL_SA2UL(x, tx)               \
0050     {                       \
0051         .thread_id = x,             \
0052         .ep_config = {              \
0053             .ep_type = PSIL_EP_NATIVE,  \
0054             .pkt_mode = 1,          \
0055             .needs_epib = 1,        \
0056             .psd_size = 64,         \
0057             .notdpkt = tx,          \
0058         },                  \
0059     }
0060
0061 #define PSIL_CSI2RX(x)                  \
0062     {                       \
0063         .thread_id = x,             \
0064         .ep_config = {              \
0065             .ep_type = PSIL_EP_NATIVE,  \
0066         },                  \
0067     }
0068
0069 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
0070 static struct psil_ep j721e_src_ep_map[] = {
0071     /* SA2UL */
0072     PSIL_SA2UL(0x4000, 0),
0073     PSIL_SA2UL(0x4001, 0),
0074     PSIL_SA2UL(0x4002, 0),
0075     PSIL_SA2UL(0x4003, 0),
0076     /* PRU_ICSSG0 */
0077     PSIL_ETHERNET(0x4100),
0078     PSIL_ETHERNET(0x4101),
0079     PSIL_ETHERNET(0x4102),
0080     PSIL_ETHERNET(0x4103),
0081     /* PRU_ICSSG1 */
0082     PSIL_ETHERNET(0x4200),
0083     PSIL_ETHERNET(0x4201),
0084     PSIL_ETHERNET(0x4202),
0085     PSIL_ETHERNET(0x4203),
0086     /* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
0087     PSIL_PDMA_MCASP(0x4400),
0088     PSIL_PDMA_MCASP(0x4401),
0089     PSIL_PDMA_MCASP(0x4402),
0090     /* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
0091     PSIL_PDMA_MCASP(0x4500),
0092     PSIL_PDMA_MCASP(0x4501),
0093     PSIL_PDMA_MCASP(0x4502),
0094     PSIL_PDMA_MCASP(0x4503),
0095     PSIL_PDMA_MCASP(0x4504),
0096     PSIL_PDMA_MCASP(0x4505),
0097     PSIL_PDMA_MCASP(0x4506),
0098     PSIL_PDMA_MCASP(0x4507),
0099     PSIL_PDMA_MCASP(0x4508),
0100     /* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
0101     PSIL_PDMA_XY_PKT(0x4600),
0102     PSIL_PDMA_XY_PKT(0x4601),
0103     PSIL_PDMA_XY_PKT(0x4602),
0104     PSIL_PDMA_XY_PKT(0x4603),
0105     PSIL_PDMA_XY_PKT(0x4604),
0106     PSIL_PDMA_XY_PKT(0x4605),
0107     PSIL_PDMA_XY_PKT(0x4606),
0108     PSIL_PDMA_XY_PKT(0x4607),
0109     /* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
0110     PSIL_PDMA_XY_PKT(0x460c),
0111     PSIL_PDMA_XY_PKT(0x460d),
0112     PSIL_PDMA_XY_PKT(0x460e),
0113     PSIL_PDMA_XY_PKT(0x460f),
0114     PSIL_PDMA_XY_PKT(0x4610),
0115     PSIL_PDMA_XY_PKT(0x4611),
0116     PSIL_PDMA_XY_PKT(0x4612),
0117     PSIL_PDMA_XY_PKT(0x4613),
0118     /* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
0119     PSIL_PDMA_XY_PKT(0x4618),
0120     PSIL_PDMA_XY_PKT(0x4619),
0121     PSIL_PDMA_XY_PKT(0x461a),
0122     PSIL_PDMA_XY_PKT(0x461b),
0123     PSIL_PDMA_XY_PKT(0x461c),
0124     PSIL_PDMA_XY_PKT(0x461d),
0125     PSIL_PDMA_XY_PKT(0x461e),
0126     PSIL_PDMA_XY_PKT(0x461f),
0127     /* PDMA11 (PDMA_MISC_G3) */
0128     PSIL_PDMA_XY_PKT(0x4624),
0129     PSIL_PDMA_XY_PKT(0x4625),
0130     PSIL_PDMA_XY_PKT(0x4626),
0131     PSIL_PDMA_XY_PKT(0x4627),
0132     PSIL_PDMA_XY_PKT(0x4628),
0133     PSIL_PDMA_XY_PKT(0x4629),
0134     PSIL_PDMA_XY_PKT(0x4630),
0135     PSIL_PDMA_XY_PKT(0x463a),
0136     /* PDMA13 (PDMA_USART_G0) - UART0-1 */
0137     PSIL_PDMA_XY_PKT(0x4700),
0138     PSIL_PDMA_XY_PKT(0x4701),
0139     /* PDMA14 (PDMA_USART_G1) - UART2-3 */
0140     PSIL_PDMA_XY_PKT(0x4702),
0141     PSIL_PDMA_XY_PKT(0x4703),
0142     /* PDMA15 (PDMA_USART_G2) - UART4-9 */
0143     PSIL_PDMA_XY_PKT(0x4704),
0144     PSIL_PDMA_XY_PKT(0x4705),
0145     PSIL_PDMA_XY_PKT(0x4706),
0146     PSIL_PDMA_XY_PKT(0x4707),
0147     PSIL_PDMA_XY_PKT(0x4708),
0148     PSIL_PDMA_XY_PKT(0x4709),
0149     /* CSI2RX */
0150     PSIL_CSI2RX(0x4940),
0151     PSIL_CSI2RX(0x4941),
0152     PSIL_CSI2RX(0x4942),
0153     PSIL_CSI2RX(0x4943),
0154     PSIL_CSI2RX(0x4944),
0155     PSIL_CSI2RX(0x4945),
0156     PSIL_CSI2RX(0x4946),
0157     PSIL_CSI2RX(0x4947),
0158     PSIL_CSI2RX(0x4948),
0159     PSIL_CSI2RX(0x4949),
0160     PSIL_CSI2RX(0x494a),
0161     PSIL_CSI2RX(0x494b),
0162     PSIL_CSI2RX(0x494c),
0163     PSIL_CSI2RX(0x494d),
0164     PSIL_CSI2RX(0x494e),
0165     PSIL_CSI2RX(0x494f),
0166     PSIL_CSI2RX(0x4950),
0167     PSIL_CSI2RX(0x4951),
0168     PSIL_CSI2RX(0x4952),
0169     PSIL_CSI2RX(0x4953),
0170     PSIL_CSI2RX(0x4954),
0171     PSIL_CSI2RX(0x4955),
0172     PSIL_CSI2RX(0x4956),
0173     PSIL_CSI2RX(0x4957),
0174     PSIL_CSI2RX(0x4958),
0175     PSIL_CSI2RX(0x4959),
0176     PSIL_CSI2RX(0x495a),
0177     PSIL_CSI2RX(0x495b),
0178     PSIL_CSI2RX(0x495c),
0179     PSIL_CSI2RX(0x495d),
0180     PSIL_CSI2RX(0x495e),
0181     PSIL_CSI2RX(0x495f),
0182     PSIL_CSI2RX(0x4960),
0183     PSIL_CSI2RX(0x4961),
0184     PSIL_CSI2RX(0x4962),
0185     PSIL_CSI2RX(0x4963),
0186     PSIL_CSI2RX(0x4964),
0187     PSIL_CSI2RX(0x4965),
0188     PSIL_CSI2RX(0x4966),
0189     PSIL_CSI2RX(0x4967),
0190     PSIL_CSI2RX(0x4968),
0191     PSIL_CSI2RX(0x4969),
0192     PSIL_CSI2RX(0x496a),
0193     PSIL_CSI2RX(0x496b),
0194     PSIL_CSI2RX(0x496c),
0195     PSIL_CSI2RX(0x496d),
0196     PSIL_CSI2RX(0x496e),
0197     PSIL_CSI2RX(0x496f),
0198     PSIL_CSI2RX(0x4970),
0199     PSIL_CSI2RX(0x4971),
0200     PSIL_CSI2RX(0x4972),
0201     PSIL_CSI2RX(0x4973),
0202     PSIL_CSI2RX(0x4974),
0203     PSIL_CSI2RX(0x4975),
0204     PSIL_CSI2RX(0x4976),
0205     PSIL_CSI2RX(0x4977),
0206     PSIL_CSI2RX(0x4978),
0207     PSIL_CSI2RX(0x4979),
0208     PSIL_CSI2RX(0x497a),
0209     PSIL_CSI2RX(0x497b),
0210     PSIL_CSI2RX(0x497c),
0211     PSIL_CSI2RX(0x497d),
0212     PSIL_CSI2RX(0x497e),
0213     PSIL_CSI2RX(0x497f),
0214     /* CPSW9 */
0215     PSIL_ETHERNET(0x4a00),
0216     /* CPSW0 */
0217     PSIL_ETHERNET(0x7000),
0218     /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
0219     PSIL_PDMA_XY_PKT(0x7100),
0220     PSIL_PDMA_XY_PKT(0x7101),
0221     PSIL_PDMA_XY_PKT(0x7102),
0222     PSIL_PDMA_XY_PKT(0x7103),
0223     /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
0224     PSIL_PDMA_XY_PKT(0x7200),
0225     PSIL_PDMA_XY_PKT(0x7201),
0226     PSIL_PDMA_XY_PKT(0x7202),
0227     PSIL_PDMA_XY_PKT(0x7203),
0228     PSIL_PDMA_XY_PKT(0x7204),
0229     PSIL_PDMA_XY_PKT(0x7205),
0230     PSIL_PDMA_XY_PKT(0x7206),
0231     PSIL_PDMA_XY_PKT(0x7207),
0232     /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
0233     PSIL_PDMA_XY_PKT(0x7300),
0234     /* MCU_PDMA_ADC - ADC0-1 */
0235     PSIL_PDMA_XY_TR(0x7400),
0236     PSIL_PDMA_XY_TR(0x7401),
0237     PSIL_PDMA_XY_TR(0x7402),
0238     PSIL_PDMA_XY_TR(0x7403),
0239     /* SA2UL */
0240     PSIL_SA2UL(0x7500, 0),
0241     PSIL_SA2UL(0x7501, 0),
0242     PSIL_SA2UL(0x7502, 0),
0243     PSIL_SA2UL(0x7503, 0),
0244 };
0245
0246 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
0247 static struct psil_ep j721e_dst_ep_map[] = {
0248     /* SA2UL */
0249     PSIL_SA2UL(0xc000, 1),
0250     PSIL_SA2UL(0xc001, 1),
0251     /* PRU_ICSSG0 */
0252     PSIL_ETHERNET(0xc100),
0253     PSIL_ETHERNET(0xc101),
0254     PSIL_ETHERNET(0xc102),
0255     PSIL_ETHERNET(0xc103),
0256     PSIL_ETHERNET(0xc104),
0257     PSIL_ETHERNET(0xc105),
0258     PSIL_ETHERNET(0xc106),
0259     PSIL_ETHERNET(0xc107),
0260     /* PRU_ICSSG1 */
0261     PSIL_ETHERNET(0xc200),
0262     PSIL_ETHERNET(0xc201),
0263     PSIL_ETHERNET(0xc202),
0264     PSIL_ETHERNET(0xc203),
0265     PSIL_ETHERNET(0xc204),
0266     PSIL_ETHERNET(0xc205),
0267     PSIL_ETHERNET(0xc206),
0268     PSIL_ETHERNET(0xc207),
0269     /* CPSW9 */
0270     PSIL_ETHERNET(0xca00),
0271     PSIL_ETHERNET(0xca01),
0272     PSIL_ETHERNET(0xca02),
0273     PSIL_ETHERNET(0xca03),
0274     PSIL_ETHERNET(0xca04),
0275     PSIL_ETHERNET(0xca05),
0276     PSIL_ETHERNET(0xca06),
0277     PSIL_ETHERNET(0xca07),
0278     /* CPSW0 */
0279     PSIL_ETHERNET(0xf000),
0280     PSIL_ETHERNET(0xf001),
0281     PSIL_ETHERNET(0xf002),
0282     PSIL_ETHERNET(0xf003),
0283     PSIL_ETHERNET(0xf004),
0284     PSIL_ETHERNET(0xf005),
0285     PSIL_ETHERNET(0xf006),
0286     PSIL_ETHERNET(0xf007),
0287     /* SA2UL */
0288     PSIL_SA2UL(0xf500, 1),
0289     PSIL_SA2UL(0xf501, 1),
0290 };
0291
0292 struct psil_ep_map j721e_ep_map = {
0293     .name = "j721e",
0294     .src = j721e_src_ep_map,
0295     .src_count = ARRAY_SIZE(j721e_src_ep_map),
0296     .dst = j721e_dst_ep_map,
0297     .dst_count = ARRAY_SIZE(j721e_dst_ep_map),
0298 };