dma/ti/k3-psil-j7200.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
0004  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0005  */
0006
0007 #include <linux/kernel.h>
0008
0009 #include "k3-psil-priv.h"
0010
0011 #define PSIL_PDMA_XY_TR(x)              \
0012     {                       \
0013         .thread_id = x,             \
0014         .ep_config = {              \
0015             .ep_type = PSIL_EP_PDMA_XY, \
0016         },                  \
0017     }
0018
0019 #define PSIL_PDMA_XY_PKT(x)             \
0020     {                       \
0021         .thread_id = x,             \
0022         .ep_config = {              \
0023             .ep_type = PSIL_EP_PDMA_XY, \
0024             .pkt_mode = 1,          \
0025         },                  \
0026     }
0027
0028 #define PSIL_PDMA_MCASP(x)              \
0029     {                       \
0030         .thread_id = x,             \
0031         .ep_config = {              \
0032             .ep_type = PSIL_EP_PDMA_XY, \
0033             .pdma_acc32 = 1,        \
0034             .pdma_burst = 1,        \
0035         },                  \
0036     }
0037
0038 #define PSIL_ETHERNET(x)                \
0039     {                       \
0040         .thread_id = x,             \
0041         .ep_config = {              \
0042             .ep_type = PSIL_EP_NATIVE,  \
0043             .pkt_mode = 1,          \
0044             .needs_epib = 1,        \
0045             .psd_size = 16,         \
0046         },                  \
0047     }
0048
0049 #define PSIL_SA2UL(x, tx)               \
0050     {                       \
0051         .thread_id = x,             \
0052         .ep_config = {              \
0053             .ep_type = PSIL_EP_NATIVE,  \
0054             .pkt_mode = 1,          \
0055             .needs_epib = 1,        \
0056             .psd_size = 64,         \
0057             .notdpkt = tx,          \
0058         },                  \
0059     }
0060
0061 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
0062 static struct psil_ep j7200_src_ep_map[] = {
0063     /* PDMA_MCASP - McASP0-2 */
0064     PSIL_PDMA_MCASP(0x4400),
0065     PSIL_PDMA_MCASP(0x4401),
0066     PSIL_PDMA_MCASP(0x4402),
0067     /* PDMA_SPI_G0 - SPI0-3 */
0068     PSIL_PDMA_XY_PKT(0x4600),
0069     PSIL_PDMA_XY_PKT(0x4601),
0070     PSIL_PDMA_XY_PKT(0x4602),
0071     PSIL_PDMA_XY_PKT(0x4603),
0072     PSIL_PDMA_XY_PKT(0x4604),
0073     PSIL_PDMA_XY_PKT(0x4605),
0074     PSIL_PDMA_XY_PKT(0x4606),
0075     PSIL_PDMA_XY_PKT(0x4607),
0076     PSIL_PDMA_XY_PKT(0x4608),
0077     PSIL_PDMA_XY_PKT(0x4609),
0078     PSIL_PDMA_XY_PKT(0x460a),
0079     PSIL_PDMA_XY_PKT(0x460b),
0080     PSIL_PDMA_XY_PKT(0x460c),
0081     PSIL_PDMA_XY_PKT(0x460d),
0082     PSIL_PDMA_XY_PKT(0x460e),
0083     PSIL_PDMA_XY_PKT(0x460f),
0084     /* PDMA_SPI_G1 - SPI4-7 */
0085     PSIL_PDMA_XY_PKT(0x4610),
0086     PSIL_PDMA_XY_PKT(0x4611),
0087     PSIL_PDMA_XY_PKT(0x4612),
0088     PSIL_PDMA_XY_PKT(0x4613),
0089     PSIL_PDMA_XY_PKT(0x4614),
0090     PSIL_PDMA_XY_PKT(0x4615),
0091     PSIL_PDMA_XY_PKT(0x4616),
0092     PSIL_PDMA_XY_PKT(0x4617),
0093     PSIL_PDMA_XY_PKT(0x4618),
0094     PSIL_PDMA_XY_PKT(0x4619),
0095     PSIL_PDMA_XY_PKT(0x461a),
0096     PSIL_PDMA_XY_PKT(0x461b),
0097     PSIL_PDMA_XY_PKT(0x461c),
0098     PSIL_PDMA_XY_PKT(0x461d),
0099     PSIL_PDMA_XY_PKT(0x461e),
0100     PSIL_PDMA_XY_PKT(0x461f),
0101     /* PDMA_USART_G0 - UART0-1 */
0102     PSIL_PDMA_XY_PKT(0x4700),
0103     PSIL_PDMA_XY_PKT(0x4701),
0104     /* PDMA_USART_G1 - UART2-3 */
0105     PSIL_PDMA_XY_PKT(0x4702),
0106     PSIL_PDMA_XY_PKT(0x4703),
0107     /* PDMA_USART_G2 - UART4-9 */
0108     PSIL_PDMA_XY_PKT(0x4704),
0109     PSIL_PDMA_XY_PKT(0x4705),
0110     PSIL_PDMA_XY_PKT(0x4706),
0111     PSIL_PDMA_XY_PKT(0x4707),
0112     PSIL_PDMA_XY_PKT(0x4708),
0113     PSIL_PDMA_XY_PKT(0x4709),
0114     /* CPSW5 */
0115     PSIL_ETHERNET(0x4a00),
0116     /* CPSW0 */
0117     PSIL_ETHERNET(0x7000),
0118     /* MCU_PDMA_MISC_G0 - SPI0 */
0119     PSIL_PDMA_XY_PKT(0x7100),
0120     PSIL_PDMA_XY_PKT(0x7101),
0121     PSIL_PDMA_XY_PKT(0x7102),
0122     PSIL_PDMA_XY_PKT(0x7103),
0123     /* MCU_PDMA_MISC_G1 - SPI1-2 */
0124     PSIL_PDMA_XY_PKT(0x7200),
0125     PSIL_PDMA_XY_PKT(0x7201),
0126     PSIL_PDMA_XY_PKT(0x7202),
0127     PSIL_PDMA_XY_PKT(0x7203),
0128     PSIL_PDMA_XY_PKT(0x7204),
0129     PSIL_PDMA_XY_PKT(0x7205),
0130     PSIL_PDMA_XY_PKT(0x7206),
0131     PSIL_PDMA_XY_PKT(0x7207),
0132     /* MCU_PDMA_MISC_G2 - UART0 */
0133     PSIL_PDMA_XY_PKT(0x7300),
0134     /* MCU_PDMA_ADC - ADC0-1 */
0135     PSIL_PDMA_XY_TR(0x7400),
0136     PSIL_PDMA_XY_TR(0x7401),
0137     /* SA2UL */
0138     PSIL_SA2UL(0x7500, 0),
0139     PSIL_SA2UL(0x7501, 0),
0140     PSIL_SA2UL(0x7502, 0),
0141     PSIL_SA2UL(0x7503, 0),
0142 };
0143
0144 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
0145 static struct psil_ep j7200_dst_ep_map[] = {
0146     /* CPSW5 */
0147     PSIL_ETHERNET(0xca00),
0148     PSIL_ETHERNET(0xca01),
0149     PSIL_ETHERNET(0xca02),
0150     PSIL_ETHERNET(0xca03),
0151     PSIL_ETHERNET(0xca04),
0152     PSIL_ETHERNET(0xca05),
0153     PSIL_ETHERNET(0xca06),
0154     PSIL_ETHERNET(0xca07),
0155     /* CPSW0 */
0156     PSIL_ETHERNET(0xf000),
0157     PSIL_ETHERNET(0xf001),
0158     PSIL_ETHERNET(0xf002),
0159     PSIL_ETHERNET(0xf003),
0160     PSIL_ETHERNET(0xf004),
0161     PSIL_ETHERNET(0xf005),
0162     PSIL_ETHERNET(0xf006),
0163     PSIL_ETHERNET(0xf007),
0164     /* SA2UL */
0165     PSIL_SA2UL(0xf500, 1),
0166     PSIL_SA2UL(0xf501, 1),
0167 };
0168
0169 struct psil_ep_map j7200_ep_map = {
0170     .name = "j7200",
0171     .src = j7200_src_ep_map,
0172     .src_count = ARRAY_SIZE(j7200_src_ep_map),
0173     .dst = j7200_dst_ep_map,
0174     .dst_count = ARRAY_SIZE(j7200_dst_ep_map),
0175 };