dma/ti/k3-psil-am654.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
0004  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0005  */
0006
0007 #include <linux/kernel.h>
0008
0009 #include "k3-psil-priv.h"
0010
0011 #define PSIL_PDMA_XY_TR(x)              \
0012     {                       \
0013         .thread_id = x,             \
0014         .ep_config = {              \
0015             .ep_type = PSIL_EP_PDMA_XY, \
0016         },                  \
0017     }
0018
0019 #define PSIL_PDMA_XY_PKT(x)             \
0020     {                       \
0021         .thread_id = x,             \
0022         .ep_config = {              \
0023             .ep_type = PSIL_EP_PDMA_XY, \
0024             .pkt_mode = 1,          \
0025         },                  \
0026     }
0027
0028 #define PSIL_ETHERNET(x)                \
0029     {                       \
0030         .thread_id = x,             \
0031         .ep_config = {              \
0032             .ep_type = PSIL_EP_NATIVE,  \
0033             .pkt_mode = 1,          \
0034             .needs_epib = 1,        \
0035             .psd_size = 16,         \
0036         },                  \
0037     }
0038
0039 #define PSIL_SA2UL(x, tx)               \
0040     {                       \
0041         .thread_id = x,             \
0042         .ep_config = {              \
0043             .ep_type = PSIL_EP_NATIVE,  \
0044             .pkt_mode = 1,          \
0045             .needs_epib = 1,        \
0046             .psd_size = 64,         \
0047             .notdpkt = tx,          \
0048         },                  \
0049     }
0050
0051 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
0052 static struct psil_ep am654_src_ep_map[] = {
0053     /* SA2UL */
0054     PSIL_SA2UL(0x4000, 0),
0055     PSIL_SA2UL(0x4001, 0),
0056     PSIL_SA2UL(0x4002, 0),
0057     PSIL_SA2UL(0x4003, 0),
0058     /* PRU_ICSSG0 */
0059     PSIL_ETHERNET(0x4100),
0060     PSIL_ETHERNET(0x4101),
0061     PSIL_ETHERNET(0x4102),
0062     PSIL_ETHERNET(0x4103),
0063     /* PRU_ICSSG1 */
0064     PSIL_ETHERNET(0x4200),
0065     PSIL_ETHERNET(0x4201),
0066     PSIL_ETHERNET(0x4202),
0067     PSIL_ETHERNET(0x4203),
0068     /* PRU_ICSSG2 */
0069     PSIL_ETHERNET(0x4300),
0070     PSIL_ETHERNET(0x4301),
0071     PSIL_ETHERNET(0x4302),
0072     PSIL_ETHERNET(0x4303),
0073     /* PDMA0 - McASPs */
0074     PSIL_PDMA_XY_TR(0x4400),
0075     PSIL_PDMA_XY_TR(0x4401),
0076     PSIL_PDMA_XY_TR(0x4402),
0077     /* PDMA1 - SPI0-4 */
0078     PSIL_PDMA_XY_PKT(0x4500),
0079     PSIL_PDMA_XY_PKT(0x4501),
0080     PSIL_PDMA_XY_PKT(0x4502),
0081     PSIL_PDMA_XY_PKT(0x4503),
0082     PSIL_PDMA_XY_PKT(0x4504),
0083     PSIL_PDMA_XY_PKT(0x4505),
0084     PSIL_PDMA_XY_PKT(0x4506),
0085     PSIL_PDMA_XY_PKT(0x4507),
0086     PSIL_PDMA_XY_PKT(0x4508),
0087     PSIL_PDMA_XY_PKT(0x4509),
0088     PSIL_PDMA_XY_PKT(0x450a),
0089     PSIL_PDMA_XY_PKT(0x450b),
0090     PSIL_PDMA_XY_PKT(0x450c),
0091     PSIL_PDMA_XY_PKT(0x450d),
0092     PSIL_PDMA_XY_PKT(0x450e),
0093     PSIL_PDMA_XY_PKT(0x450f),
0094     PSIL_PDMA_XY_PKT(0x4510),
0095     PSIL_PDMA_XY_PKT(0x4511),
0096     PSIL_PDMA_XY_PKT(0x4512),
0097     PSIL_PDMA_XY_PKT(0x4513),
0098     /* PDMA1 - USART0-2 */
0099     PSIL_PDMA_XY_PKT(0x4514),
0100     PSIL_PDMA_XY_PKT(0x4515),
0101     PSIL_PDMA_XY_PKT(0x4516),
0102     /* CPSW0 */
0103     PSIL_ETHERNET(0x7000),
0104     /* MCU_PDMA0 - ADCs */
0105     PSIL_PDMA_XY_TR(0x7100),
0106     PSIL_PDMA_XY_TR(0x7101),
0107     PSIL_PDMA_XY_TR(0x7102),
0108     PSIL_PDMA_XY_TR(0x7103),
0109     /* MCU_PDMA1 - MCU_SPI0-2 */
0110     PSIL_PDMA_XY_PKT(0x7200),
0111     PSIL_PDMA_XY_PKT(0x7201),
0112     PSIL_PDMA_XY_PKT(0x7202),
0113     PSIL_PDMA_XY_PKT(0x7203),
0114     PSIL_PDMA_XY_PKT(0x7204),
0115     PSIL_PDMA_XY_PKT(0x7205),
0116     PSIL_PDMA_XY_PKT(0x7206),
0117     PSIL_PDMA_XY_PKT(0x7207),
0118     PSIL_PDMA_XY_PKT(0x7208),
0119     PSIL_PDMA_XY_PKT(0x7209),
0120     PSIL_PDMA_XY_PKT(0x720a),
0121     PSIL_PDMA_XY_PKT(0x720b),
0122     /* MCU_PDMA1 - MCU_USART0 */
0123     PSIL_PDMA_XY_PKT(0x7212),
0124 };
0125
0126 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
0127 static struct psil_ep am654_dst_ep_map[] = {
0128     /* SA2UL */
0129     PSIL_SA2UL(0xc000, 1),
0130     PSIL_SA2UL(0xc001, 1),
0131     /* PRU_ICSSG0 */
0132     PSIL_ETHERNET(0xc100),
0133     PSIL_ETHERNET(0xc101),
0134     PSIL_ETHERNET(0xc102),
0135     PSIL_ETHERNET(0xc103),
0136     PSIL_ETHERNET(0xc104),
0137     PSIL_ETHERNET(0xc105),
0138     PSIL_ETHERNET(0xc106),
0139     PSIL_ETHERNET(0xc107),
0140     /* PRU_ICSSG1 */
0141     PSIL_ETHERNET(0xc200),
0142     PSIL_ETHERNET(0xc201),
0143     PSIL_ETHERNET(0xc202),
0144     PSIL_ETHERNET(0xc203),
0145     PSIL_ETHERNET(0xc204),
0146     PSIL_ETHERNET(0xc205),
0147     PSIL_ETHERNET(0xc206),
0148     PSIL_ETHERNET(0xc207),
0149     /* PRU_ICSSG2 */
0150     PSIL_ETHERNET(0xc300),
0151     PSIL_ETHERNET(0xc301),
0152     PSIL_ETHERNET(0xc302),
0153     PSIL_ETHERNET(0xc303),
0154     PSIL_ETHERNET(0xc304),
0155     PSIL_ETHERNET(0xc305),
0156     PSIL_ETHERNET(0xc306),
0157     PSIL_ETHERNET(0xc307),
0158     /* CPSW0 */
0159     PSIL_ETHERNET(0xf000),
0160     PSIL_ETHERNET(0xf001),
0161     PSIL_ETHERNET(0xf002),
0162     PSIL_ETHERNET(0xf003),
0163     PSIL_ETHERNET(0xf004),
0164     PSIL_ETHERNET(0xf005),
0165     PSIL_ETHERNET(0xf006),
0166     PSIL_ETHERNET(0xf007),
0167 };
0168
0169 struct psil_ep_map am654_ep_map = {
0170     .name = "am654",
0171     .src = am654_src_ep_map,
0172     .src_count = ARRAY_SIZE(am654_src_ep_map),
0173     .dst = am654_dst_ep_map,
0174     .dst_count = ARRAY_SIZE(am654_dst_ep_map),
0175 };