dma/ti/k3-psil-am64.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
0004  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0005  */
0006
0007 #include <linux/kernel.h>
0008
0009 #include "k3-psil-priv.h"
0010
0011 #define PSIL_PDMA_XY_TR(x)                  \
0012     {                           \
0013         .thread_id = x,                 \
0014         .ep_config = {                  \
0015             .ep_type = PSIL_EP_PDMA_XY,     \
0016             .mapped_channel_id = -1,        \
0017             .default_flow_id = -1,          \
0018         },                      \
0019     }
0020
0021 #define PSIL_PDMA_XY_PKT(x)                 \
0022     {                           \
0023         .thread_id = x,                 \
0024         .ep_config = {                  \
0025             .ep_type = PSIL_EP_PDMA_XY,     \
0026             .mapped_channel_id = -1,        \
0027             .default_flow_id = -1,          \
0028             .pkt_mode = 1,              \
0029         },                      \
0030     }
0031
0032 #define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)       \
0033     {                           \
0034         .thread_id = x,                 \
0035         .ep_config = {                  \
0036             .ep_type = PSIL_EP_NATIVE,      \
0037             .pkt_mode = 1,              \
0038             .needs_epib = 1,            \
0039             .psd_size = 16,             \
0040             .mapped_channel_id = ch,        \
0041             .flow_start = flow_base,        \
0042             .flow_num = flow_cnt,           \
0043             .default_flow_id = flow_base,       \
0044         },                      \
0045     }
0046
0047 #define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
0048     {                           \
0049         .thread_id = x,                 \
0050         .ep_config = {                  \
0051             .ep_type = PSIL_EP_NATIVE,      \
0052             .pkt_mode = 1,              \
0053             .needs_epib = 1,            \
0054             .psd_size = 64,             \
0055             .mapped_channel_id = ch,        \
0056             .flow_start = flow_base,        \
0057             .flow_num = flow_cnt,           \
0058             .default_flow_id = default_flow,    \
0059             .notdpkt = tx,              \
0060         },                      \
0061     }
0062
0063 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
0064 static struct psil_ep am64_src_ep_map[] = {
0065     /* SAUL */
0066     PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
0067     PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
0068     PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
0069     PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
0070     /* ICSS_G0 */
0071     PSIL_ETHERNET(0x4100, 21, 48, 16),
0072     PSIL_ETHERNET(0x4101, 22, 64, 16),
0073     PSIL_ETHERNET(0x4102, 23, 80, 16),
0074     PSIL_ETHERNET(0x4103, 24, 96, 16),
0075     /* ICSS_G1 */
0076     PSIL_ETHERNET(0x4200, 25, 112, 16),
0077     PSIL_ETHERNET(0x4201, 26, 128, 16),
0078     PSIL_ETHERNET(0x4202, 27, 144, 16),
0079     PSIL_ETHERNET(0x4203, 28, 160, 16),
0080     /* PDMA_MAIN0 - SPI0-3 */
0081     PSIL_PDMA_XY_PKT(0x4300),
0082     PSIL_PDMA_XY_PKT(0x4301),
0083     PSIL_PDMA_XY_PKT(0x4302),
0084     PSIL_PDMA_XY_PKT(0x4303),
0085     PSIL_PDMA_XY_PKT(0x4304),
0086     PSIL_PDMA_XY_PKT(0x4305),
0087     PSIL_PDMA_XY_PKT(0x4306),
0088     PSIL_PDMA_XY_PKT(0x4307),
0089     PSIL_PDMA_XY_PKT(0x4308),
0090     PSIL_PDMA_XY_PKT(0x4309),
0091     PSIL_PDMA_XY_PKT(0x430a),
0092     PSIL_PDMA_XY_PKT(0x430b),
0093     PSIL_PDMA_XY_PKT(0x430c),
0094     PSIL_PDMA_XY_PKT(0x430d),
0095     PSIL_PDMA_XY_PKT(0x430e),
0096     PSIL_PDMA_XY_PKT(0x430f),
0097     /* PDMA_MAIN0 - USART0-1 */
0098     PSIL_PDMA_XY_PKT(0x4310),
0099     PSIL_PDMA_XY_PKT(0x4311),
0100     /* PDMA_MAIN1 - SPI4 */
0101     PSIL_PDMA_XY_PKT(0x4400),
0102     PSIL_PDMA_XY_PKT(0x4401),
0103     PSIL_PDMA_XY_PKT(0x4402),
0104     PSIL_PDMA_XY_PKT(0x4403),
0105     /* PDMA_MAIN1 - USART2-6 */
0106     PSIL_PDMA_XY_PKT(0x4404),
0107     PSIL_PDMA_XY_PKT(0x4405),
0108     PSIL_PDMA_XY_PKT(0x4406),
0109     PSIL_PDMA_XY_PKT(0x4407),
0110     PSIL_PDMA_XY_PKT(0x4408),
0111     /* PDMA_MAIN1 - ADCs */
0112     PSIL_PDMA_XY_TR(0x440f),
0113     PSIL_PDMA_XY_TR(0x4410),
0114     /* CPSW2 */
0115     PSIL_ETHERNET(0x4500, 16, 16, 16),
0116 };
0117
0118 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
0119 static struct psil_ep am64_dst_ep_map[] = {
0120     /* SAUL */
0121     PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
0122     PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
0123     /* ICSS_G0 */
0124     PSIL_ETHERNET(0xc100, 26, 96, 1),
0125     PSIL_ETHERNET(0xc101, 27, 97, 1),
0126     PSIL_ETHERNET(0xc102, 28, 98, 1),
0127     PSIL_ETHERNET(0xc103, 29, 99, 1),
0128     PSIL_ETHERNET(0xc104, 30, 100, 1),
0129     PSIL_ETHERNET(0xc105, 31, 101, 1),
0130     PSIL_ETHERNET(0xc106, 32, 102, 1),
0131     PSIL_ETHERNET(0xc107, 33, 103, 1),
0132     /* ICSS_G1 */
0133     PSIL_ETHERNET(0xc200, 34, 104, 1),
0134     PSIL_ETHERNET(0xc201, 35, 105, 1),
0135     PSIL_ETHERNET(0xc202, 36, 106, 1),
0136     PSIL_ETHERNET(0xc203, 37, 107, 1),
0137     PSIL_ETHERNET(0xc204, 38, 108, 1),
0138     PSIL_ETHERNET(0xc205, 39, 109, 1),
0139     PSIL_ETHERNET(0xc206, 40, 110, 1),
0140     PSIL_ETHERNET(0xc207, 41, 111, 1),
0141     /* CPSW2 */
0142     PSIL_ETHERNET(0xc500, 16, 16, 8),
0143     PSIL_ETHERNET(0xc501, 17, 24, 8),
0144     PSIL_ETHERNET(0xc502, 18, 32, 8),
0145     PSIL_ETHERNET(0xc503, 19, 40, 8),
0146     PSIL_ETHERNET(0xc504, 20, 48, 8),
0147     PSIL_ETHERNET(0xc505, 21, 56, 8),
0148     PSIL_ETHERNET(0xc506, 22, 64, 8),
0149     PSIL_ETHERNET(0xc507, 23, 72, 8),
0150 };
0151
0152 struct psil_ep_map am64_ep_map = {
0153     .name = "am64",
0154     .src = am64_src_ep_map,
0155     .src_count = ARRAY_SIZE(am64_src_ep_map),
0156     .dst = am64_dst_ep_map,
0157     .dst_count = ARRAY_SIZE(am64_dst_ep_map),
0158 };