dma/ti/k3-psil-am62.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
0004  */
0005
0006 #include <linux/kernel.h>
0007
0008 #include "k3-psil-priv.h"
0009
0010 #define PSIL_PDMA_XY_PKT(x)                 \
0011     {                           \
0012         .thread_id = x,                 \
0013         .ep_config = {                  \
0014             .ep_type = PSIL_EP_PDMA_XY,     \
0015             .mapped_channel_id = -1,        \
0016             .default_flow_id = -1,          \
0017             .pkt_mode = 1,              \
0018         },                      \
0019     }
0020
0021 #define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)       \
0022     {                           \
0023         .thread_id = x,                 \
0024         .ep_config = {                  \
0025             .ep_type = PSIL_EP_NATIVE,      \
0026             .pkt_mode = 1,              \
0027             .needs_epib = 1,            \
0028             .psd_size = 16,             \
0029             .mapped_channel_id = ch,        \
0030             .flow_start = flow_base,        \
0031             .flow_num = flow_cnt,           \
0032             .default_flow_id = flow_base,       \
0033         },                      \
0034     }
0035
0036 #define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
0037     {                           \
0038         .thread_id = x,                 \
0039         .ep_config = {                  \
0040             .ep_type = PSIL_EP_NATIVE,      \
0041             .pkt_mode = 1,              \
0042             .needs_epib = 1,            \
0043             .psd_size = 64,             \
0044             .mapped_channel_id = ch,        \
0045             .flow_start = flow_base,        \
0046             .flow_num = flow_cnt,           \
0047             .default_flow_id = default_flow,    \
0048             .notdpkt = tx,              \
0049         },                      \
0050     }
0051
0052 #define PSIL_PDMA_MCASP(x)              \
0053     {                       \
0054         .thread_id = x,             \
0055         .ep_config = {              \
0056             .ep_type = PSIL_EP_PDMA_XY, \
0057             .pdma_acc32 = 1,        \
0058             .pdma_burst = 1,        \
0059         },                  \
0060     }
0061
0062 #define PSIL_CSI2RX(x)                  \
0063     {                       \
0064         .thread_id = x,             \
0065         .ep_config = {              \
0066             .ep_type = PSIL_EP_NATIVE,  \
0067         },                  \
0068     }
0069
0070 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
0071 static struct psil_ep am62_src_ep_map[] = {
0072     /* SAUL */
0073     PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
0074     PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
0075     PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
0076     PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
0077     /* PDMA_MAIN0 - SPI0-3 */
0078     PSIL_PDMA_XY_PKT(0x4302),
0079     PSIL_PDMA_XY_PKT(0x4303),
0080     PSIL_PDMA_XY_PKT(0x4304),
0081     PSIL_PDMA_XY_PKT(0x4305),
0082     PSIL_PDMA_XY_PKT(0x4306),
0083     PSIL_PDMA_XY_PKT(0x4307),
0084     PSIL_PDMA_XY_PKT(0x4308),
0085     PSIL_PDMA_XY_PKT(0x4309),
0086     PSIL_PDMA_XY_PKT(0x430a),
0087     PSIL_PDMA_XY_PKT(0x430b),
0088     PSIL_PDMA_XY_PKT(0x430c),
0089     PSIL_PDMA_XY_PKT(0x430d),
0090     /* PDMA_MAIN1 - UART0-6 */
0091     PSIL_PDMA_XY_PKT(0x4400),
0092     PSIL_PDMA_XY_PKT(0x4401),
0093     PSIL_PDMA_XY_PKT(0x4402),
0094     PSIL_PDMA_XY_PKT(0x4403),
0095     PSIL_PDMA_XY_PKT(0x4404),
0096     PSIL_PDMA_XY_PKT(0x4405),
0097     PSIL_PDMA_XY_PKT(0x4406),
0098     /* PDMA_MAIN2 - MCASP0-2 */
0099     PSIL_PDMA_MCASP(0x4500),
0100     PSIL_PDMA_MCASP(0x4501),
0101     PSIL_PDMA_MCASP(0x4502),
0102     /* CPSW3G */
0103     PSIL_ETHERNET(0x4600, 19, 19, 16),
0104     /* CSI2RX */
0105     PSIL_CSI2RX(0x4700),
0106     PSIL_CSI2RX(0x4701),
0107     PSIL_CSI2RX(0x4702),
0108     PSIL_CSI2RX(0x4703),
0109     PSIL_CSI2RX(0x4704),
0110     PSIL_CSI2RX(0x4705),
0111     PSIL_CSI2RX(0x4706),
0112     PSIL_CSI2RX(0x4707),
0113     PSIL_CSI2RX(0x4708),
0114     PSIL_CSI2RX(0x4709),
0115     PSIL_CSI2RX(0x470a),
0116     PSIL_CSI2RX(0x470b),
0117     PSIL_CSI2RX(0x470c),
0118     PSIL_CSI2RX(0x470d),
0119     PSIL_CSI2RX(0x470e),
0120     PSIL_CSI2RX(0x470f),
0121     PSIL_CSI2RX(0x4710),
0122     PSIL_CSI2RX(0x4711),
0123     PSIL_CSI2RX(0x4712),
0124     PSIL_CSI2RX(0x4713),
0125     PSIL_CSI2RX(0x4714),
0126     PSIL_CSI2RX(0x4715),
0127     PSIL_CSI2RX(0x4716),
0128     PSIL_CSI2RX(0x4717),
0129     PSIL_CSI2RX(0x4718),
0130     PSIL_CSI2RX(0x4719),
0131     PSIL_CSI2RX(0x471a),
0132     PSIL_CSI2RX(0x471b),
0133     PSIL_CSI2RX(0x471c),
0134     PSIL_CSI2RX(0x471d),
0135     PSIL_CSI2RX(0x471e),
0136     PSIL_CSI2RX(0x471f),
0137 };
0138
0139 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
0140 static struct psil_ep am62_dst_ep_map[] = {
0141     /* SAUL */
0142     PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
0143     PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
0144     /* PDMA_MAIN0 - SPI0-3 */
0145     PSIL_PDMA_XY_PKT(0xc302),
0146     PSIL_PDMA_XY_PKT(0xc303),
0147     PSIL_PDMA_XY_PKT(0xc304),
0148     PSIL_PDMA_XY_PKT(0xc305),
0149     PSIL_PDMA_XY_PKT(0xc306),
0150     PSIL_PDMA_XY_PKT(0xc307),
0151     PSIL_PDMA_XY_PKT(0xc308),
0152     PSIL_PDMA_XY_PKT(0xc309),
0153     PSIL_PDMA_XY_PKT(0xc30a),
0154     PSIL_PDMA_XY_PKT(0xc30b),
0155     PSIL_PDMA_XY_PKT(0xc30c),
0156     PSIL_PDMA_XY_PKT(0xc30d),
0157     /* PDMA_MAIN1 - UART0-6 */
0158     PSIL_PDMA_XY_PKT(0xc400),
0159     PSIL_PDMA_XY_PKT(0xc401),
0160     PSIL_PDMA_XY_PKT(0xc402),
0161     PSIL_PDMA_XY_PKT(0xc403),
0162     PSIL_PDMA_XY_PKT(0xc404),
0163     PSIL_PDMA_XY_PKT(0xc405),
0164     PSIL_PDMA_XY_PKT(0xc406),
0165     /* PDMA_MAIN2 - MCASP0-2 */
0166     PSIL_PDMA_MCASP(0xc500),
0167     PSIL_PDMA_MCASP(0xc501),
0168     PSIL_PDMA_MCASP(0xc502),
0169     /* CPSW3G */
0170     PSIL_ETHERNET(0xc600, 19, 19, 8),
0171     PSIL_ETHERNET(0xc601, 20, 27, 8),
0172     PSIL_ETHERNET(0xc602, 21, 35, 8),
0173     PSIL_ETHERNET(0xc603, 22, 43, 8),
0174     PSIL_ETHERNET(0xc604, 23, 51, 8),
0175     PSIL_ETHERNET(0xc605, 24, 59, 8),
0176     PSIL_ETHERNET(0xc606, 25, 67, 8),
0177     PSIL_ETHERNET(0xc607, 26, 75, 8),
0178 };
0179
0180 struct psil_ep_map am62_ep_map = {
0181     .name = "am62",
0182     .src = am62_src_ep_map,
0183     .src_count = ARRAY_SIZE(am62_src_ep_map),
0184     .dst = am62_dst_ep_map,
0185     .dst_count = ARRAY_SIZE(am62_dst_ep_map),
0186 };