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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
0004  * Author: Sugar <shuge@allwinnertech.com>
0005  *
0006  * Copyright (C) 2014 Maxime Ripard
0007  * Maxime Ripard <maxime.ripard@free-electrons.com>
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/dmaengine.h>
0013 #include <linux/dmapool.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/module.h>
0016 #include <linux/of_dma.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/reset.h>
0020 #include <linux/slab.h>
0021 #include <linux/types.h>
0022 
0023 #include "virt-dma.h"
0024 
0025 /*
0026  * Common registers
0027  */
0028 #define DMA_IRQ_EN(x)       ((x) * 0x04)
0029 #define DMA_IRQ_HALF            BIT(0)
0030 #define DMA_IRQ_PKG         BIT(1)
0031 #define DMA_IRQ_QUEUE           BIT(2)
0032 
0033 #define DMA_IRQ_CHAN_NR         8
0034 #define DMA_IRQ_CHAN_WIDTH      4
0035 
0036 
0037 #define DMA_IRQ_STAT(x)     ((x) * 0x04 + 0x10)
0038 
0039 #define DMA_STAT        0x30
0040 
0041 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */
0042 #define DMA_MAX_CHANNELS    (DMA_IRQ_CHAN_NR * 0x10 / 4)
0043 
0044 /*
0045  * sun8i specific registers
0046  */
0047 #define SUN8I_DMA_GATE      0x20
0048 #define SUN8I_DMA_GATE_ENABLE   0x4
0049 
0050 #define SUNXI_H3_SECURE_REG     0x20
0051 #define SUNXI_H3_DMA_GATE       0x28
0052 #define SUNXI_H3_DMA_GATE_ENABLE    0x4
0053 /*
0054  * Channels specific registers
0055  */
0056 #define DMA_CHAN_ENABLE     0x00
0057 #define DMA_CHAN_ENABLE_START       BIT(0)
0058 #define DMA_CHAN_ENABLE_STOP        0
0059 
0060 #define DMA_CHAN_PAUSE      0x04
0061 #define DMA_CHAN_PAUSE_PAUSE        BIT(1)
0062 #define DMA_CHAN_PAUSE_RESUME       0
0063 
0064 #define DMA_CHAN_LLI_ADDR   0x08
0065 
0066 #define DMA_CHAN_CUR_CFG    0x0c
0067 #define DMA_CHAN_MAX_DRQ_A31        0x1f
0068 #define DMA_CHAN_MAX_DRQ_H6     0x3f
0069 #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
0070 #define DMA_CHAN_CFG_SRC_DRQ_H6(x)  ((x) & DMA_CHAN_MAX_DRQ_H6)
0071 #define DMA_CHAN_CFG_SRC_MODE_A31(x)    (((x) & 0x1) << 5)
0072 #define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8)
0073 #define DMA_CHAN_CFG_SRC_BURST_A31(x)   (((x) & 0x3) << 7)
0074 #define DMA_CHAN_CFG_SRC_BURST_H3(x)    (((x) & 0x3) << 6)
0075 #define DMA_CHAN_CFG_SRC_WIDTH(x)   (((x) & 0x3) << 9)
0076 
0077 #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
0078 #define DMA_CHAN_CFG_DST_DRQ_H6(x)  (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
0079 #define DMA_CHAN_CFG_DST_MODE_A31(x)    (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
0080 #define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
0081 #define DMA_CHAN_CFG_DST_BURST_A31(x)   (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
0082 #define DMA_CHAN_CFG_DST_BURST_H3(x)    (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
0083 #define DMA_CHAN_CFG_DST_WIDTH(x)   (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
0084 
0085 #define DMA_CHAN_CUR_SRC    0x10
0086 
0087 #define DMA_CHAN_CUR_DST    0x14
0088 
0089 #define DMA_CHAN_CUR_CNT    0x18
0090 
0091 #define DMA_CHAN_CUR_PARA   0x1c
0092 
0093 /*
0094  * LLI address mangling
0095  *
0096  * The LLI link physical address is also mangled, but we avoid dealing
0097  * with that by allocating LLIs from the DMA32 zone.
0098  */
0099 #define SRC_HIGH_ADDR(x)        (((x) & 0x3U) << 16)
0100 #define DST_HIGH_ADDR(x)        (((x) & 0x3U) << 18)
0101 
0102 /*
0103  * Various hardware related defines
0104  */
0105 #define LLI_LAST_ITEM   0xfffff800
0106 #define NORMAL_WAIT 8
0107 #define DRQ_SDRAM   1
0108 #define LINEAR_MODE     0
0109 #define IO_MODE         1
0110 
0111 /* forward declaration */
0112 struct sun6i_dma_dev;
0113 
0114 /*
0115  * Hardware channels / ports representation
0116  *
0117  * The hardware is used in several SoCs, with differing numbers
0118  * of channels and endpoints. This structure ties those numbers
0119  * to a certain compatible string.
0120  */
0121 struct sun6i_dma_config {
0122     u32 nr_max_channels;
0123     u32 nr_max_requests;
0124     u32 nr_max_vchans;
0125     /*
0126      * In the datasheets/user manuals of newer Allwinner SoCs, a special
0127      * bit (bit 2 at register 0x20) is present.
0128      * It's named "DMA MCLK interface circuit auto gating bit" in the
0129      * documents, and the footnote of this register says that this bit
0130      * should be set up when initializing the DMA controller.
0131      * Allwinner A23/A33 user manuals do not have this bit documented,
0132      * however these SoCs really have and need this bit, as seen in the
0133      * BSP kernel source code.
0134      */
0135     void (*clock_autogate_enable)(struct sun6i_dma_dev *);
0136     void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
0137     void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
0138     void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
0139     u32 src_burst_lengths;
0140     u32 dst_burst_lengths;
0141     u32 src_addr_widths;
0142     u32 dst_addr_widths;
0143     bool has_high_addr;
0144     bool has_mbus_clk;
0145 };
0146 
0147 /*
0148  * Hardware representation of the LLI
0149  *
0150  * The hardware will be fed the physical address of this structure,
0151  * and read its content in order to start the transfer.
0152  */
0153 struct sun6i_dma_lli {
0154     u32         cfg;
0155     u32         src;
0156     u32         dst;
0157     u32         len;
0158     u32         para;
0159     u32         p_lli_next;
0160 
0161     /*
0162      * This field is not used by the DMA controller, but will be
0163      * used by the CPU to go through the list (mostly for dumping
0164      * or freeing it).
0165      */
0166     struct sun6i_dma_lli    *v_lli_next;
0167 };
0168 
0169 
0170 struct sun6i_desc {
0171     struct virt_dma_desc    vd;
0172     dma_addr_t      p_lli;
0173     struct sun6i_dma_lli    *v_lli;
0174 };
0175 
0176 struct sun6i_pchan {
0177     u32         idx;
0178     void __iomem        *base;
0179     struct sun6i_vchan  *vchan;
0180     struct sun6i_desc   *desc;
0181     struct sun6i_desc   *done;
0182 };
0183 
0184 struct sun6i_vchan {
0185     struct virt_dma_chan    vc;
0186     struct list_head    node;
0187     struct dma_slave_config cfg;
0188     struct sun6i_pchan  *phy;
0189     u8          port;
0190     u8          irq_type;
0191     bool            cyclic;
0192 };
0193 
0194 struct sun6i_dma_dev {
0195     struct dma_device   slave;
0196     void __iomem        *base;
0197     struct clk      *clk;
0198     struct clk      *clk_mbus;
0199     int         irq;
0200     spinlock_t      lock;
0201     struct reset_control    *rstc;
0202     struct tasklet_struct   task;
0203     atomic_t        tasklet_shutdown;
0204     struct list_head    pending;
0205     struct dma_pool     *pool;
0206     struct sun6i_pchan  *pchans;
0207     struct sun6i_vchan  *vchans;
0208     const struct sun6i_dma_config *cfg;
0209     u32         num_pchans;
0210     u32         num_vchans;
0211     u32         max_request;
0212 };
0213 
0214 static struct device *chan2dev(struct dma_chan *chan)
0215 {
0216     return &chan->dev->device;
0217 }
0218 
0219 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
0220 {
0221     return container_of(d, struct sun6i_dma_dev, slave);
0222 }
0223 
0224 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
0225 {
0226     return container_of(chan, struct sun6i_vchan, vc.chan);
0227 }
0228 
0229 static inline struct sun6i_desc *
0230 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
0231 {
0232     return container_of(tx, struct sun6i_desc, vd.tx);
0233 }
0234 
0235 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
0236 {
0237     dev_dbg(sdev->slave.dev, "Common register:\n"
0238         "\tmask0(%04x): 0x%08x\n"
0239         "\tmask1(%04x): 0x%08x\n"
0240         "\tpend0(%04x): 0x%08x\n"
0241         "\tpend1(%04x): 0x%08x\n"
0242         "\tstats(%04x): 0x%08x\n",
0243         DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
0244         DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
0245         DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
0246         DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
0247         DMA_STAT, readl(sdev->base + DMA_STAT));
0248 }
0249 
0250 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
0251                         struct sun6i_pchan *pchan)
0252 {
0253     dev_dbg(sdev->slave.dev, "Chan %d reg:\n"
0254         "\t___en(%04x): \t0x%08x\n"
0255         "\tpause(%04x): \t0x%08x\n"
0256         "\tstart(%04x): \t0x%08x\n"
0257         "\t__cfg(%04x): \t0x%08x\n"
0258         "\t__src(%04x): \t0x%08x\n"
0259         "\t__dst(%04x): \t0x%08x\n"
0260         "\tcount(%04x): \t0x%08x\n"
0261         "\t_para(%04x): \t0x%08x\n\n",
0262         pchan->idx,
0263         DMA_CHAN_ENABLE,
0264         readl(pchan->base + DMA_CHAN_ENABLE),
0265         DMA_CHAN_PAUSE,
0266         readl(pchan->base + DMA_CHAN_PAUSE),
0267         DMA_CHAN_LLI_ADDR,
0268         readl(pchan->base + DMA_CHAN_LLI_ADDR),
0269         DMA_CHAN_CUR_CFG,
0270         readl(pchan->base + DMA_CHAN_CUR_CFG),
0271         DMA_CHAN_CUR_SRC,
0272         readl(pchan->base + DMA_CHAN_CUR_SRC),
0273         DMA_CHAN_CUR_DST,
0274         readl(pchan->base + DMA_CHAN_CUR_DST),
0275         DMA_CHAN_CUR_CNT,
0276         readl(pchan->base + DMA_CHAN_CUR_CNT),
0277         DMA_CHAN_CUR_PARA,
0278         readl(pchan->base + DMA_CHAN_CUR_PARA));
0279 }
0280 
0281 static inline s8 convert_burst(u32 maxburst)
0282 {
0283     switch (maxburst) {
0284     case 1:
0285         return 0;
0286     case 4:
0287         return 1;
0288     case 8:
0289         return 2;
0290     case 16:
0291         return 3;
0292     default:
0293         return -EINVAL;
0294     }
0295 }
0296 
0297 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
0298 {
0299     return ilog2(addr_width);
0300 }
0301 
0302 static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
0303 {
0304     writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
0305 }
0306 
0307 static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
0308 {
0309     writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
0310 }
0311 
0312 static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst)
0313 {
0314     *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
0315           DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
0316 }
0317 
0318 static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
0319 {
0320     *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
0321           DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
0322 }
0323 
0324 static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
0325 {
0326     *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
0327           DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
0328 }
0329 
0330 static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
0331 {
0332     *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
0333           DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
0334 }
0335 
0336 static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
0337 {
0338     *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
0339           DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
0340 }
0341 
0342 static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
0343 {
0344     *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
0345           DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
0346 }
0347 
0348 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
0349 {
0350     struct sun6i_desc *txd = pchan->desc;
0351     struct sun6i_dma_lli *lli;
0352     size_t bytes;
0353     dma_addr_t pos;
0354 
0355     pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
0356     bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
0357 
0358     if (pos == LLI_LAST_ITEM)
0359         return bytes;
0360 
0361     for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
0362         if (lli->p_lli_next == pos) {
0363             for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
0364                 bytes += lli->len;
0365             break;
0366         }
0367     }
0368 
0369     return bytes;
0370 }
0371 
0372 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
0373                    struct sun6i_dma_lli *next,
0374                    dma_addr_t next_phy,
0375                    struct sun6i_desc *txd)
0376 {
0377     if ((!prev && !txd) || !next)
0378         return NULL;
0379 
0380     if (!prev) {
0381         txd->p_lli = next_phy;
0382         txd->v_lli = next;
0383     } else {
0384         prev->p_lli_next = next_phy;
0385         prev->v_lli_next = next;
0386     }
0387 
0388     next->p_lli_next = LLI_LAST_ITEM;
0389     next->v_lli_next = NULL;
0390 
0391     return next;
0392 }
0393 
0394 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
0395                       struct sun6i_dma_lli *v_lli,
0396                       dma_addr_t p_lli)
0397 {
0398     dev_dbg(chan2dev(&vchan->vc.chan),
0399         "\n\tdesc:\tp - %pad v - 0x%p\n"
0400         "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
0401         "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
0402         &p_lli, v_lli,
0403         v_lli->cfg, v_lli->src, v_lli->dst,
0404         v_lli->len, v_lli->para, v_lli->p_lli_next);
0405 }
0406 
0407 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
0408 {
0409     struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
0410     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
0411     struct sun6i_dma_lli *v_lli, *v_next;
0412     dma_addr_t p_lli, p_next;
0413 
0414     if (unlikely(!txd))
0415         return;
0416 
0417     p_lli = txd->p_lli;
0418     v_lli = txd->v_lli;
0419 
0420     while (v_lli) {
0421         v_next = v_lli->v_lli_next;
0422         p_next = v_lli->p_lli_next;
0423 
0424         dma_pool_free(sdev->pool, v_lli, p_lli);
0425 
0426         v_lli = v_next;
0427         p_lli = p_next;
0428     }
0429 
0430     kfree(txd);
0431 }
0432 
0433 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
0434 {
0435     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
0436     struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
0437     struct sun6i_pchan *pchan = vchan->phy;
0438     u32 irq_val, irq_reg, irq_offset;
0439 
0440     if (!pchan)
0441         return -EAGAIN;
0442 
0443     if (!desc) {
0444         pchan->desc = NULL;
0445         pchan->done = NULL;
0446         return -EAGAIN;
0447     }
0448 
0449     list_del(&desc->node);
0450 
0451     pchan->desc = to_sun6i_desc(&desc->tx);
0452     pchan->done = NULL;
0453 
0454     sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli);
0455 
0456     irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
0457     irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
0458 
0459     vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
0460 
0461     irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
0462     irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
0463             (irq_offset * DMA_IRQ_CHAN_WIDTH));
0464     irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
0465     writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
0466 
0467     writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
0468     writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
0469 
0470     sun6i_dma_dump_com_regs(sdev);
0471     sun6i_dma_dump_chan_regs(sdev, pchan);
0472 
0473     return 0;
0474 }
0475 
0476 static void sun6i_dma_tasklet(struct tasklet_struct *t)
0477 {
0478     struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task);
0479     struct sun6i_vchan *vchan;
0480     struct sun6i_pchan *pchan;
0481     unsigned int pchan_alloc = 0;
0482     unsigned int pchan_idx;
0483 
0484     list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
0485         spin_lock_irq(&vchan->vc.lock);
0486 
0487         pchan = vchan->phy;
0488 
0489         if (pchan && pchan->done) {
0490             if (sun6i_dma_start_desc(vchan)) {
0491                 /*
0492                  * No current txd associated with this channel
0493                  */
0494                 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
0495                     pchan->idx);
0496 
0497                 /* Mark this channel free */
0498                 vchan->phy = NULL;
0499                 pchan->vchan = NULL;
0500             }
0501         }
0502         spin_unlock_irq(&vchan->vc.lock);
0503     }
0504 
0505     spin_lock_irq(&sdev->lock);
0506     for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
0507         pchan = &sdev->pchans[pchan_idx];
0508 
0509         if (pchan->vchan || list_empty(&sdev->pending))
0510             continue;
0511 
0512         vchan = list_first_entry(&sdev->pending,
0513                      struct sun6i_vchan, node);
0514 
0515         /* Remove from pending channels */
0516         list_del_init(&vchan->node);
0517         pchan_alloc |= BIT(pchan_idx);
0518 
0519         /* Mark this channel allocated */
0520         pchan->vchan = vchan;
0521         vchan->phy = pchan;
0522         dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
0523             pchan->idx, &vchan->vc);
0524     }
0525     spin_unlock_irq(&sdev->lock);
0526 
0527     for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
0528         if (!(pchan_alloc & BIT(pchan_idx)))
0529             continue;
0530 
0531         pchan = sdev->pchans + pchan_idx;
0532         vchan = pchan->vchan;
0533         if (vchan) {
0534             spin_lock_irq(&vchan->vc.lock);
0535             sun6i_dma_start_desc(vchan);
0536             spin_unlock_irq(&vchan->vc.lock);
0537         }
0538     }
0539 }
0540 
0541 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
0542 {
0543     struct sun6i_dma_dev *sdev = dev_id;
0544     struct sun6i_vchan *vchan;
0545     struct sun6i_pchan *pchan;
0546     int i, j, ret = IRQ_NONE;
0547     u32 status;
0548 
0549     for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) {
0550         status = readl(sdev->base + DMA_IRQ_STAT(i));
0551         if (!status)
0552             continue;
0553 
0554         dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
0555             i ? "high" : "low", status);
0556 
0557         writel(status, sdev->base + DMA_IRQ_STAT(i));
0558 
0559         for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
0560             pchan = sdev->pchans + j;
0561             vchan = pchan->vchan;
0562             if (vchan && (status & vchan->irq_type)) {
0563                 if (vchan->cyclic) {
0564                     vchan_cyclic_callback(&pchan->desc->vd);
0565                 } else {
0566                     spin_lock(&vchan->vc.lock);
0567                     vchan_cookie_complete(&pchan->desc->vd);
0568                     pchan->done = pchan->desc;
0569                     spin_unlock(&vchan->vc.lock);
0570                 }
0571             }
0572 
0573             status = status >> DMA_IRQ_CHAN_WIDTH;
0574         }
0575 
0576         if (!atomic_read(&sdev->tasklet_shutdown))
0577             tasklet_schedule(&sdev->task);
0578         ret = IRQ_HANDLED;
0579     }
0580 
0581     return ret;
0582 }
0583 
0584 static int set_config(struct sun6i_dma_dev *sdev,
0585             struct dma_slave_config *sconfig,
0586             enum dma_transfer_direction direction,
0587             u32 *p_cfg)
0588 {
0589     enum dma_slave_buswidth src_addr_width, dst_addr_width;
0590     u32 src_maxburst, dst_maxburst;
0591     s8 src_width, dst_width, src_burst, dst_burst;
0592 
0593     src_addr_width = sconfig->src_addr_width;
0594     dst_addr_width = sconfig->dst_addr_width;
0595     src_maxburst = sconfig->src_maxburst;
0596     dst_maxburst = sconfig->dst_maxburst;
0597 
0598     switch (direction) {
0599     case DMA_MEM_TO_DEV:
0600         if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
0601             src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0602         src_maxburst = src_maxburst ? src_maxburst : 8;
0603         break;
0604     case DMA_DEV_TO_MEM:
0605         if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
0606             dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0607         dst_maxburst = dst_maxburst ? dst_maxburst : 8;
0608         break;
0609     default:
0610         return -EINVAL;
0611     }
0612 
0613     if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths))
0614         return -EINVAL;
0615     if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths))
0616         return -EINVAL;
0617     if (!(BIT(src_maxburst) & sdev->cfg->src_burst_lengths))
0618         return -EINVAL;
0619     if (!(BIT(dst_maxburst) & sdev->cfg->dst_burst_lengths))
0620         return -EINVAL;
0621 
0622     src_width = convert_buswidth(src_addr_width);
0623     dst_width = convert_buswidth(dst_addr_width);
0624     dst_burst = convert_burst(dst_maxburst);
0625     src_burst = convert_burst(src_maxburst);
0626 
0627     *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
0628         DMA_CHAN_CFG_DST_WIDTH(dst_width);
0629 
0630     sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst);
0631 
0632     return 0;
0633 }
0634 
0635 static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev,
0636                       struct sun6i_dma_lli *v_lli,
0637                       dma_addr_t src, dma_addr_t dst)
0638 {
0639     v_lli->src = lower_32_bits(src);
0640     v_lli->dst = lower_32_bits(dst);
0641 
0642     if (sdev->cfg->has_high_addr)
0643         v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) |
0644                    DST_HIGH_ADDR(upper_32_bits(dst));
0645 }
0646 
0647 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
0648         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
0649         size_t len, unsigned long flags)
0650 {
0651     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0652     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0653     struct sun6i_dma_lli *v_lli;
0654     struct sun6i_desc *txd;
0655     dma_addr_t p_lli;
0656     s8 burst, width;
0657 
0658     dev_dbg(chan2dev(chan),
0659         "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
0660         __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
0661 
0662     if (!len)
0663         return NULL;
0664 
0665     txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
0666     if (!txd)
0667         return NULL;
0668 
0669     v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
0670     if (!v_lli) {
0671         dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
0672         goto err_txd_free;
0673     }
0674 
0675     v_lli->len = len;
0676     v_lli->para = NORMAL_WAIT;
0677     sun6i_dma_set_addr(sdev, v_lli, src, dest);
0678 
0679     burst = convert_burst(8);
0680     width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
0681     v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
0682         DMA_CHAN_CFG_DST_WIDTH(width);
0683 
0684     sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
0685     sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
0686     sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
0687 
0688     sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
0689 
0690     sun6i_dma_dump_lli(vchan, v_lli, p_lli);
0691 
0692     return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
0693 
0694 err_txd_free:
0695     kfree(txd);
0696     return NULL;
0697 }
0698 
0699 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
0700         struct dma_chan *chan, struct scatterlist *sgl,
0701         unsigned int sg_len, enum dma_transfer_direction dir,
0702         unsigned long flags, void *context)
0703 {
0704     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0705     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0706     struct dma_slave_config *sconfig = &vchan->cfg;
0707     struct sun6i_dma_lli *v_lli, *prev = NULL;
0708     struct sun6i_desc *txd;
0709     struct scatterlist *sg;
0710     dma_addr_t p_lli;
0711     u32 lli_cfg;
0712     int i, ret;
0713 
0714     if (!sgl)
0715         return NULL;
0716 
0717     ret = set_config(sdev, sconfig, dir, &lli_cfg);
0718     if (ret) {
0719         dev_err(chan2dev(chan), "Invalid DMA configuration\n");
0720         return NULL;
0721     }
0722 
0723     txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
0724     if (!txd)
0725         return NULL;
0726 
0727     for_each_sg(sgl, sg, sg_len, i) {
0728         v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
0729         if (!v_lli)
0730             goto err_lli_free;
0731 
0732         v_lli->len = sg_dma_len(sg);
0733         v_lli->para = NORMAL_WAIT;
0734 
0735         if (dir == DMA_MEM_TO_DEV) {
0736             sun6i_dma_set_addr(sdev, v_lli,
0737                        sg_dma_address(sg),
0738                        sconfig->dst_addr);
0739             v_lli->cfg = lli_cfg;
0740             sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
0741             sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
0742 
0743             dev_dbg(chan2dev(chan),
0744                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
0745                 __func__, vchan->vc.chan.chan_id,
0746                 &sconfig->dst_addr, &sg_dma_address(sg),
0747                 sg_dma_len(sg), flags);
0748 
0749         } else {
0750             sun6i_dma_set_addr(sdev, v_lli,
0751                        sconfig->src_addr,
0752                        sg_dma_address(sg));
0753             v_lli->cfg = lli_cfg;
0754             sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
0755             sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
0756 
0757             dev_dbg(chan2dev(chan),
0758                 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
0759                 __func__, vchan->vc.chan.chan_id,
0760                 &sg_dma_address(sg), &sconfig->src_addr,
0761                 sg_dma_len(sg), flags);
0762         }
0763 
0764         prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
0765     }
0766 
0767     dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
0768     for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
0769          p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
0770         sun6i_dma_dump_lli(vchan, v_lli, p_lli);
0771 
0772     return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
0773 
0774 err_lli_free:
0775     for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
0776          p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
0777         dma_pool_free(sdev->pool, v_lli, p_lli);
0778     kfree(txd);
0779     return NULL;
0780 }
0781 
0782 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
0783                     struct dma_chan *chan,
0784                     dma_addr_t buf_addr,
0785                     size_t buf_len,
0786                     size_t period_len,
0787                     enum dma_transfer_direction dir,
0788                     unsigned long flags)
0789 {
0790     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0791     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0792     struct dma_slave_config *sconfig = &vchan->cfg;
0793     struct sun6i_dma_lli *v_lli, *prev = NULL;
0794     struct sun6i_desc *txd;
0795     dma_addr_t p_lli;
0796     u32 lli_cfg;
0797     unsigned int i, periods = buf_len / period_len;
0798     int ret;
0799 
0800     ret = set_config(sdev, sconfig, dir, &lli_cfg);
0801     if (ret) {
0802         dev_err(chan2dev(chan), "Invalid DMA configuration\n");
0803         return NULL;
0804     }
0805 
0806     txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
0807     if (!txd)
0808         return NULL;
0809 
0810     for (i = 0; i < periods; i++) {
0811         v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
0812         if (!v_lli) {
0813             dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
0814             goto err_lli_free;
0815         }
0816 
0817         v_lli->len = period_len;
0818         v_lli->para = NORMAL_WAIT;
0819 
0820         if (dir == DMA_MEM_TO_DEV) {
0821             sun6i_dma_set_addr(sdev, v_lli,
0822                        buf_addr + period_len * i,
0823                        sconfig->dst_addr);
0824             v_lli->cfg = lli_cfg;
0825             sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
0826             sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
0827         } else {
0828             sun6i_dma_set_addr(sdev, v_lli,
0829                        sconfig->src_addr,
0830                        buf_addr + period_len * i);
0831             v_lli->cfg = lli_cfg;
0832             sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
0833             sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
0834         }
0835 
0836         prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
0837     }
0838 
0839     prev->p_lli_next = txd->p_lli;      /* cyclic list */
0840 
0841     vchan->cyclic = true;
0842 
0843     return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
0844 
0845 err_lli_free:
0846     for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
0847          p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
0848         dma_pool_free(sdev->pool, v_lli, p_lli);
0849     kfree(txd);
0850     return NULL;
0851 }
0852 
0853 static int sun6i_dma_config(struct dma_chan *chan,
0854                 struct dma_slave_config *config)
0855 {
0856     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0857 
0858     memcpy(&vchan->cfg, config, sizeof(*config));
0859 
0860     return 0;
0861 }
0862 
0863 static int sun6i_dma_pause(struct dma_chan *chan)
0864 {
0865     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0866     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0867     struct sun6i_pchan *pchan = vchan->phy;
0868 
0869     dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
0870 
0871     if (pchan) {
0872         writel(DMA_CHAN_PAUSE_PAUSE,
0873                pchan->base + DMA_CHAN_PAUSE);
0874     } else {
0875         spin_lock(&sdev->lock);
0876         list_del_init(&vchan->node);
0877         spin_unlock(&sdev->lock);
0878     }
0879 
0880     return 0;
0881 }
0882 
0883 static int sun6i_dma_resume(struct dma_chan *chan)
0884 {
0885     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0886     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0887     struct sun6i_pchan *pchan = vchan->phy;
0888     unsigned long flags;
0889 
0890     dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
0891 
0892     spin_lock_irqsave(&vchan->vc.lock, flags);
0893 
0894     if (pchan) {
0895         writel(DMA_CHAN_PAUSE_RESUME,
0896                pchan->base + DMA_CHAN_PAUSE);
0897     } else if (!list_empty(&vchan->vc.desc_issued)) {
0898         spin_lock(&sdev->lock);
0899         list_add_tail(&vchan->node, &sdev->pending);
0900         spin_unlock(&sdev->lock);
0901     }
0902 
0903     spin_unlock_irqrestore(&vchan->vc.lock, flags);
0904 
0905     return 0;
0906 }
0907 
0908 static int sun6i_dma_terminate_all(struct dma_chan *chan)
0909 {
0910     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0911     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0912     struct sun6i_pchan *pchan = vchan->phy;
0913     unsigned long flags;
0914     LIST_HEAD(head);
0915 
0916     spin_lock(&sdev->lock);
0917     list_del_init(&vchan->node);
0918     spin_unlock(&sdev->lock);
0919 
0920     spin_lock_irqsave(&vchan->vc.lock, flags);
0921 
0922     if (vchan->cyclic) {
0923         vchan->cyclic = false;
0924         if (pchan && pchan->desc) {
0925             struct virt_dma_desc *vd = &pchan->desc->vd;
0926             struct virt_dma_chan *vc = &vchan->vc;
0927 
0928             list_add_tail(&vd->node, &vc->desc_completed);
0929         }
0930     }
0931 
0932     vchan_get_all_descriptors(&vchan->vc, &head);
0933 
0934     if (pchan) {
0935         writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
0936         writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
0937 
0938         vchan->phy = NULL;
0939         pchan->vchan = NULL;
0940         pchan->desc = NULL;
0941         pchan->done = NULL;
0942     }
0943 
0944     spin_unlock_irqrestore(&vchan->vc.lock, flags);
0945 
0946     vchan_dma_desc_free_list(&vchan->vc, &head);
0947 
0948     return 0;
0949 }
0950 
0951 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
0952                        dma_cookie_t cookie,
0953                        struct dma_tx_state *state)
0954 {
0955     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0956     struct sun6i_pchan *pchan = vchan->phy;
0957     struct sun6i_dma_lli *lli;
0958     struct virt_dma_desc *vd;
0959     struct sun6i_desc *txd;
0960     enum dma_status ret;
0961     unsigned long flags;
0962     size_t bytes = 0;
0963 
0964     ret = dma_cookie_status(chan, cookie, state);
0965     if (ret == DMA_COMPLETE || !state)
0966         return ret;
0967 
0968     spin_lock_irqsave(&vchan->vc.lock, flags);
0969 
0970     vd = vchan_find_desc(&vchan->vc, cookie);
0971     txd = to_sun6i_desc(&vd->tx);
0972 
0973     if (vd) {
0974         for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
0975             bytes += lli->len;
0976     } else if (!pchan || !pchan->desc) {
0977         bytes = 0;
0978     } else {
0979         bytes = sun6i_get_chan_size(pchan);
0980     }
0981 
0982     spin_unlock_irqrestore(&vchan->vc.lock, flags);
0983 
0984     dma_set_residue(state, bytes);
0985 
0986     return ret;
0987 }
0988 
0989 static void sun6i_dma_issue_pending(struct dma_chan *chan)
0990 {
0991     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
0992     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
0993     unsigned long flags;
0994 
0995     spin_lock_irqsave(&vchan->vc.lock, flags);
0996 
0997     if (vchan_issue_pending(&vchan->vc)) {
0998         spin_lock(&sdev->lock);
0999 
1000         if (!vchan->phy && list_empty(&vchan->node)) {
1001             list_add_tail(&vchan->node, &sdev->pending);
1002             tasklet_schedule(&sdev->task);
1003             dev_dbg(chan2dev(chan), "vchan %p: issued\n",
1004                 &vchan->vc);
1005         }
1006 
1007         spin_unlock(&sdev->lock);
1008     } else {
1009         dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
1010             &vchan->vc);
1011     }
1012 
1013     spin_unlock_irqrestore(&vchan->vc.lock, flags);
1014 }
1015 
1016 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
1017 {
1018     struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
1019     struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
1020     unsigned long flags;
1021 
1022     spin_lock_irqsave(&sdev->lock, flags);
1023     list_del_init(&vchan->node);
1024     spin_unlock_irqrestore(&sdev->lock, flags);
1025 
1026     vchan_free_chan_resources(&vchan->vc);
1027 }
1028 
1029 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
1030                        struct of_dma *ofdma)
1031 {
1032     struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
1033     struct sun6i_vchan *vchan;
1034     struct dma_chan *chan;
1035     u8 port = dma_spec->args[0];
1036 
1037     if (port > sdev->max_request)
1038         return NULL;
1039 
1040     chan = dma_get_any_slave_channel(&sdev->slave);
1041     if (!chan)
1042         return NULL;
1043 
1044     vchan = to_sun6i_vchan(chan);
1045     vchan->port = port;
1046 
1047     return chan;
1048 }
1049 
1050 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
1051 {
1052     /* Disable all interrupts from DMA */
1053     writel(0, sdev->base + DMA_IRQ_EN(0));
1054     writel(0, sdev->base + DMA_IRQ_EN(1));
1055 
1056     /* Prevent spurious interrupts from scheduling the tasklet */
1057     atomic_inc(&sdev->tasklet_shutdown);
1058 
1059     /* Make sure we won't have any further interrupts */
1060     devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
1061 
1062     /* Actually prevent the tasklet from being scheduled */
1063     tasklet_kill(&sdev->task);
1064 }
1065 
1066 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
1067 {
1068     int i;
1069 
1070     for (i = 0; i < sdev->num_vchans; i++) {
1071         struct sun6i_vchan *vchan = &sdev->vchans[i];
1072 
1073         list_del(&vchan->vc.chan.device_node);
1074         tasklet_kill(&vchan->vc.task);
1075     }
1076 }
1077 
1078 /*
1079  * For A31:
1080  *
1081  * There's 16 physical channels that can work in parallel.
1082  *
1083  * However we have 30 different endpoints for our requests.
1084  *
1085  * Since the channels are able to handle only an unidirectional
1086  * transfer, we need to allocate more virtual channels so that
1087  * everyone can grab one channel.
1088  *
1089  * Some devices can't work in both direction (mostly because it
1090  * wouldn't make sense), so we have a bit fewer virtual channels than
1091  * 2 channels per endpoints.
1092  */
1093 
1094 static struct sun6i_dma_config sun6i_a31_dma_cfg = {
1095     .nr_max_channels = 16,
1096     .nr_max_requests = 30,
1097     .nr_max_vchans   = 53,
1098     .set_burst_length = sun6i_set_burst_length_a31,
1099     .set_drq          = sun6i_set_drq_a31,
1100     .set_mode         = sun6i_set_mode_a31,
1101     .src_burst_lengths = BIT(1) | BIT(8),
1102     .dst_burst_lengths = BIT(1) | BIT(8),
1103     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1104                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1105                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1106     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1107                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1108                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1109 };
1110 
1111 /*
1112  * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
1113  * and a total of 37 usable source and destination endpoints.
1114  */
1115 
1116 static struct sun6i_dma_config sun8i_a23_dma_cfg = {
1117     .nr_max_channels = 8,
1118     .nr_max_requests = 24,
1119     .nr_max_vchans   = 37,
1120     .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1121     .set_burst_length = sun6i_set_burst_length_a31,
1122     .set_drq          = sun6i_set_drq_a31,
1123     .set_mode         = sun6i_set_mode_a31,
1124     .src_burst_lengths = BIT(1) | BIT(8),
1125     .dst_burst_lengths = BIT(1) | BIT(8),
1126     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1127                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1128                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1129     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1130                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1131                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1132 };
1133 
1134 static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
1135     .nr_max_channels = 8,
1136     .nr_max_requests = 28,
1137     .nr_max_vchans   = 39,
1138     .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1139     .set_burst_length = sun6i_set_burst_length_a31,
1140     .set_drq          = sun6i_set_drq_a31,
1141     .set_mode         = sun6i_set_mode_a31,
1142     .src_burst_lengths = BIT(1) | BIT(8),
1143     .dst_burst_lengths = BIT(1) | BIT(8),
1144     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1145                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1146                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1147     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1148                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1149                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1150 };
1151 
1152 /*
1153  * The H3 has 12 physical channels, a maximum DRQ port id of 27,
1154  * and a total of 34 usable source and destination endpoints.
1155  * It also supports additional burst lengths and bus widths,
1156  * and the burst length fields have different offsets.
1157  */
1158 
1159 static struct sun6i_dma_config sun8i_h3_dma_cfg = {
1160     .nr_max_channels = 12,
1161     .nr_max_requests = 27,
1162     .nr_max_vchans   = 34,
1163     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1164     .set_burst_length = sun6i_set_burst_length_h3,
1165     .set_drq          = sun6i_set_drq_a31,
1166     .set_mode         = sun6i_set_mode_a31,
1167     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1168     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1169     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1170                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1171                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1172                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1173     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1174                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1175                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1176                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1177 };
1178 
1179 /*
1180  * The A64 binding uses the number of dma channels from the
1181  * device tree node.
1182  */
1183 static struct sun6i_dma_config sun50i_a64_dma_cfg = {
1184     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1185     .set_burst_length = sun6i_set_burst_length_h3,
1186     .set_drq          = sun6i_set_drq_a31,
1187     .set_mode         = sun6i_set_mode_a31,
1188     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1189     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1190     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1191                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1192                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1193                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1194     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1195                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1196                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1197                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1198 };
1199 
1200 /*
1201  * The A100 binding uses the number of dma channels from the
1202  * device tree node.
1203  */
1204 static struct sun6i_dma_config sun50i_a100_dma_cfg = {
1205     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1206     .set_burst_length = sun6i_set_burst_length_h3,
1207     .set_drq          = sun6i_set_drq_h6,
1208     .set_mode         = sun6i_set_mode_h6,
1209     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1210     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1211     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1212                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1213                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1214                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1215     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1216                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1217                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1218                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1219     .has_high_addr = true,
1220     .has_mbus_clk = true,
1221 };
1222 
1223 /*
1224  * The H6 binding uses the number of dma channels from the
1225  * device tree node.
1226  */
1227 static struct sun6i_dma_config sun50i_h6_dma_cfg = {
1228     .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1229     .set_burst_length = sun6i_set_burst_length_h3,
1230     .set_drq          = sun6i_set_drq_h6,
1231     .set_mode         = sun6i_set_mode_h6,
1232     .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1233     .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1234     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1235                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1236                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1237                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1238     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1239                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1240                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1241                  BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1242     .has_mbus_clk = true,
1243 };
1244 
1245 /*
1246  * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
1247  * and a total of 24 usable source and destination endpoints.
1248  */
1249 
1250 static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
1251     .nr_max_channels = 8,
1252     .nr_max_requests = 23,
1253     .nr_max_vchans   = 24,
1254     .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1255     .set_burst_length = sun6i_set_burst_length_a31,
1256     .set_drq          = sun6i_set_drq_a31,
1257     .set_mode         = sun6i_set_mode_a31,
1258     .src_burst_lengths = BIT(1) | BIT(8),
1259     .dst_burst_lengths = BIT(1) | BIT(8),
1260     .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1261                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1262                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1263     .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1264                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1265                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1266 };
1267 
1268 static const struct of_device_id sun6i_dma_match[] = {
1269     { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
1270     { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
1271     { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
1272     { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
1273     { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
1274     { .compatible = "allwinner,sun20i-d1-dma", .data = &sun50i_a100_dma_cfg },
1275     { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
1276     { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg },
1277     { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
1278     { /* sentinel */ }
1279 };
1280 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
1281 
1282 static int sun6i_dma_probe(struct platform_device *pdev)
1283 {
1284     struct device_node *np = pdev->dev.of_node;
1285     struct sun6i_dma_dev *sdc;
1286     struct resource *res;
1287     int ret, i;
1288 
1289     sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
1290     if (!sdc)
1291         return -ENOMEM;
1292 
1293     sdc->cfg = of_device_get_match_data(&pdev->dev);
1294     if (!sdc->cfg)
1295         return -ENODEV;
1296 
1297     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298     sdc->base = devm_ioremap_resource(&pdev->dev, res);
1299     if (IS_ERR(sdc->base))
1300         return PTR_ERR(sdc->base);
1301 
1302     sdc->irq = platform_get_irq(pdev, 0);
1303     if (sdc->irq < 0)
1304         return sdc->irq;
1305 
1306     sdc->clk = devm_clk_get(&pdev->dev, NULL);
1307     if (IS_ERR(sdc->clk)) {
1308         dev_err(&pdev->dev, "No clock specified\n");
1309         return PTR_ERR(sdc->clk);
1310     }
1311 
1312     if (sdc->cfg->has_mbus_clk) {
1313         sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
1314         if (IS_ERR(sdc->clk_mbus)) {
1315             dev_err(&pdev->dev, "No mbus clock specified\n");
1316             return PTR_ERR(sdc->clk_mbus);
1317         }
1318     }
1319 
1320     sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
1321     if (IS_ERR(sdc->rstc)) {
1322         dev_err(&pdev->dev, "No reset controller specified\n");
1323         return PTR_ERR(sdc->rstc);
1324     }
1325 
1326     sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1327                      sizeof(struct sun6i_dma_lli), 4, 0);
1328     if (!sdc->pool) {
1329         dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1330         return -ENOMEM;
1331     }
1332 
1333     platform_set_drvdata(pdev, sdc);
1334     INIT_LIST_HEAD(&sdc->pending);
1335     spin_lock_init(&sdc->lock);
1336 
1337     dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
1338     dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
1339     dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
1340     dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
1341 
1342     INIT_LIST_HEAD(&sdc->slave.channels);
1343     sdc->slave.device_free_chan_resources   = sun6i_dma_free_chan_resources;
1344     sdc->slave.device_tx_status     = sun6i_dma_tx_status;
1345     sdc->slave.device_issue_pending     = sun6i_dma_issue_pending;
1346     sdc->slave.device_prep_slave_sg     = sun6i_dma_prep_slave_sg;
1347     sdc->slave.device_prep_dma_memcpy   = sun6i_dma_prep_dma_memcpy;
1348     sdc->slave.device_prep_dma_cyclic   = sun6i_dma_prep_dma_cyclic;
1349     sdc->slave.copy_align           = DMAENGINE_ALIGN_4_BYTES;
1350     sdc->slave.device_config        = sun6i_dma_config;
1351     sdc->slave.device_pause         = sun6i_dma_pause;
1352     sdc->slave.device_resume        = sun6i_dma_resume;
1353     sdc->slave.device_terminate_all     = sun6i_dma_terminate_all;
1354     sdc->slave.src_addr_widths      = sdc->cfg->src_addr_widths;
1355     sdc->slave.dst_addr_widths      = sdc->cfg->dst_addr_widths;
1356     sdc->slave.directions           = BIT(DMA_DEV_TO_MEM) |
1357                           BIT(DMA_MEM_TO_DEV);
1358     sdc->slave.residue_granularity      = DMA_RESIDUE_GRANULARITY_BURST;
1359     sdc->slave.dev = &pdev->dev;
1360 
1361     sdc->num_pchans = sdc->cfg->nr_max_channels;
1362     sdc->num_vchans = sdc->cfg->nr_max_vchans;
1363     sdc->max_request = sdc->cfg->nr_max_requests;
1364 
1365     ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans);
1366     if (ret && !sdc->num_pchans) {
1367         dev_err(&pdev->dev, "Can't get dma-channels.\n");
1368         return ret;
1369     }
1370 
1371     ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
1372     if (ret && !sdc->max_request) {
1373         dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
1374              DMA_CHAN_MAX_DRQ_A31);
1375         sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
1376     }
1377 
1378     /*
1379      * If the number of vchans is not specified, derive it from the
1380      * highest port number, at most one channel per port and direction.
1381      */
1382     if (!sdc->num_vchans)
1383         sdc->num_vchans = 2 * (sdc->max_request + 1);
1384 
1385     sdc->pchans = devm_kcalloc(&pdev->dev, sdc->num_pchans,
1386                    sizeof(struct sun6i_pchan), GFP_KERNEL);
1387     if (!sdc->pchans)
1388         return -ENOMEM;
1389 
1390     sdc->vchans = devm_kcalloc(&pdev->dev, sdc->num_vchans,
1391                    sizeof(struct sun6i_vchan), GFP_KERNEL);
1392     if (!sdc->vchans)
1393         return -ENOMEM;
1394 
1395     tasklet_setup(&sdc->task, sun6i_dma_tasklet);
1396 
1397     for (i = 0; i < sdc->num_pchans; i++) {
1398         struct sun6i_pchan *pchan = &sdc->pchans[i];
1399 
1400         pchan->idx = i;
1401         pchan->base = sdc->base + 0x100 + i * 0x40;
1402     }
1403 
1404     for (i = 0; i < sdc->num_vchans; i++) {
1405         struct sun6i_vchan *vchan = &sdc->vchans[i];
1406 
1407         INIT_LIST_HEAD(&vchan->node);
1408         vchan->vc.desc_free = sun6i_dma_free_desc;
1409         vchan_init(&vchan->vc, &sdc->slave);
1410     }
1411 
1412     ret = reset_control_deassert(sdc->rstc);
1413     if (ret) {
1414         dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
1415         goto err_chan_free;
1416     }
1417 
1418     ret = clk_prepare_enable(sdc->clk);
1419     if (ret) {
1420         dev_err(&pdev->dev, "Couldn't enable the clock\n");
1421         goto err_reset_assert;
1422     }
1423 
1424     if (sdc->cfg->has_mbus_clk) {
1425         ret = clk_prepare_enable(sdc->clk_mbus);
1426         if (ret) {
1427             dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
1428             goto err_clk_disable;
1429         }
1430     }
1431 
1432     ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
1433                    dev_name(&pdev->dev), sdc);
1434     if (ret) {
1435         dev_err(&pdev->dev, "Cannot request IRQ\n");
1436         goto err_mbus_clk_disable;
1437     }
1438 
1439     ret = dma_async_device_register(&sdc->slave);
1440     if (ret) {
1441         dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
1442         goto err_irq_disable;
1443     }
1444 
1445     ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
1446                      sdc);
1447     if (ret) {
1448         dev_err(&pdev->dev, "of_dma_controller_register failed\n");
1449         goto err_dma_unregister;
1450     }
1451 
1452     if (sdc->cfg->clock_autogate_enable)
1453         sdc->cfg->clock_autogate_enable(sdc);
1454 
1455     return 0;
1456 
1457 err_dma_unregister:
1458     dma_async_device_unregister(&sdc->slave);
1459 err_irq_disable:
1460     sun6i_kill_tasklet(sdc);
1461 err_mbus_clk_disable:
1462     clk_disable_unprepare(sdc->clk_mbus);
1463 err_clk_disable:
1464     clk_disable_unprepare(sdc->clk);
1465 err_reset_assert:
1466     reset_control_assert(sdc->rstc);
1467 err_chan_free:
1468     sun6i_dma_free(sdc);
1469     return ret;
1470 }
1471 
1472 static int sun6i_dma_remove(struct platform_device *pdev)
1473 {
1474     struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
1475 
1476     of_dma_controller_free(pdev->dev.of_node);
1477     dma_async_device_unregister(&sdc->slave);
1478 
1479     sun6i_kill_tasklet(sdc);
1480 
1481     clk_disable_unprepare(sdc->clk_mbus);
1482     clk_disable_unprepare(sdc->clk);
1483     reset_control_assert(sdc->rstc);
1484 
1485     sun6i_dma_free(sdc);
1486 
1487     return 0;
1488 }
1489 
1490 static struct platform_driver sun6i_dma_driver = {
1491     .probe      = sun6i_dma_probe,
1492     .remove     = sun6i_dma_remove,
1493     .driver = {
1494         .name       = "sun6i-dma",
1495         .of_match_table = sun6i_dma_match,
1496     },
1497 };
1498 module_platform_driver(sun6i_dma_driver);
1499 
1500 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1501 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1502 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1503 MODULE_LICENSE("GPL");
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