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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Renesas SuperH DMA Engine support
0004  *
0005  * base is drivers/dma/flsdma.c
0006  *
0007  * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
0008  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
0009  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
0010  * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
0011  *
0012  * - DMA of SuperH does not have Hardware DMA chain mode.
0013  * - MAX DMA size is 16MB.
0014  *
0015  */
0016 
0017 #include <linux/delay.h>
0018 #include <linux/dmaengine.h>
0019 #include <linux/err.h>
0020 #include <linux/init.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/kdebug.h>
0023 #include <linux/module.h>
0024 #include <linux/notifier.h>
0025 #include <linux/of.h>
0026 #include <linux/of_device.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/pm_runtime.h>
0029 #include <linux/rculist.h>
0030 #include <linux/sh_dma.h>
0031 #include <linux/slab.h>
0032 #include <linux/spinlock.h>
0033 
0034 #include "../dmaengine.h"
0035 #include "shdma.h"
0036 
0037 /* DMA registers */
0038 #define SAR 0x00    /* Source Address Register */
0039 #define DAR 0x04    /* Destination Address Register */
0040 #define TCR 0x08    /* Transfer Count Register */
0041 #define CHCR    0x0C    /* Channel Control Register */
0042 #define DMAOR   0x40    /* DMA Operation Register */
0043 
0044 #define TEND    0x18 /* USB-DMAC */
0045 
0046 #define SH_DMAE_DRV_NAME "sh-dma-engine"
0047 
0048 /* Default MEMCPY transfer size = 2^2 = 4 bytes */
0049 #define LOG2_DEFAULT_XFER_SIZE  2
0050 #define SH_DMA_SLAVE_NUMBER 256
0051 #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1)
0052 
0053 /*
0054  * Used for write-side mutual exclusion for the global device list,
0055  * read-side synchronization by way of RCU, and per-controller data.
0056  */
0057 static DEFINE_SPINLOCK(sh_dmae_lock);
0058 static LIST_HEAD(sh_dmae_devices);
0059 
0060 /*
0061  * Different DMAC implementations provide different ways to clear DMA channels:
0062  * (1) none - no CHCLR registers are available
0063  * (2) one CHCLR register per channel - 0 has to be written to it to clear
0064  *     channel buffers
0065  * (3) one CHCLR per several channels - 1 has to be written to the bit,
0066  *     corresponding to the specific channel to reset it
0067  */
0068 static void channel_clear(struct sh_dmae_chan *sh_dc)
0069 {
0070     struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
0071     const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel +
0072         sh_dc->shdma_chan.id;
0073     u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0;
0074 
0075     __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset);
0076 }
0077 
0078 static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
0079 {
0080     __raw_writel(data, sh_dc->base + reg);
0081 }
0082 
0083 static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
0084 {
0085     return __raw_readl(sh_dc->base + reg);
0086 }
0087 
0088 static u16 dmaor_read(struct sh_dmae_device *shdev)
0089 {
0090     void __iomem *addr = shdev->chan_reg + DMAOR;
0091 
0092     if (shdev->pdata->dmaor_is_32bit)
0093         return __raw_readl(addr);
0094     else
0095         return __raw_readw(addr);
0096 }
0097 
0098 static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
0099 {
0100     void __iomem *addr = shdev->chan_reg + DMAOR;
0101 
0102     if (shdev->pdata->dmaor_is_32bit)
0103         __raw_writel(data, addr);
0104     else
0105         __raw_writew(data, addr);
0106 }
0107 
0108 static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
0109 {
0110     struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
0111 
0112     __raw_writel(data, sh_dc->base + shdev->chcr_offset);
0113 }
0114 
0115 static u32 chcr_read(struct sh_dmae_chan *sh_dc)
0116 {
0117     struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
0118 
0119     return __raw_readl(sh_dc->base + shdev->chcr_offset);
0120 }
0121 
0122 /*
0123  * Reset DMA controller
0124  *
0125  * SH7780 has two DMAOR register
0126  */
0127 static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
0128 {
0129     unsigned short dmaor;
0130     unsigned long flags;
0131 
0132     spin_lock_irqsave(&sh_dmae_lock, flags);
0133 
0134     dmaor = dmaor_read(shdev);
0135     dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
0136 
0137     spin_unlock_irqrestore(&sh_dmae_lock, flags);
0138 }
0139 
0140 static int sh_dmae_rst(struct sh_dmae_device *shdev)
0141 {
0142     unsigned short dmaor;
0143     unsigned long flags;
0144 
0145     spin_lock_irqsave(&sh_dmae_lock, flags);
0146 
0147     dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
0148 
0149     if (shdev->pdata->chclr_present) {
0150         int i;
0151         for (i = 0; i < shdev->pdata->channel_num; i++) {
0152             struct sh_dmae_chan *sh_chan = shdev->chan[i];
0153             if (sh_chan)
0154                 channel_clear(sh_chan);
0155         }
0156     }
0157 
0158     dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
0159 
0160     dmaor = dmaor_read(shdev);
0161 
0162     spin_unlock_irqrestore(&sh_dmae_lock, flags);
0163 
0164     if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
0165         dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n");
0166         return -EIO;
0167     }
0168     if (shdev->pdata->dmaor_init & ~dmaor)
0169         dev_warn(shdev->shdma_dev.dma_dev.dev,
0170              "DMAOR=0x%x hasn't latched the initial value 0x%x.\n",
0171              dmaor, shdev->pdata->dmaor_init);
0172     return 0;
0173 }
0174 
0175 static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
0176 {
0177     u32 chcr = chcr_read(sh_chan);
0178 
0179     if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
0180         return true; /* working */
0181 
0182     return false; /* waiting */
0183 }
0184 
0185 static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
0186 {
0187     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0188     const struct sh_dmae_pdata *pdata = shdev->pdata;
0189     int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
0190         ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
0191 
0192     if (cnt >= pdata->ts_shift_num)
0193         cnt = 0;
0194 
0195     return pdata->ts_shift[cnt];
0196 }
0197 
0198 static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
0199 {
0200     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0201     const struct sh_dmae_pdata *pdata = shdev->pdata;
0202     int i;
0203 
0204     for (i = 0; i < pdata->ts_shift_num; i++)
0205         if (pdata->ts_shift[i] == l2size)
0206             break;
0207 
0208     if (i == pdata->ts_shift_num)
0209         i = 0;
0210 
0211     return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
0212         ((i << pdata->ts_high_shift) & pdata->ts_high_mask);
0213 }
0214 
0215 static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
0216 {
0217     sh_dmae_writel(sh_chan, hw->sar, SAR);
0218     sh_dmae_writel(sh_chan, hw->dar, DAR);
0219     sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR);
0220 }
0221 
0222 static void dmae_start(struct sh_dmae_chan *sh_chan)
0223 {
0224     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0225     u32 chcr = chcr_read(sh_chan);
0226 
0227     if (shdev->pdata->needs_tend_set)
0228         sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
0229 
0230     chcr |= CHCR_DE | shdev->chcr_ie_bit;
0231     chcr_write(sh_chan, chcr & ~CHCR_TE);
0232 }
0233 
0234 static void dmae_init(struct sh_dmae_chan *sh_chan)
0235 {
0236     /*
0237      * Default configuration for dual address memory-memory transfer.
0238      */
0239     u32 chcr = DM_INC | SM_INC | RS_AUTO | log2size_to_chcr(sh_chan,
0240                            LOG2_DEFAULT_XFER_SIZE);
0241     sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
0242     chcr_write(sh_chan, chcr);
0243 }
0244 
0245 static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
0246 {
0247     /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
0248     if (dmae_is_busy(sh_chan))
0249         return -EBUSY;
0250 
0251     sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
0252     chcr_write(sh_chan, val);
0253 
0254     return 0;
0255 }
0256 
0257 static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
0258 {
0259     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0260     const struct sh_dmae_pdata *pdata = shdev->pdata;
0261     const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id];
0262     void __iomem *addr = shdev->dmars;
0263     unsigned int shift = chan_pdata->dmars_bit;
0264 
0265     if (dmae_is_busy(sh_chan))
0266         return -EBUSY;
0267 
0268     if (pdata->no_dmars)
0269         return 0;
0270 
0271     /* in the case of a missing DMARS resource use first memory window */
0272     if (!addr)
0273         addr = shdev->chan_reg;
0274     addr += chan_pdata->dmars;
0275 
0276     __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
0277              addr);
0278 
0279     return 0;
0280 }
0281 
0282 static void sh_dmae_start_xfer(struct shdma_chan *schan,
0283                    struct shdma_desc *sdesc)
0284 {
0285     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0286                             shdma_chan);
0287     struct sh_dmae_desc *sh_desc = container_of(sdesc,
0288                     struct sh_dmae_desc, shdma_desc);
0289     dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n",
0290         sdesc->async_tx.cookie, sh_chan->shdma_chan.id,
0291         sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar);
0292     /* Get the ld start address from ld_queue */
0293     dmae_set_reg(sh_chan, &sh_desc->hw);
0294     dmae_start(sh_chan);
0295 }
0296 
0297 static bool sh_dmae_channel_busy(struct shdma_chan *schan)
0298 {
0299     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0300                             shdma_chan);
0301     return dmae_is_busy(sh_chan);
0302 }
0303 
0304 static void sh_dmae_setup_xfer(struct shdma_chan *schan,
0305                    int slave_id)
0306 {
0307     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0308                             shdma_chan);
0309 
0310     if (slave_id >= 0) {
0311         const struct sh_dmae_slave_config *cfg =
0312             sh_chan->config;
0313 
0314         dmae_set_dmars(sh_chan, cfg->mid_rid);
0315         dmae_set_chcr(sh_chan, cfg->chcr);
0316     } else {
0317         dmae_init(sh_chan);
0318     }
0319 }
0320 
0321 /*
0322  * Find a slave channel configuration from the contoller list by either a slave
0323  * ID in the non-DT case, or by a MID/RID value in the DT case
0324  */
0325 static const struct sh_dmae_slave_config *dmae_find_slave(
0326     struct sh_dmae_chan *sh_chan, int match)
0327 {
0328     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0329     const struct sh_dmae_pdata *pdata = shdev->pdata;
0330     const struct sh_dmae_slave_config *cfg;
0331     int i;
0332 
0333     if (!sh_chan->shdma_chan.dev->of_node) {
0334         if (match >= SH_DMA_SLAVE_NUMBER)
0335             return NULL;
0336 
0337         for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
0338             if (cfg->slave_id == match)
0339                 return cfg;
0340     } else {
0341         for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
0342             if (cfg->mid_rid == match) {
0343                 sh_chan->shdma_chan.slave_id = i;
0344                 return cfg;
0345             }
0346     }
0347 
0348     return NULL;
0349 }
0350 
0351 static int sh_dmae_set_slave(struct shdma_chan *schan,
0352                  int slave_id, dma_addr_t slave_addr, bool try)
0353 {
0354     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0355                             shdma_chan);
0356     const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id);
0357     if (!cfg)
0358         return -ENXIO;
0359 
0360     if (!try) {
0361         sh_chan->config = cfg;
0362         sh_chan->slave_addr = slave_addr ? : cfg->addr;
0363     }
0364 
0365     return 0;
0366 }
0367 
0368 static void dmae_halt(struct sh_dmae_chan *sh_chan)
0369 {
0370     struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
0371     u32 chcr = chcr_read(sh_chan);
0372 
0373     chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
0374     chcr_write(sh_chan, chcr);
0375 }
0376 
0377 static int sh_dmae_desc_setup(struct shdma_chan *schan,
0378                   struct shdma_desc *sdesc,
0379                   dma_addr_t src, dma_addr_t dst, size_t *len)
0380 {
0381     struct sh_dmae_desc *sh_desc = container_of(sdesc,
0382                     struct sh_dmae_desc, shdma_desc);
0383 
0384     if (*len > schan->max_xfer_len)
0385         *len = schan->max_xfer_len;
0386 
0387     sh_desc->hw.sar = src;
0388     sh_desc->hw.dar = dst;
0389     sh_desc->hw.tcr = *len;
0390 
0391     return 0;
0392 }
0393 
0394 static void sh_dmae_halt(struct shdma_chan *schan)
0395 {
0396     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0397                             shdma_chan);
0398     dmae_halt(sh_chan);
0399 }
0400 
0401 static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq)
0402 {
0403     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0404                             shdma_chan);
0405 
0406     if (!(chcr_read(sh_chan) & CHCR_TE))
0407         return false;
0408 
0409     /* DMA stop */
0410     dmae_halt(sh_chan);
0411 
0412     return true;
0413 }
0414 
0415 static size_t sh_dmae_get_partial(struct shdma_chan *schan,
0416                   struct shdma_desc *sdesc)
0417 {
0418     struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
0419                             shdma_chan);
0420     struct sh_dmae_desc *sh_desc = container_of(sdesc,
0421                     struct sh_dmae_desc, shdma_desc);
0422     return sh_desc->hw.tcr -
0423         (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift);
0424 }
0425 
0426 /* Called from error IRQ or NMI */
0427 static bool sh_dmae_reset(struct sh_dmae_device *shdev)
0428 {
0429     bool ret;
0430 
0431     /* halt the dma controller */
0432     sh_dmae_ctl_stop(shdev);
0433 
0434     /* We cannot detect, which channel caused the error, have to reset all */
0435     ret = shdma_reset(&shdev->shdma_dev);
0436 
0437     sh_dmae_rst(shdev);
0438 
0439     return ret;
0440 }
0441 
0442 static irqreturn_t sh_dmae_err(int irq, void *data)
0443 {
0444     struct sh_dmae_device *shdev = data;
0445 
0446     if (!(dmaor_read(shdev) & DMAOR_AE))
0447         return IRQ_NONE;
0448 
0449     sh_dmae_reset(shdev);
0450     return IRQ_HANDLED;
0451 }
0452 
0453 static bool sh_dmae_desc_completed(struct shdma_chan *schan,
0454                    struct shdma_desc *sdesc)
0455 {
0456     struct sh_dmae_chan *sh_chan = container_of(schan,
0457                     struct sh_dmae_chan, shdma_chan);
0458     struct sh_dmae_desc *sh_desc = container_of(sdesc,
0459                     struct sh_dmae_desc, shdma_desc);
0460     u32 sar_buf = sh_dmae_readl(sh_chan, SAR);
0461     u32 dar_buf = sh_dmae_readl(sh_chan, DAR);
0462 
0463     return  (sdesc->direction == DMA_DEV_TO_MEM &&
0464          (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) ||
0465         (sdesc->direction != DMA_DEV_TO_MEM &&
0466          (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf);
0467 }
0468 
0469 static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
0470 {
0471     /* Fast path out if NMIF is not asserted for this controller */
0472     if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
0473         return false;
0474 
0475     return sh_dmae_reset(shdev);
0476 }
0477 
0478 static int sh_dmae_nmi_handler(struct notifier_block *self,
0479                    unsigned long cmd, void *data)
0480 {
0481     struct sh_dmae_device *shdev;
0482     int ret = NOTIFY_DONE;
0483     bool triggered;
0484 
0485     /*
0486      * Only concern ourselves with NMI events.
0487      *
0488      * Normally we would check the die chain value, but as this needs
0489      * to be architecture independent, check for NMI context instead.
0490      */
0491     if (!in_nmi())
0492         return NOTIFY_DONE;
0493 
0494     rcu_read_lock();
0495     list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) {
0496         /*
0497          * Only stop if one of the controllers has NMIF asserted,
0498          * we do not want to interfere with regular address error
0499          * handling or NMI events that don't concern the DMACs.
0500          */
0501         triggered = sh_dmae_nmi_notify(shdev);
0502         if (triggered == true)
0503             ret = NOTIFY_OK;
0504     }
0505     rcu_read_unlock();
0506 
0507     return ret;
0508 }
0509 
0510 static struct notifier_block sh_dmae_nmi_notifier __read_mostly = {
0511     .notifier_call  = sh_dmae_nmi_handler,
0512 
0513     /* Run before NMI debug handler and KGDB */
0514     .priority   = 1,
0515 };
0516 
0517 static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
0518                     int irq, unsigned long flags)
0519 {
0520     const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
0521     struct shdma_dev *sdev = &shdev->shdma_dev;
0522     struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
0523     struct sh_dmae_chan *sh_chan;
0524     struct shdma_chan *schan;
0525     int err;
0526 
0527     sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan),
0528                    GFP_KERNEL);
0529     if (!sh_chan)
0530         return -ENOMEM;
0531 
0532     schan = &sh_chan->shdma_chan;
0533     schan->max_xfer_len = SH_DMA_TCR_MAX + 1;
0534 
0535     shdma_chan_probe(sdev, schan, id);
0536 
0537     sh_chan->base = shdev->chan_reg + chan_pdata->offset;
0538 
0539     /* set up channel irq */
0540     if (pdev->id >= 0)
0541         snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
0542              "sh-dmae%d.%d", pdev->id, id);
0543     else
0544         snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id),
0545              "sh-dma%d", id);
0546 
0547     err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id);
0548     if (err) {
0549         dev_err(sdev->dma_dev.dev,
0550             "DMA channel %d request_irq error %d\n",
0551             id, err);
0552         goto err_no_irq;
0553     }
0554 
0555     shdev->chan[id] = sh_chan;
0556     return 0;
0557 
0558 err_no_irq:
0559     /* remove from dmaengine device node */
0560     shdma_chan_remove(schan);
0561     return err;
0562 }
0563 
0564 static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
0565 {
0566     struct shdma_chan *schan;
0567     int i;
0568 
0569     shdma_for_each_chan(schan, &shdev->shdma_dev, i) {
0570         BUG_ON(!schan);
0571 
0572         shdma_chan_remove(schan);
0573     }
0574 }
0575 
0576 #ifdef CONFIG_PM
0577 static int sh_dmae_runtime_suspend(struct device *dev)
0578 {
0579     struct sh_dmae_device *shdev = dev_get_drvdata(dev);
0580 
0581     sh_dmae_ctl_stop(shdev);
0582     return 0;
0583 }
0584 
0585 static int sh_dmae_runtime_resume(struct device *dev)
0586 {
0587     struct sh_dmae_device *shdev = dev_get_drvdata(dev);
0588 
0589     return sh_dmae_rst(shdev);
0590 }
0591 #endif
0592 
0593 #ifdef CONFIG_PM_SLEEP
0594 static int sh_dmae_suspend(struct device *dev)
0595 {
0596     struct sh_dmae_device *shdev = dev_get_drvdata(dev);
0597 
0598     sh_dmae_ctl_stop(shdev);
0599     return 0;
0600 }
0601 
0602 static int sh_dmae_resume(struct device *dev)
0603 {
0604     struct sh_dmae_device *shdev = dev_get_drvdata(dev);
0605     int i, ret;
0606 
0607     ret = sh_dmae_rst(shdev);
0608     if (ret < 0)
0609         dev_err(dev, "Failed to reset!\n");
0610 
0611     for (i = 0; i < shdev->pdata->channel_num; i++) {
0612         struct sh_dmae_chan *sh_chan = shdev->chan[i];
0613 
0614         if (!sh_chan->shdma_chan.desc_num)
0615             continue;
0616 
0617         if (sh_chan->shdma_chan.slave_id >= 0) {
0618             const struct sh_dmae_slave_config *cfg = sh_chan->config;
0619             dmae_set_dmars(sh_chan, cfg->mid_rid);
0620             dmae_set_chcr(sh_chan, cfg->chcr);
0621         } else {
0622             dmae_init(sh_chan);
0623         }
0624     }
0625 
0626     return 0;
0627 }
0628 #endif
0629 
0630 static const struct dev_pm_ops sh_dmae_pm = {
0631     SET_SYSTEM_SLEEP_PM_OPS(sh_dmae_suspend, sh_dmae_resume)
0632     SET_RUNTIME_PM_OPS(sh_dmae_runtime_suspend, sh_dmae_runtime_resume,
0633                NULL)
0634 };
0635 
0636 static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
0637 {
0638     struct sh_dmae_chan *sh_chan = container_of(schan,
0639                     struct sh_dmae_chan, shdma_chan);
0640 
0641     /*
0642      * Implicit BUG_ON(!sh_chan->config)
0643      * This is an exclusive slave DMA operation, may only be called after a
0644      * successful slave configuration.
0645      */
0646     return sh_chan->slave_addr;
0647 }
0648 
0649 static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
0650 {
0651     return &((struct sh_dmae_desc *)buf)[i].shdma_desc;
0652 }
0653 
0654 static const struct shdma_ops sh_dmae_shdma_ops = {
0655     .desc_completed = sh_dmae_desc_completed,
0656     .halt_channel = sh_dmae_halt,
0657     .channel_busy = sh_dmae_channel_busy,
0658     .slave_addr = sh_dmae_slave_addr,
0659     .desc_setup = sh_dmae_desc_setup,
0660     .set_slave = sh_dmae_set_slave,
0661     .setup_xfer = sh_dmae_setup_xfer,
0662     .start_xfer = sh_dmae_start_xfer,
0663     .embedded_desc = sh_dmae_embedded_desc,
0664     .chan_irq = sh_dmae_chan_irq,
0665     .get_partial = sh_dmae_get_partial,
0666 };
0667 
0668 static int sh_dmae_probe(struct platform_device *pdev)
0669 {
0670     const enum dma_slave_buswidth widths =
0671         DMA_SLAVE_BUSWIDTH_1_BYTE   | DMA_SLAVE_BUSWIDTH_2_BYTES |
0672         DMA_SLAVE_BUSWIDTH_4_BYTES  | DMA_SLAVE_BUSWIDTH_8_BYTES |
0673         DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES;
0674     const struct sh_dmae_pdata *pdata;
0675     unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {};
0676     int chan_irq[SH_DMAE_MAX_CHANNELS];
0677     unsigned long irqflags = 0;
0678     int err, errirq, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
0679     struct sh_dmae_device *shdev;
0680     struct dma_device *dma_dev;
0681     struct resource *chan, *dmars, *errirq_res, *chanirq_res;
0682 
0683     if (pdev->dev.of_node)
0684         pdata = of_device_get_match_data(&pdev->dev);
0685     else
0686         pdata = dev_get_platdata(&pdev->dev);
0687 
0688     /* get platform data */
0689     if (!pdata || !pdata->channel_num)
0690         return -ENODEV;
0691 
0692     chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0693     /* DMARS area is optional */
0694     dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0695     /*
0696      * IRQ resources:
0697      * 1. there always must be at least one IRQ IO-resource. On SH4 it is
0698      *    the error IRQ, in which case it is the only IRQ in this resource:
0699      *    start == end. If it is the only IRQ resource, all channels also
0700      *    use the same IRQ.
0701      * 2. DMA channel IRQ resources can be specified one per resource or in
0702      *    ranges (start != end)
0703      * 3. iff all events (channels and, optionally, error) on this
0704      *    controller use the same IRQ, only one IRQ resource can be
0705      *    specified, otherwise there must be one IRQ per channel, even if
0706      *    some of them are equal
0707      * 4. if all IRQs on this controller are equal or if some specific IRQs
0708      *    specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
0709      *    requested with the IRQF_SHARED flag
0710      */
0711     errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
0712     if (!chan || !errirq_res)
0713         return -ENODEV;
0714 
0715     shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device),
0716                  GFP_KERNEL);
0717     if (!shdev)
0718         return -ENOMEM;
0719 
0720     dma_dev = &shdev->shdma_dev.dma_dev;
0721 
0722     shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan);
0723     if (IS_ERR(shdev->chan_reg))
0724         return PTR_ERR(shdev->chan_reg);
0725     if (dmars) {
0726         shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars);
0727         if (IS_ERR(shdev->dmars))
0728             return PTR_ERR(shdev->dmars);
0729     }
0730 
0731     dma_dev->src_addr_widths = widths;
0732     dma_dev->dst_addr_widths = widths;
0733     dma_dev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
0734     dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
0735 
0736     if (!pdata->slave_only)
0737         dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
0738     if (pdata->slave && pdata->slave_num)
0739         dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
0740 
0741     /* Default transfer size of 32 bytes requires 32-byte alignment */
0742     dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE;
0743 
0744     shdev->shdma_dev.ops = &sh_dmae_shdma_ops;
0745     shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc);
0746     err = shdma_init(&pdev->dev, &shdev->shdma_dev,
0747                   pdata->channel_num);
0748     if (err < 0)
0749         goto eshdma;
0750 
0751     /* platform data */
0752     shdev->pdata = pdata;
0753 
0754     if (pdata->chcr_offset)
0755         shdev->chcr_offset = pdata->chcr_offset;
0756     else
0757         shdev->chcr_offset = CHCR;
0758 
0759     if (pdata->chcr_ie_bit)
0760         shdev->chcr_ie_bit = pdata->chcr_ie_bit;
0761     else
0762         shdev->chcr_ie_bit = CHCR_IE;
0763 
0764     platform_set_drvdata(pdev, shdev);
0765 
0766     pm_runtime_enable(&pdev->dev);
0767     err = pm_runtime_get_sync(&pdev->dev);
0768     if (err < 0)
0769         dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err);
0770 
0771     spin_lock_irq(&sh_dmae_lock);
0772     list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
0773     spin_unlock_irq(&sh_dmae_lock);
0774 
0775     /* reset dma controller - only needed as a test */
0776     err = sh_dmae_rst(shdev);
0777     if (err)
0778         goto rst_err;
0779 
0780     if (IS_ENABLED(CONFIG_CPU_SH4) || IS_ENABLED(CONFIG_ARCH_RENESAS)) {
0781         chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
0782 
0783         if (!chanirq_res)
0784             chanirq_res = errirq_res;
0785         else
0786             irqres++;
0787 
0788         if (chanirq_res == errirq_res ||
0789             (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
0790             irqflags = IRQF_SHARED;
0791 
0792         errirq = errirq_res->start;
0793 
0794         err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err,
0795                        irqflags, "DMAC Address Error", shdev);
0796         if (err) {
0797             dev_err(&pdev->dev,
0798                 "DMA failed requesting irq #%d, error %d\n",
0799                 errirq, err);
0800             goto eirq_err;
0801         }
0802     } else {
0803         chanirq_res = errirq_res;
0804     }
0805 
0806     if (chanirq_res->start == chanirq_res->end &&
0807         !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
0808         /* Special case - all multiplexed */
0809         for (; irq_cnt < pdata->channel_num; irq_cnt++) {
0810             if (irq_cnt < SH_DMAE_MAX_CHANNELS) {
0811                 chan_irq[irq_cnt] = chanirq_res->start;
0812                 chan_flag[irq_cnt] = IRQF_SHARED;
0813             } else {
0814                 irq_cap = 1;
0815                 break;
0816             }
0817         }
0818     } else {
0819         do {
0820             for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
0821                 if (irq_cnt >= SH_DMAE_MAX_CHANNELS) {
0822                     irq_cap = 1;
0823                     break;
0824                 }
0825 
0826                 if ((errirq_res->flags & IORESOURCE_BITS) ==
0827                     IORESOURCE_IRQ_SHAREABLE)
0828                     chan_flag[irq_cnt] = IRQF_SHARED;
0829                 else
0830                     chan_flag[irq_cnt] = 0;
0831                 dev_dbg(&pdev->dev,
0832                     "Found IRQ %d for channel %d\n",
0833                     i, irq_cnt);
0834                 chan_irq[irq_cnt++] = i;
0835             }
0836 
0837             if (irq_cnt >= SH_DMAE_MAX_CHANNELS)
0838                 break;
0839 
0840             chanirq_res = platform_get_resource(pdev,
0841                         IORESOURCE_IRQ, ++irqres);
0842         } while (irq_cnt < pdata->channel_num && chanirq_res);
0843     }
0844 
0845     /* Create DMA Channel */
0846     for (i = 0; i < irq_cnt; i++) {
0847         err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
0848         if (err)
0849             goto chan_probe_err;
0850     }
0851 
0852     if (irq_cap)
0853         dev_notice(&pdev->dev, "Attempting to register %d DMA "
0854                "channels when a maximum of %d are supported.\n",
0855                pdata->channel_num, SH_DMAE_MAX_CHANNELS);
0856 
0857     pm_runtime_put(&pdev->dev);
0858 
0859     err = dma_async_device_register(&shdev->shdma_dev.dma_dev);
0860     if (err < 0)
0861         goto edmadevreg;
0862 
0863     return err;
0864 
0865 edmadevreg:
0866     pm_runtime_get(&pdev->dev);
0867 
0868 chan_probe_err:
0869     sh_dmae_chan_remove(shdev);
0870 
0871 eirq_err:
0872 rst_err:
0873     spin_lock_irq(&sh_dmae_lock);
0874     list_del_rcu(&shdev->node);
0875     spin_unlock_irq(&sh_dmae_lock);
0876 
0877     pm_runtime_put(&pdev->dev);
0878     pm_runtime_disable(&pdev->dev);
0879 
0880     shdma_cleanup(&shdev->shdma_dev);
0881 eshdma:
0882     synchronize_rcu();
0883 
0884     return err;
0885 }
0886 
0887 static int sh_dmae_remove(struct platform_device *pdev)
0888 {
0889     struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
0890     struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev;
0891 
0892     dma_async_device_unregister(dma_dev);
0893 
0894     spin_lock_irq(&sh_dmae_lock);
0895     list_del_rcu(&shdev->node);
0896     spin_unlock_irq(&sh_dmae_lock);
0897 
0898     pm_runtime_disable(&pdev->dev);
0899 
0900     sh_dmae_chan_remove(shdev);
0901     shdma_cleanup(&shdev->shdma_dev);
0902 
0903     synchronize_rcu();
0904 
0905     return 0;
0906 }
0907 
0908 static struct platform_driver sh_dmae_driver = {
0909     .driver     = {
0910         .pm = &sh_dmae_pm,
0911         .name   = SH_DMAE_DRV_NAME,
0912     },
0913     .remove     = sh_dmae_remove,
0914 };
0915 
0916 static int __init sh_dmae_init(void)
0917 {
0918     /* Wire up NMI handling */
0919     int err = register_die_notifier(&sh_dmae_nmi_notifier);
0920     if (err)
0921         return err;
0922 
0923     return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe);
0924 }
0925 module_init(sh_dmae_init);
0926 
0927 static void __exit sh_dmae_exit(void)
0928 {
0929     platform_driver_unregister(&sh_dmae_driver);
0930 
0931     unregister_die_notifier(&sh_dmae_nmi_notifier);
0932 }
0933 module_exit(sh_dmae_exit);
0934 
0935 MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>");
0936 MODULE_DESCRIPTION("Renesas SH DMA Engine driver");
0937 MODULE_LICENSE("GPL");
0938 MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME);
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