dma/sh/shdma.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Renesas SuperH DMA Engine support
0004  *
0005  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
0006  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
0007  *
0008  */
0009 #ifndef __DMA_SHDMA_H
0010 #define __DMA_SHDMA_H
0011
0012 #include <linux/sh_dma.h>
0013 #include <linux/shdma-base.h>
0014 #include <linux/dmaengine.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/list.h>
0017
0018 #define SH_DMAE_MAX_CHANNELS 20
0019 #define SH_DMAE_TCR_MAX 0x00FFFFFF  /* 16MB */
0020
0021 struct device;
0022
0023 struct sh_dmae_chan {
0024     struct shdma_chan shdma_chan;
0025     const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
0026     int xmit_shift;         /* log_2(bytes_per_xfer) */
0027     void __iomem *base;
0028     char dev_id[16];        /* unique name per DMAC of channel */
0029     int pm_error;
0030     dma_addr_t slave_addr;
0031 };
0032
0033 struct sh_dmae_device {
0034     struct shdma_dev shdma_dev;
0035     struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
0036     const struct sh_dmae_pdata *pdata;
0037     struct list_head node;
0038     void __iomem *chan_reg;
0039     void __iomem *dmars;
0040     unsigned int chcr_offset;
0041     u32 chcr_ie_bit;
0042 };
0043
0044 struct sh_dmae_regs {
0045     u32 sar; /* SAR / source address */
0046     u32 dar; /* DAR / destination address */
0047     u32 tcr; /* TCR / transfer count */
0048 };
0049
0050 struct sh_dmae_desc {
0051     struct sh_dmae_regs hw;
0052     struct shdma_desc shdma_desc;
0053 };
0054
0055 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
0056 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
0057 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
0058 #define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
0059                      struct sh_dmae_device, shdma_dev.dma_dev)
0060
0061 #endif  /* __DMA_SHDMA_H */