dma/sf-pdma/sf-pdma.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * SiFive FU540 Platform DMA driver
0004  * Copyright (C) 2019 SiFive
0005  *
0006  * Based partially on:
0007  * - drivers/dma/fsl-edma.c
0008  * - drivers/dma/dw-edma/
0009  * - drivers/dma/pxa-dma.c
0010  *
0011  * See the following sources for further documentation:
0012  * - Chapter 12 "Platform DMA Engine (PDMA)" of
0013  *   SiFive FU540-C000 v1.0
0014  *   https://static.dev.sifive.com/FU540-C000-v1.0.pdf
0015  */
0016 #include <linux/module.h>
0017 #include <linux/device.h>
0018 #include <linux/kernel.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/dma-mapping.h>
0022 #include <linux/of.h>
0023 #include <linux/slab.h>
0024
0025 #include "sf-pdma.h"
0026
0027 #ifndef readq
0028 static inline unsigned long long readq(void __iomem *addr)
0029 {
0030     return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
0031 }
0032 #endif
0033
0034 #ifndef writeq
0035 static inline void writeq(unsigned long long v, void __iomem *addr)
0036 {
0037     writel(lower_32_bits(v), addr);
0038     writel(upper_32_bits(v), addr + 4);
0039 }
0040 #endif
0041
0042 static inline struct sf_pdma_chan *to_sf_pdma_chan(struct dma_chan *dchan)
0043 {
0044     return container_of(dchan, struct sf_pdma_chan, vchan.chan);
0045 }
0046
0047 static inline struct sf_pdma_desc *to_sf_pdma_desc(struct virt_dma_desc *vd)
0048 {
0049     return container_of(vd, struct sf_pdma_desc, vdesc);
0050 }
0051
0052 static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan)
0053 {
0054     struct sf_pdma_desc *desc;
0055
0056     desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
0057     if (!desc)
0058         return NULL;
0059
0060     desc->chan = chan;
0061
0062     return desc;
0063 }
0064
0065 static void sf_pdma_fill_desc(struct sf_pdma_desc *desc,
0066                   u64 dst, u64 src, u64 size)
0067 {
0068     desc->xfer_type = PDMA_FULL_SPEED;
0069     desc->xfer_size = size;
0070     desc->dst_addr = dst;
0071     desc->src_addr = src;
0072 }
0073
0074 static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan)
0075 {
0076     struct pdma_regs *regs = &chan->regs;
0077
0078     writel(PDMA_CLEAR_CTRL, regs->ctrl);
0079 }
0080
0081 static struct dma_async_tx_descriptor *
0082 sf_pdma_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dest, dma_addr_t src,
0083             size_t len, unsigned long flags)
0084 {
0085     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0086     struct sf_pdma_desc *desc;
0087     unsigned long iflags;
0088
0089     if (chan && (!len || !dest || !src)) {
0090         dev_err(chan->pdma->dma_dev.dev,
0091             "Please check dma len, dest, src!\n");
0092         return NULL;
0093     }
0094
0095     desc = sf_pdma_alloc_desc(chan);
0096     if (!desc)
0097         return NULL;
0098
0099     desc->in_use = true;
0100     desc->dirn = DMA_MEM_TO_MEM;
0101     desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
0102
0103     spin_lock_irqsave(&chan->vchan.lock, iflags);
0104     sf_pdma_fill_desc(desc, dest, src, len);
0105     spin_unlock_irqrestore(&chan->vchan.lock, iflags);
0106
0107     return desc->async_tx;
0108 }
0109
0110 static int sf_pdma_slave_config(struct dma_chan *dchan,
0111                 struct dma_slave_config *cfg)
0112 {
0113     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0114
0115     memcpy(&chan->cfg, cfg, sizeof(*cfg));
0116
0117     return 0;
0118 }
0119
0120 static int sf_pdma_alloc_chan_resources(struct dma_chan *dchan)
0121 {
0122     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0123     struct pdma_regs *regs = &chan->regs;
0124
0125     dma_cookie_init(dchan);
0126     writel(PDMA_CLAIM_MASK, regs->ctrl);
0127
0128     return 0;
0129 }
0130
0131 static void sf_pdma_disable_request(struct sf_pdma_chan *chan)
0132 {
0133     struct pdma_regs *regs = &chan->regs;
0134
0135     writel(readl(regs->ctrl) & ~PDMA_RUN_MASK, regs->ctrl);
0136 }
0137
0138 static void sf_pdma_free_chan_resources(struct dma_chan *dchan)
0139 {
0140     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0141     unsigned long flags;
0142     LIST_HEAD(head);
0143
0144     spin_lock_irqsave(&chan->vchan.lock, flags);
0145     sf_pdma_disable_request(chan);
0146     kfree(chan->desc);
0147     chan->desc = NULL;
0148     vchan_get_all_descriptors(&chan->vchan, &head);
0149     sf_pdma_disclaim_chan(chan);
0150     spin_unlock_irqrestore(&chan->vchan.lock, flags);
0151     vchan_dma_desc_free_list(&chan->vchan, &head);
0152 }
0153
0154 static size_t sf_pdma_desc_residue(struct sf_pdma_chan *chan,
0155                    dma_cookie_t cookie)
0156 {
0157     struct virt_dma_desc *vd = NULL;
0158     struct pdma_regs *regs = &chan->regs;
0159     unsigned long flags;
0160     u64 residue = 0;
0161     struct sf_pdma_desc *desc;
0162     struct dma_async_tx_descriptor *tx = NULL;
0163
0164     spin_lock_irqsave(&chan->vchan.lock, flags);
0165
0166     list_for_each_entry(vd, &chan->vchan.desc_submitted, node)
0167         if (vd->tx.cookie == cookie)
0168             tx = &vd->tx;
0169
0170     if (!tx)
0171         goto out;
0172
0173     if (cookie == tx->chan->completed_cookie)
0174         goto out;
0175
0176     if (cookie == tx->cookie) {
0177         residue = readq(regs->residue);
0178     } else {
0179         vd = vchan_find_desc(&chan->vchan, cookie);
0180         if (!vd)
0181             goto out;
0182
0183         desc = to_sf_pdma_desc(vd);
0184         residue = desc->xfer_size;
0185     }
0186
0187 out:
0188     spin_unlock_irqrestore(&chan->vchan.lock, flags);
0189     return residue;
0190 }
0191
0192 static enum dma_status
0193 sf_pdma_tx_status(struct dma_chan *dchan,
0194           dma_cookie_t cookie,
0195           struct dma_tx_state *txstate)
0196 {
0197     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0198     enum dma_status status;
0199
0200     status = dma_cookie_status(dchan, cookie, txstate);
0201
0202     if (txstate && status != DMA_ERROR)
0203         dma_set_residue(txstate, sf_pdma_desc_residue(chan, cookie));
0204
0205     return status;
0206 }
0207
0208 static int sf_pdma_terminate_all(struct dma_chan *dchan)
0209 {
0210     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0211     unsigned long flags;
0212     LIST_HEAD(head);
0213
0214     spin_lock_irqsave(&chan->vchan.lock, flags);
0215     sf_pdma_disable_request(chan);
0216     kfree(chan->desc);
0217     chan->desc = NULL;
0218     chan->xfer_err = false;
0219     vchan_get_all_descriptors(&chan->vchan, &head);
0220     spin_unlock_irqrestore(&chan->vchan.lock, flags);
0221     vchan_dma_desc_free_list(&chan->vchan, &head);
0222
0223     return 0;
0224 }
0225
0226 static void sf_pdma_enable_request(struct sf_pdma_chan *chan)
0227 {
0228     struct pdma_regs *regs = &chan->regs;
0229     u32 v;
0230
0231     v = PDMA_CLAIM_MASK |
0232         PDMA_ENABLE_DONE_INT_MASK |
0233         PDMA_ENABLE_ERR_INT_MASK |
0234         PDMA_RUN_MASK;
0235
0236     writel(v, regs->ctrl);
0237 }
0238
0239 static struct sf_pdma_desc *sf_pdma_get_first_pending_desc(struct sf_pdma_chan *chan)
0240 {
0241     struct virt_dma_chan *vchan = &chan->vchan;
0242     struct virt_dma_desc *vdesc;
0243
0244     if (list_empty(&vchan->desc_issued))
0245         return NULL;
0246
0247     vdesc = list_first_entry(&vchan->desc_issued, struct virt_dma_desc, node);
0248
0249     return container_of(vdesc, struct sf_pdma_desc, vdesc);
0250 }
0251
0252 static void sf_pdma_xfer_desc(struct sf_pdma_chan *chan)
0253 {
0254     struct sf_pdma_desc *desc = chan->desc;
0255     struct pdma_regs *regs = &chan->regs;
0256
0257     if (!desc) {
0258         dev_err(chan->pdma->dma_dev.dev, "NULL desc.\n");
0259         return;
0260     }
0261
0262     writel(desc->xfer_type, regs->xfer_type);
0263     writeq(desc->xfer_size, regs->xfer_size);
0264     writeq(desc->dst_addr, regs->dst_addr);
0265     writeq(desc->src_addr, regs->src_addr);
0266
0267     chan->desc = desc;
0268     chan->status = DMA_IN_PROGRESS;
0269     sf_pdma_enable_request(chan);
0270 }
0271
0272 static void sf_pdma_issue_pending(struct dma_chan *dchan)
0273 {
0274     struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan);
0275     unsigned long flags;
0276
0277     spin_lock_irqsave(&chan->vchan.lock, flags);
0278
0279     if (!chan->desc && vchan_issue_pending(&chan->vchan)) {
0280         /* vchan_issue_pending has made a check that desc in not NULL */
0281         chan->desc = sf_pdma_get_first_pending_desc(chan);
0282         sf_pdma_xfer_desc(chan);
0283     }
0284
0285     spin_unlock_irqrestore(&chan->vchan.lock, flags);
0286 }
0287
0288 static void sf_pdma_free_desc(struct virt_dma_desc *vdesc)
0289 {
0290     struct sf_pdma_desc *desc;
0291
0292     desc = to_sf_pdma_desc(vdesc);
0293     desc->in_use = false;
0294 }
0295
0296 static void sf_pdma_donebh_tasklet(struct tasklet_struct *t)
0297 {
0298     struct sf_pdma_chan *chan = from_tasklet(chan, t, done_tasklet);
0299     unsigned long flags;
0300
0301     spin_lock_irqsave(&chan->lock, flags);
0302     if (chan->xfer_err) {
0303         chan->retries = MAX_RETRY;
0304         chan->status = DMA_COMPLETE;
0305         chan->xfer_err = false;
0306     }
0307     spin_unlock_irqrestore(&chan->lock, flags);
0308
0309     spin_lock_irqsave(&chan->vchan.lock, flags);
0310     list_del(&chan->desc->vdesc.node);
0311     vchan_cookie_complete(&chan->desc->vdesc);
0312
0313     chan->desc = sf_pdma_get_first_pending_desc(chan);
0314     if (chan->desc)
0315         sf_pdma_xfer_desc(chan);
0316
0317     spin_unlock_irqrestore(&chan->vchan.lock, flags);
0318 }
0319
0320 static void sf_pdma_errbh_tasklet(struct tasklet_struct *t)
0321 {
0322     struct sf_pdma_chan *chan = from_tasklet(chan, t, err_tasklet);
0323     struct sf_pdma_desc *desc = chan->desc;
0324     unsigned long flags;
0325
0326     spin_lock_irqsave(&chan->lock, flags);
0327     if (chan->retries <= 0) {
0328         /* fail to recover */
0329         spin_unlock_irqrestore(&chan->lock, flags);
0330         dmaengine_desc_get_callback_invoke(desc->async_tx, NULL);
0331     } else {
0332         /* retry */
0333         chan->retries--;
0334         chan->xfer_err = true;
0335         chan->status = DMA_ERROR;
0336
0337         sf_pdma_enable_request(chan);
0338         spin_unlock_irqrestore(&chan->lock, flags);
0339     }
0340 }
0341
0342 static irqreturn_t sf_pdma_done_isr(int irq, void *dev_id)
0343 {
0344     struct sf_pdma_chan *chan = dev_id;
0345     struct pdma_regs *regs = &chan->regs;
0346     u64 residue;
0347
0348     spin_lock(&chan->vchan.lock);
0349     writel((readl(regs->ctrl)) & ~PDMA_DONE_STATUS_MASK, regs->ctrl);
0350     residue = readq(regs->residue);
0351
0352     if (!residue) {
0353         tasklet_hi_schedule(&chan->done_tasklet);
0354     } else {
0355         /* submit next trascatioin if possible */
0356         struct sf_pdma_desc *desc = chan->desc;
0357
0358         desc->src_addr += desc->xfer_size - residue;
0359         desc->dst_addr += desc->xfer_size - residue;
0360         desc->xfer_size = residue;
0361
0362         sf_pdma_xfer_desc(chan);
0363     }
0364
0365     spin_unlock(&chan->vchan.lock);
0366
0367     return IRQ_HANDLED;
0368 }
0369
0370 static irqreturn_t sf_pdma_err_isr(int irq, void *dev_id)
0371 {
0372     struct sf_pdma_chan *chan = dev_id;
0373     struct pdma_regs *regs = &chan->regs;
0374
0375     spin_lock(&chan->lock);
0376     writel((readl(regs->ctrl)) & ~PDMA_ERR_STATUS_MASK, regs->ctrl);
0377     spin_unlock(&chan->lock);
0378
0379     tasklet_schedule(&chan->err_tasklet);
0380
0381     return IRQ_HANDLED;
0382 }
0383
0384 /**
0385  * sf_pdma_irq_init() - Init PDMA IRQ Handlers
0386  * @pdev: pointer of platform_device
0387  * @pdma: pointer of PDMA engine. Caller should check NULL
0388  *
0389  * Initialize DONE and ERROR interrupt handler for 4 channels. Caller should
0390  * make sure the pointer passed in are non-NULL. This function should be called
0391  * only one time during the device probe.
0392  *
0393  * Context: Any context.
0394  *
0395  * Return:
0396  * * 0      - OK to init all IRQ handlers
0397  * * -EINVAL    - Fail to request IRQ
0398  */
0399 static int sf_pdma_irq_init(struct platform_device *pdev, struct sf_pdma *pdma)
0400 {
0401     int irq, r, i;
0402     struct sf_pdma_chan *chan;
0403
0404     for (i = 0; i < pdma->n_chans; i++) {
0405         chan = &pdma->chans[i];
0406
0407         irq = platform_get_irq(pdev, i * 2);
0408         if (irq < 0) {
0409             dev_err(&pdev->dev, "ch(%d) Can't get done irq.\n", i);
0410             return -EINVAL;
0411         }
0412
0413         r = devm_request_irq(&pdev->dev, irq, sf_pdma_done_isr, 0,
0414                      dev_name(&pdev->dev), (void *)chan);
0415         if (r) {
0416             dev_err(&pdev->dev, "Fail to attach done ISR: %d\n", r);
0417             return -EINVAL;
0418         }
0419
0420         chan->txirq = irq;
0421
0422         irq = platform_get_irq(pdev, (i * 2) + 1);
0423         if (irq < 0) {
0424             dev_err(&pdev->dev, "ch(%d) Can't get err irq.\n", i);
0425             return -EINVAL;
0426         }
0427
0428         r = devm_request_irq(&pdev->dev, irq, sf_pdma_err_isr, 0,
0429                      dev_name(&pdev->dev), (void *)chan);
0430         if (r) {
0431             dev_err(&pdev->dev, "Fail to attach err ISR: %d\n", r);
0432             return -EINVAL;
0433         }
0434
0435         chan->errirq = irq;
0436     }
0437
0438     return 0;
0439 }
0440
0441 /**
0442  * sf_pdma_setup_chans() - Init settings of each channel
0443  * @pdma: pointer of PDMA engine. Caller should check NULL
0444  *
0445  * Initialize all data structure and register base. Caller should make sure
0446  * the pointer passed in are non-NULL. This function should be called only
0447  * one time during the device probe.
0448  *
0449  * Context: Any context.
0450  *
0451  * Return: none
0452  */
0453 static void sf_pdma_setup_chans(struct sf_pdma *pdma)
0454 {
0455     int i;
0456     struct sf_pdma_chan *chan;
0457
0458     INIT_LIST_HEAD(&pdma->dma_dev.channels);
0459
0460     for (i = 0; i < pdma->n_chans; i++) {
0461         chan = &pdma->chans[i];
0462
0463         chan->regs.ctrl =
0464             SF_PDMA_REG_BASE(i) + PDMA_CTRL;
0465         chan->regs.xfer_type =
0466             SF_PDMA_REG_BASE(i) + PDMA_XFER_TYPE;
0467         chan->regs.xfer_size =
0468             SF_PDMA_REG_BASE(i) + PDMA_XFER_SIZE;
0469         chan->regs.dst_addr =
0470             SF_PDMA_REG_BASE(i) + PDMA_DST_ADDR;
0471         chan->regs.src_addr =
0472             SF_PDMA_REG_BASE(i) + PDMA_SRC_ADDR;
0473         chan->regs.act_type =
0474             SF_PDMA_REG_BASE(i) + PDMA_ACT_TYPE;
0475         chan->regs.residue =
0476             SF_PDMA_REG_BASE(i) + PDMA_REMAINING_BYTE;
0477         chan->regs.cur_dst_addr =
0478             SF_PDMA_REG_BASE(i) + PDMA_CUR_DST_ADDR;
0479         chan->regs.cur_src_addr =
0480             SF_PDMA_REG_BASE(i) + PDMA_CUR_SRC_ADDR;
0481
0482         chan->pdma = pdma;
0483         chan->pm_state = RUNNING;
0484         chan->slave_id = i;
0485         chan->xfer_err = false;
0486         spin_lock_init(&chan->lock);
0487
0488         chan->vchan.desc_free = sf_pdma_free_desc;
0489         vchan_init(&chan->vchan, &pdma->dma_dev);
0490
0491         writel(PDMA_CLEAR_CTRL, chan->regs.ctrl);
0492
0493         tasklet_setup(&chan->done_tasklet, sf_pdma_donebh_tasklet);
0494         tasklet_setup(&chan->err_tasklet, sf_pdma_errbh_tasklet);
0495     }
0496 }
0497
0498 static int sf_pdma_probe(struct platform_device *pdev)
0499 {
0500     struct sf_pdma *pdma;
0501     struct resource *res;
0502     int ret, n_chans;
0503     const enum dma_slave_buswidth widths =
0504         DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
0505         DMA_SLAVE_BUSWIDTH_4_BYTES | DMA_SLAVE_BUSWIDTH_8_BYTES |
0506         DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES |
0507         DMA_SLAVE_BUSWIDTH_64_BYTES;
0508
0509     ret = of_property_read_u32(pdev->dev.of_node, "dma-channels", &n_chans);
0510     if (ret) {
0511         /* backwards-compatibility for no dma-channels property */
0512         dev_dbg(&pdev->dev, "set number of channels to default value: 4\n");
0513         n_chans = PDMA_MAX_NR_CH;
0514     } else if (n_chans > PDMA_MAX_NR_CH) {
0515         dev_err(&pdev->dev, "the number of channels exceeds the maximum\n");
0516         return -EINVAL;
0517     }
0518
0519     pdma = devm_kzalloc(&pdev->dev, struct_size(pdma, chans, n_chans),
0520                 GFP_KERNEL);
0521     if (!pdma)
0522         return -ENOMEM;
0523
0524     pdma->n_chans = n_chans;
0525
0526     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0527     pdma->membase = devm_ioremap_resource(&pdev->dev, res);
0528     if (IS_ERR(pdma->membase))
0529         return PTR_ERR(pdma->membase);
0530
0531     ret = sf_pdma_irq_init(pdev, pdma);
0532     if (ret)
0533         return ret;
0534
0535     sf_pdma_setup_chans(pdma);
0536
0537     pdma->dma_dev.dev = &pdev->dev;
0538
0539     /* Setup capability */
0540     dma_cap_set(DMA_MEMCPY, pdma->dma_dev.cap_mask);
0541     pdma->dma_dev.copy_align = 2;
0542     pdma->dma_dev.src_addr_widths = widths;
0543     pdma->dma_dev.dst_addr_widths = widths;
0544     pdma->dma_dev.directions = BIT(DMA_MEM_TO_MEM);
0545     pdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
0546     pdma->dma_dev.descriptor_reuse = true;
0547
0548     /* Setup DMA APIs */
0549     pdma->dma_dev.device_alloc_chan_resources =
0550         sf_pdma_alloc_chan_resources;
0551     pdma->dma_dev.device_free_chan_resources =
0552         sf_pdma_free_chan_resources;
0553     pdma->dma_dev.device_tx_status = sf_pdma_tx_status;
0554     pdma->dma_dev.device_prep_dma_memcpy = sf_pdma_prep_dma_memcpy;
0555     pdma->dma_dev.device_config = sf_pdma_slave_config;
0556     pdma->dma_dev.device_terminate_all = sf_pdma_terminate_all;
0557     pdma->dma_dev.device_issue_pending = sf_pdma_issue_pending;
0558
0559     platform_set_drvdata(pdev, pdma);
0560
0561     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0562     if (ret)
0563         dev_warn(&pdev->dev,
0564              "Failed to set DMA mask. Fall back to default.\n");
0565
0566     ret = dma_async_device_register(&pdma->dma_dev);
0567     if (ret) {
0568         dev_err(&pdev->dev,
0569             "Can't register SiFive Platform DMA. (%d)\n", ret);
0570         return ret;
0571     }
0572
0573     return 0;
0574 }
0575
0576 static int sf_pdma_remove(struct platform_device *pdev)
0577 {
0578     struct sf_pdma *pdma = platform_get_drvdata(pdev);
0579     struct sf_pdma_chan *ch;
0580     int i;
0581
0582     for (i = 0; i < pdma->n_chans; i++) {
0583         ch = &pdma->chans[i];
0584
0585         devm_free_irq(&pdev->dev, ch->txirq, ch);
0586         devm_free_irq(&pdev->dev, ch->errirq, ch);
0587         list_del(&ch->vchan.chan.device_node);
0588         tasklet_kill(&ch->vchan.task);
0589         tasklet_kill(&ch->done_tasklet);
0590         tasklet_kill(&ch->err_tasklet);
0591     }
0592
0593     dma_async_device_unregister(&pdma->dma_dev);
0594
0595     return 0;
0596 }
0597
0598 static const struct of_device_id sf_pdma_dt_ids[] = {
0599     { .compatible = "sifive,fu540-c000-pdma" },
0600     { .compatible = "sifive,pdma0" },
0601     {},
0602 };
0603 MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);
0604
0605 static struct platform_driver sf_pdma_driver = {
0606     .probe      = sf_pdma_probe,
0607     .remove     = sf_pdma_remove,
0608     .driver     = {
0609         .name   = "sf-pdma",
0610         .of_match_table = sf_pdma_dt_ids,
0611     },
0612 };
0613
0614 static int __init sf_pdma_init(void)
0615 {
0616     return platform_driver_register(&sf_pdma_driver);
0617 }
0618
0619 static void __exit sf_pdma_exit(void)
0620 {
0621     platform_driver_unregister(&sf_pdma_driver);
0622 }
0623
0624 /* do early init */
0625 subsys_initcall(sf_pdma_init);
0626 module_exit(sf_pdma_exit);
0627
0628 MODULE_LICENSE("GPL v2");
0629 MODULE_DESCRIPTION("SiFive Platform DMA driver");
0630 MODULE_AUTHOR("Green Wan <green.wan@sifive.com>");