dma/qcom/qcom_adm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/device.h>
0009 #include <linux/dmaengine.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/dma/qcom_adm.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/of_dma.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/reset.h>
0023 #include <linux/scatterlist.h>
0024 #include <linux/slab.h>
0025
0026 #include "../dmaengine.h"
0027 #include "../virt-dma.h"
0028
0029 /* ADM registers - calculated from channel number and security domain */
0030 #define ADM_CHAN_MULTI          0x4
0031 #define ADM_CI_MULTI            0x4
0032 #define ADM_CRCI_MULTI          0x4
0033 #define ADM_EE_MULTI            0x800
0034 #define ADM_CHAN_OFFS(chan)     (ADM_CHAN_MULTI * (chan))
0035 #define ADM_EE_OFFS(ee)         (ADM_EE_MULTI * (ee))
0036 #define ADM_CHAN_EE_OFFS(chan, ee)  (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
0037 #define ADM_CHAN_OFFS(chan)     (ADM_CHAN_MULTI * (chan))
0038 #define ADM_CI_OFFS(ci)         (ADM_CHAN_OFF(ci))
0039 #define ADM_CH_CMD_PTR(chan, ee)    (ADM_CHAN_EE_OFFS(chan, ee))
0040 #define ADM_CH_RSLT(chan, ee)       (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
0041 #define ADM_CH_FLUSH_STATE0(chan, ee)   (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
0042 #define ADM_CH_STATUS_SD(chan, ee)  (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
0043 #define ADM_CH_CONF(chan)       (0x240 + ADM_CHAN_OFFS(chan))
0044 #define ADM_CH_RSLT_CONF(chan, ee)  (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
0045 #define ADM_SEC_DOMAIN_IRQ_STATUS(ee)   (0x380 + ADM_EE_OFFS(ee))
0046 #define ADM_CI_CONF(ci)         (0x390 + (ci) * ADM_CI_MULTI)
0047 #define ADM_GP_CTL          0x3d8
0048 #define ADM_CRCI_CTL(crci, ee)      (0x400 + (crci) * ADM_CRCI_MULTI + \
0049                         ADM_EE_OFFS(ee))
0050
0051 /* channel status */
0052 #define ADM_CH_STATUS_VALID     BIT(1)
0053
0054 /* channel result */
0055 #define ADM_CH_RSLT_VALID       BIT(31)
0056 #define ADM_CH_RSLT_ERR         BIT(3)
0057 #define ADM_CH_RSLT_FLUSH       BIT(2)
0058 #define ADM_CH_RSLT_TPD         BIT(1)
0059
0060 /* channel conf */
0061 #define ADM_CH_CONF_SHADOW_EN       BIT(12)
0062 #define ADM_CH_CONF_MPU_DISABLE     BIT(11)
0063 #define ADM_CH_CONF_PERM_MPU_CONF   BIT(9)
0064 #define ADM_CH_CONF_FORCE_RSLT_EN   BIT(7)
0065 #define ADM_CH_CONF_SEC_DOMAIN(ee)  ((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11))
0066
0067 /* channel result conf */
0068 #define ADM_CH_RSLT_CONF_FLUSH_EN   BIT(1)
0069 #define ADM_CH_RSLT_CONF_IRQ_EN     BIT(0)
0070
0071 /* CRCI CTL */
0072 #define ADM_CRCI_CTL_MUX_SEL        BIT(18)
0073 #define ADM_CRCI_CTL_RST        BIT(17)
0074
0075 /* CI configuration */
0076 #define ADM_CI_RANGE_END(x)     ((x) << 24)
0077 #define ADM_CI_RANGE_START(x)       ((x) << 16)
0078 #define ADM_CI_BURST_4_WORDS        BIT(2)
0079 #define ADM_CI_BURST_8_WORDS        BIT(3)
0080
0081 /* GP CTL */
0082 #define ADM_GP_CTL_LP_EN        BIT(12)
0083 #define ADM_GP_CTL_LP_CNT(x)        ((x) << 8)
0084
0085 /* Command pointer list entry */
0086 #define ADM_CPLE_LP         BIT(31)
0087 #define ADM_CPLE_CMD_PTR_LIST       BIT(29)
0088
0089 /* Command list entry */
0090 #define ADM_CMD_LC          BIT(31)
0091 #define ADM_CMD_DST_CRCI(n)     (((n) & 0xf) << 7)
0092 #define ADM_CMD_SRC_CRCI(n)     (((n) & 0xf) << 3)
0093
0094 #define ADM_CMD_TYPE_SINGLE     0x0
0095 #define ADM_CMD_TYPE_BOX        0x3
0096
0097 #define ADM_CRCI_MUX_SEL        BIT(4)
0098 #define ADM_DESC_ALIGN          8
0099 #define ADM_MAX_XFER            (SZ_64K - 1)
0100 #define ADM_MAX_ROWS            (SZ_64K - 1)
0101 #define ADM_MAX_CHANNELS        16
0102
0103 struct adm_desc_hw_box {
0104     u32 cmd;
0105     u32 src_addr;
0106     u32 dst_addr;
0107     u32 row_len;
0108     u32 num_rows;
0109     u32 row_offset;
0110 };
0111
0112 struct adm_desc_hw_single {
0113     u32 cmd;
0114     u32 src_addr;
0115     u32 dst_addr;
0116     u32 len;
0117 };
0118
0119 struct adm_async_desc {
0120     struct virt_dma_desc vd;
0121     struct adm_device *adev;
0122
0123     size_t length;
0124     enum dma_transfer_direction dir;
0125     dma_addr_t dma_addr;
0126     size_t dma_len;
0127
0128     void *cpl;
0129     dma_addr_t cp_addr;
0130     u32 crci;
0131     u32 mux;
0132     u32 blk_size;
0133 };
0134
0135 struct adm_chan {
0136     struct virt_dma_chan vc;
0137     struct adm_device *adev;
0138
0139     /* parsed from DT */
0140     u32 id;         /* channel id */
0141
0142     struct adm_async_desc *curr_txd;
0143     struct dma_slave_config slave;
0144     u32 crci;
0145     u32 mux;
0146     struct list_head node;
0147
0148     int error;
0149     int initialized;
0150 };
0151
0152 static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
0153 {
0154     return container_of(common, struct adm_chan, vc.chan);
0155 }
0156
0157 struct adm_device {
0158     void __iomem *regs;
0159     struct device *dev;
0160     struct dma_device common;
0161     struct device_dma_parameters dma_parms;
0162     struct adm_chan *channels;
0163
0164     u32 ee;
0165
0166     struct clk *core_clk;
0167     struct clk *iface_clk;
0168
0169     struct reset_control *clk_reset;
0170     struct reset_control *c0_reset;
0171     struct reset_control *c1_reset;
0172     struct reset_control *c2_reset;
0173     int irq;
0174 };
0175
0176 /**
0177  * adm_free_chan - Frees dma resources associated with the specific channel
0178  *
0179  * @chan: dma channel
0180  *
0181  * Free all allocated descriptors associated with this channel
0182  */
0183 static void adm_free_chan(struct dma_chan *chan)
0184 {
0185     /* free all queued descriptors */
0186     vchan_free_chan_resources(to_virt_chan(chan));
0187 }
0188
0189 /**
0190  * adm_get_blksize - Get block size from burst value
0191  *
0192  * @burst: Burst size of transaction
0193  */
0194 static int adm_get_blksize(unsigned int burst)
0195 {
0196     int ret;
0197
0198     switch (burst) {
0199     case 16:
0200     case 32:
0201     case 64:
0202     case 128:
0203         ret = ffs(burst >> 4) - 1;
0204         break;
0205     case 192:
0206         ret = 4;
0207         break;
0208     case 256:
0209         ret = 5;
0210         break;
0211     default:
0212         ret = -EINVAL;
0213         break;
0214     }
0215
0216     return ret;
0217 }
0218
0219 /**
0220  * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
0221  *
0222  * @achan: ADM channel
0223  * @desc: Descriptor memory pointer
0224  * @sg: Scatterlist entry
0225  * @crci: CRCI value
0226  * @burst: Burst size of transaction
0227  * @direction: DMA transfer direction
0228  */
0229 static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc,
0230                     struct scatterlist *sg, u32 crci,
0231                     u32 burst,
0232                     enum dma_transfer_direction direction)
0233 {
0234     struct adm_desc_hw_box *box_desc = NULL;
0235     struct adm_desc_hw_single *single_desc;
0236     u32 remainder = sg_dma_len(sg);
0237     u32 rows, row_offset, crci_cmd;
0238     u32 mem_addr = sg_dma_address(sg);
0239     u32 *incr_addr = &mem_addr;
0240     u32 *src, *dst;
0241
0242     if (direction == DMA_DEV_TO_MEM) {
0243         crci_cmd = ADM_CMD_SRC_CRCI(crci);
0244         row_offset = burst;
0245         src = &achan->slave.src_addr;
0246         dst = &mem_addr;
0247     } else {
0248         crci_cmd = ADM_CMD_DST_CRCI(crci);
0249         row_offset = burst << 16;
0250         src = &mem_addr;
0251         dst = &achan->slave.dst_addr;
0252     }
0253
0254     while (remainder >= burst) {
0255         box_desc = desc;
0256         box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
0257         box_desc->row_offset = row_offset;
0258         box_desc->src_addr = *src;
0259         box_desc->dst_addr = *dst;
0260
0261         rows = remainder / burst;
0262         rows = min_t(u32, rows, ADM_MAX_ROWS);
0263         box_desc->num_rows = rows << 16 | rows;
0264         box_desc->row_len = burst << 16 | burst;
0265
0266         *incr_addr += burst * rows;
0267         remainder -= burst * rows;
0268         desc += sizeof(*box_desc);
0269     }
0270
0271     /* if leftover bytes, do one single descriptor */
0272     if (remainder) {
0273         single_desc = desc;
0274         single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
0275         single_desc->len = remainder;
0276         single_desc->src_addr = *src;
0277         single_desc->dst_addr = *dst;
0278         desc += sizeof(*single_desc);
0279
0280         if (sg_is_last(sg))
0281             single_desc->cmd |= ADM_CMD_LC;
0282     } else {
0283         if (box_desc && sg_is_last(sg))
0284             box_desc->cmd |= ADM_CMD_LC;
0285     }
0286
0287     return desc;
0288 }
0289
0290 /**
0291  * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
0292  *
0293  * @achan: ADM channel
0294  * @desc: Descriptor memory pointer
0295  * @sg: Scatterlist entry
0296  * @direction: DMA transfer direction
0297  */
0298 static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc,
0299                         struct scatterlist *sg,
0300                         enum dma_transfer_direction direction)
0301 {
0302     struct adm_desc_hw_single *single_desc;
0303     u32 remainder = sg_dma_len(sg);
0304     u32 mem_addr = sg_dma_address(sg);
0305     u32 *incr_addr = &mem_addr;
0306     u32 *src, *dst;
0307
0308     if (direction == DMA_DEV_TO_MEM) {
0309         src = &achan->slave.src_addr;
0310         dst = &mem_addr;
0311     } else {
0312         src = &mem_addr;
0313         dst = &achan->slave.dst_addr;
0314     }
0315
0316     do {
0317         single_desc = desc;
0318         single_desc->cmd = ADM_CMD_TYPE_SINGLE;
0319         single_desc->src_addr = *src;
0320         single_desc->dst_addr = *dst;
0321         single_desc->len = (remainder > ADM_MAX_XFER) ?
0322                 ADM_MAX_XFER : remainder;
0323
0324         remainder -= single_desc->len;
0325         *incr_addr += single_desc->len;
0326         desc += sizeof(*single_desc);
0327     } while (remainder);
0328
0329     /* set last command if this is the end of the whole transaction */
0330     if (sg_is_last(sg))
0331         single_desc->cmd |= ADM_CMD_LC;
0332
0333     return desc;
0334 }
0335
0336 /**
0337  * adm_prep_slave_sg - Prep slave sg transaction
0338  *
0339  * @chan: dma channel
0340  * @sgl: scatter gather list
0341  * @sg_len: length of sg
0342  * @direction: DMA transfer direction
0343  * @flags: DMA flags
0344  * @context: transfer context (unused)
0345  */
0346 static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
0347                              struct scatterlist *sgl,
0348                              unsigned int sg_len,
0349                              enum dma_transfer_direction direction,
0350                              unsigned long flags,
0351                              void *context)
0352 {
0353     struct adm_chan *achan = to_adm_chan(chan);
0354     struct adm_device *adev = achan->adev;
0355     struct adm_async_desc *async_desc;
0356     struct scatterlist *sg;
0357     dma_addr_t cple_addr;
0358     u32 i, burst;
0359     u32 single_count = 0, box_count = 0, crci = 0;
0360     void *desc;
0361     u32 *cple;
0362     int blk_size = 0;
0363
0364     if (!is_slave_direction(direction)) {
0365         dev_err(adev->dev, "invalid dma direction\n");
0366         return NULL;
0367     }
0368
0369     /*
0370      * get burst value from slave configuration
0371      */
0372     burst = (direction == DMA_MEM_TO_DEV) ?
0373         achan->slave.dst_maxburst :
0374         achan->slave.src_maxburst;
0375
0376     /* if using flow control, validate burst and crci values */
0377     if (achan->slave.device_fc) {
0378         blk_size = adm_get_blksize(burst);
0379         if (blk_size < 0) {
0380             dev_err(adev->dev, "invalid burst value: %d\n",
0381                 burst);
0382             return ERR_PTR(-EINVAL);
0383         }
0384
0385         crci = achan->crci & 0xf;
0386         if (!crci || achan->crci > 0x1f) {
0387             dev_err(adev->dev, "invalid crci value\n");
0388             return ERR_PTR(-EINVAL);
0389         }
0390     }
0391
0392     /* iterate through sgs and compute allocation size of structures */
0393     for_each_sg(sgl, sg, sg_len, i) {
0394         if (achan->slave.device_fc) {
0395             box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
0396                           ADM_MAX_ROWS);
0397             if (sg_dma_len(sg) % burst)
0398                 single_count++;
0399         } else {
0400             single_count += DIV_ROUND_UP(sg_dma_len(sg),
0401                              ADM_MAX_XFER);
0402         }
0403     }
0404
0405     async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);
0406     if (!async_desc)
0407         return ERR_PTR(-ENOMEM);
0408
0409     async_desc->mux = achan->mux ? ADM_CRCI_CTL_MUX_SEL : 0;
0410     async_desc->crci = crci;
0411     async_desc->blk_size = blk_size;
0412     async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
0413                 box_count * sizeof(struct adm_desc_hw_box) +
0414                 sizeof(*cple) + 2 * ADM_DESC_ALIGN;
0415
0416     async_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT);
0417     if (!async_desc->cpl)
0418         goto free;
0419
0420     async_desc->adev = adev;
0421
0422     /* both command list entry and descriptors must be 8 byte aligned */
0423     cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
0424     desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
0425
0426     for_each_sg(sgl, sg, sg_len, i) {
0427         async_desc->length += sg_dma_len(sg);
0428
0429         if (achan->slave.device_fc)
0430             desc = adm_process_fc_descriptors(achan, desc, sg, crci,
0431                               burst, direction);
0432         else
0433             desc = adm_process_non_fc_descriptors(achan, desc, sg,
0434                                   direction);
0435     }
0436
0437     async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl,
0438                           async_desc->dma_len,
0439                           DMA_TO_DEVICE);
0440     if (dma_mapping_error(adev->dev, async_desc->dma_addr))
0441         goto free;
0442
0443     cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl);
0444
0445     /* init cmd list */
0446     dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple),
0447                 DMA_TO_DEVICE);
0448     *cple = ADM_CPLE_LP;
0449     *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3;
0450     dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple),
0451                    DMA_TO_DEVICE);
0452
0453     return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
0454
0455 free:
0456     kfree(async_desc);
0457     return ERR_PTR(-ENOMEM);
0458 }
0459
0460 /**
0461  * adm_terminate_all - terminate all transactions on a channel
0462  * @chan: dma channel
0463  *
0464  * Dequeues and frees all transactions, aborts current transaction
0465  * No callbacks are done
0466  *
0467  */
0468 static int adm_terminate_all(struct dma_chan *chan)
0469 {
0470     struct adm_chan *achan = to_adm_chan(chan);
0471     struct adm_device *adev = achan->adev;
0472     unsigned long flags;
0473     LIST_HEAD(head);
0474
0475     spin_lock_irqsave(&achan->vc.lock, flags);
0476     vchan_get_all_descriptors(&achan->vc, &head);
0477
0478     /* send flush command to terminate current transaction */
0479     writel_relaxed(0x0,
0480                adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
0481
0482     spin_unlock_irqrestore(&achan->vc.lock, flags);
0483
0484     vchan_dma_desc_free_list(&achan->vc, &head);
0485
0486     return 0;
0487 }
0488
0489 static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
0490 {
0491     struct adm_chan *achan = to_adm_chan(chan);
0492     struct qcom_adm_peripheral_config *config = cfg->peripheral_config;
0493     unsigned long flag;
0494
0495     spin_lock_irqsave(&achan->vc.lock, flag);
0496     memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
0497     if (cfg->peripheral_size == sizeof(config))
0498         achan->crci = config->crci;
0499     spin_unlock_irqrestore(&achan->vc.lock, flag);
0500
0501     return 0;
0502 }
0503
0504 /**
0505  * adm_start_dma - start next transaction
0506  * @achan: ADM dma channel
0507  */
0508 static void adm_start_dma(struct adm_chan *achan)
0509 {
0510     struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
0511     struct adm_device *adev = achan->adev;
0512     struct adm_async_desc *async_desc;
0513
0514     lockdep_assert_held(&achan->vc.lock);
0515
0516     if (!vd)
0517         return;
0518
0519     list_del(&vd->node);
0520
0521     /* write next command list out to the CMD FIFO */
0522     async_desc = container_of(vd, struct adm_async_desc, vd);
0523     achan->curr_txd = async_desc;
0524
0525     /* reset channel error */
0526     achan->error = 0;
0527
0528     if (!achan->initialized) {
0529         /* enable interrupts */
0530         writel(ADM_CH_CONF_SHADOW_EN |
0531                ADM_CH_CONF_PERM_MPU_CONF |
0532                ADM_CH_CONF_MPU_DISABLE |
0533                ADM_CH_CONF_SEC_DOMAIN(adev->ee),
0534                adev->regs + ADM_CH_CONF(achan->id));
0535
0536         writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
0537                adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
0538
0539         achan->initialized = 1;
0540     }
0541
0542     /* set the crci block size if this transaction requires CRCI */
0543     if (async_desc->crci) {
0544         writel(async_desc->mux | async_desc->blk_size,
0545                adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
0546     }
0547
0548     /* make sure IRQ enable doesn't get reordered */
0549     wmb();
0550
0551     /* write next command list out to the CMD FIFO */
0552     writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
0553            adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
0554 }
0555
0556 /**
0557  * adm_dma_irq - irq handler for ADM controller
0558  * @irq: IRQ of interrupt
0559  * @data: callback data
0560  *
0561  * IRQ handler for the bam controller
0562  */
0563 static irqreturn_t adm_dma_irq(int irq, void *data)
0564 {
0565     struct adm_device *adev = data;
0566     u32 srcs, i;
0567     struct adm_async_desc *async_desc;
0568     unsigned long flags;
0569
0570     srcs = readl_relaxed(adev->regs +
0571             ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
0572
0573     for (i = 0; i < ADM_MAX_CHANNELS; i++) {
0574         struct adm_chan *achan = &adev->channels[i];
0575         u32 status, result;
0576
0577         if (srcs & BIT(i)) {
0578             status = readl_relaxed(adev->regs +
0579                            ADM_CH_STATUS_SD(i, adev->ee));
0580
0581             /* if no result present, skip */
0582             if (!(status & ADM_CH_STATUS_VALID))
0583                 continue;
0584
0585             result = readl_relaxed(adev->regs +
0586                 ADM_CH_RSLT(i, adev->ee));
0587
0588             /* no valid results, skip */
0589             if (!(result & ADM_CH_RSLT_VALID))
0590                 continue;
0591
0592             /* flag error if transaction was flushed or failed */
0593             if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
0594                 achan->error = 1;
0595
0596             spin_lock_irqsave(&achan->vc.lock, flags);
0597             async_desc = achan->curr_txd;
0598
0599             achan->curr_txd = NULL;
0600
0601             if (async_desc) {
0602                 vchan_cookie_complete(&async_desc->vd);
0603
0604                 /* kick off next DMA */
0605                 adm_start_dma(achan);
0606             }
0607
0608             spin_unlock_irqrestore(&achan->vc.lock, flags);
0609         }
0610     }
0611
0612     return IRQ_HANDLED;
0613 }
0614
0615 /**
0616  * adm_tx_status - returns status of transaction
0617  * @chan: dma channel
0618  * @cookie: transaction cookie
0619  * @txstate: DMA transaction state
0620  *
0621  * Return status of dma transaction
0622  */
0623 static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
0624                      struct dma_tx_state *txstate)
0625 {
0626     struct adm_chan *achan = to_adm_chan(chan);
0627     struct virt_dma_desc *vd;
0628     enum dma_status ret;
0629     unsigned long flags;
0630     size_t residue = 0;
0631
0632     ret = dma_cookie_status(chan, cookie, txstate);
0633     if (ret == DMA_COMPLETE || !txstate)
0634         return ret;
0635
0636     spin_lock_irqsave(&achan->vc.lock, flags);
0637
0638     vd = vchan_find_desc(&achan->vc, cookie);
0639     if (vd)
0640         residue = container_of(vd, struct adm_async_desc, vd)->length;
0641
0642     spin_unlock_irqrestore(&achan->vc.lock, flags);
0643
0644     /*
0645      * residue is either the full length if it is in the issued list, or 0
0646      * if it is in progress.  We have no reliable way of determining
0647      * anything inbetween
0648      */
0649     dma_set_residue(txstate, residue);
0650
0651     if (achan->error)
0652         return DMA_ERROR;
0653
0654     return ret;
0655 }
0656
0657 /**
0658  * adm_issue_pending - starts pending transactions
0659  * @chan: dma channel
0660  *
0661  * Issues all pending transactions and starts DMA
0662  */
0663 static void adm_issue_pending(struct dma_chan *chan)
0664 {
0665     struct adm_chan *achan = to_adm_chan(chan);
0666     unsigned long flags;
0667
0668     spin_lock_irqsave(&achan->vc.lock, flags);
0669
0670     if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
0671         adm_start_dma(achan);
0672     spin_unlock_irqrestore(&achan->vc.lock, flags);
0673 }
0674
0675 /**
0676  * adm_dma_free_desc - free descriptor memory
0677  * @vd: virtual descriptor
0678  *
0679  */
0680 static void adm_dma_free_desc(struct virt_dma_desc *vd)
0681 {
0682     struct adm_async_desc *async_desc = container_of(vd,
0683             struct adm_async_desc, vd);
0684
0685     dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr,
0686              async_desc->dma_len, DMA_TO_DEVICE);
0687     kfree(async_desc->cpl);
0688     kfree(async_desc);
0689 }
0690
0691 static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
0692                  u32 index)
0693 {
0694     achan->id = index;
0695     achan->adev = adev;
0696
0697     vchan_init(&achan->vc, &adev->common);
0698     achan->vc.desc_free = adm_dma_free_desc;
0699 }
0700
0701 /**
0702  * adm_dma_xlate
0703  * @dma_spec:   pointer to DMA specifier as found in the device tree
0704  * @ofdma:  pointer to DMA controller data
0705  *
0706  * This can use either 1-cell or 2-cell formats, the first cell
0707  * identifies the slave device, while the optional second cell
0708  * contains the crci value.
0709  *
0710  * Returns pointer to appropriate dma channel on success or NULL on error.
0711  */
0712 static struct dma_chan *adm_dma_xlate(struct of_phandle_args *dma_spec,
0713                    struct of_dma *ofdma)
0714 {
0715     struct dma_device *dev = ofdma->of_dma_data;
0716     struct dma_chan *chan, *candidate = NULL;
0717     struct adm_chan *achan;
0718
0719     if (!dev || dma_spec->args_count > 2)
0720         return NULL;
0721
0722     list_for_each_entry(chan, &dev->channels, device_node)
0723         if (chan->chan_id == dma_spec->args[0]) {
0724             candidate = chan;
0725             break;
0726         }
0727
0728     if (!candidate)
0729         return NULL;
0730
0731     achan = to_adm_chan(candidate);
0732     if (dma_spec->args_count == 2)
0733         achan->crci = dma_spec->args[1];
0734     else
0735         achan->crci = 0;
0736
0737     return dma_get_slave_channel(candidate);
0738 }
0739
0740 static int adm_dma_probe(struct platform_device *pdev)
0741 {
0742     struct adm_device *adev;
0743     int ret;
0744     u32 i;
0745
0746     adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
0747     if (!adev)
0748         return -ENOMEM;
0749
0750     adev->dev = &pdev->dev;
0751
0752     adev->regs = devm_platform_ioremap_resource(pdev, 0);
0753     if (IS_ERR(adev->regs))
0754         return PTR_ERR(adev->regs);
0755
0756     adev->irq = platform_get_irq(pdev, 0);
0757     if (adev->irq < 0)
0758         return adev->irq;
0759
0760     ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
0761     if (ret) {
0762         dev_err(adev->dev, "Execution environment unspecified\n");
0763         return ret;
0764     }
0765
0766     adev->core_clk = devm_clk_get(adev->dev, "core");
0767     if (IS_ERR(adev->core_clk))
0768         return PTR_ERR(adev->core_clk);
0769
0770     adev->iface_clk = devm_clk_get(adev->dev, "iface");
0771     if (IS_ERR(adev->iface_clk))
0772         return PTR_ERR(adev->iface_clk);
0773
0774     adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk");
0775     if (IS_ERR(adev->clk_reset)) {
0776         dev_err(adev->dev, "failed to get ADM0 reset\n");
0777         return PTR_ERR(adev->clk_reset);
0778     }
0779
0780     adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0");
0781     if (IS_ERR(adev->c0_reset)) {
0782         dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
0783         return PTR_ERR(adev->c0_reset);
0784     }
0785
0786     adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1");
0787     if (IS_ERR(adev->c1_reset)) {
0788         dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
0789         return PTR_ERR(adev->c1_reset);
0790     }
0791
0792     adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2");
0793     if (IS_ERR(adev->c2_reset)) {
0794         dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
0795         return PTR_ERR(adev->c2_reset);
0796     }
0797
0798     ret = clk_prepare_enable(adev->core_clk);
0799     if (ret) {
0800         dev_err(adev->dev, "failed to prepare/enable core clock\n");
0801         return ret;
0802     }
0803
0804     ret = clk_prepare_enable(adev->iface_clk);
0805     if (ret) {
0806         dev_err(adev->dev, "failed to prepare/enable iface clock\n");
0807         goto err_disable_core_clk;
0808     }
0809
0810     reset_control_assert(adev->clk_reset);
0811     reset_control_assert(adev->c0_reset);
0812     reset_control_assert(adev->c1_reset);
0813     reset_control_assert(adev->c2_reset);
0814
0815     udelay(2);
0816
0817     reset_control_deassert(adev->clk_reset);
0818     reset_control_deassert(adev->c0_reset);
0819     reset_control_deassert(adev->c1_reset);
0820     reset_control_deassert(adev->c2_reset);
0821
0822     adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
0823                       sizeof(*adev->channels), GFP_KERNEL);
0824
0825     if (!adev->channels) {
0826         ret = -ENOMEM;
0827         goto err_disable_clks;
0828     }
0829
0830     /* allocate and initialize channels */
0831     INIT_LIST_HEAD(&adev->common.channels);
0832
0833     for (i = 0; i < ADM_MAX_CHANNELS; i++)
0834         adm_channel_init(adev, &adev->channels[i], i);
0835
0836     /* reset CRCIs */
0837     for (i = 0; i < 16; i++)
0838         writel(ADM_CRCI_CTL_RST, adev->regs +
0839             ADM_CRCI_CTL(i, adev->ee));
0840
0841     /* configure client interfaces */
0842     writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
0843            ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
0844     writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
0845            ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
0846     writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
0847            ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
0848     writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
0849            adev->regs + ADM_GP_CTL);
0850
0851     ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
0852                    0, "adm_dma", adev);
0853     if (ret)
0854         goto err_disable_clks;
0855
0856     platform_set_drvdata(pdev, adev);
0857
0858     adev->common.dev = adev->dev;
0859     adev->common.dev->dma_parms = &adev->dma_parms;
0860
0861     /* set capabilities */
0862     dma_cap_zero(adev->common.cap_mask);
0863     dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
0864     dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
0865
0866     /* initialize dmaengine apis */
0867     adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
0868     adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
0869     adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
0870     adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
0871     adev->common.device_free_chan_resources = adm_free_chan;
0872     adev->common.device_prep_slave_sg = adm_prep_slave_sg;
0873     adev->common.device_issue_pending = adm_issue_pending;
0874     adev->common.device_tx_status = adm_tx_status;
0875     adev->common.device_terminate_all = adm_terminate_all;
0876     adev->common.device_config = adm_slave_config;
0877
0878     ret = dma_async_device_register(&adev->common);
0879     if (ret) {
0880         dev_err(adev->dev, "failed to register dma async device\n");
0881         goto err_disable_clks;
0882     }
0883
0884     ret = of_dma_controller_register(pdev->dev.of_node, adm_dma_xlate,
0885                      &adev->common);
0886     if (ret)
0887         goto err_unregister_dma;
0888
0889     return 0;
0890
0891 err_unregister_dma:
0892     dma_async_device_unregister(&adev->common);
0893 err_disable_clks:
0894     clk_disable_unprepare(adev->iface_clk);
0895 err_disable_core_clk:
0896     clk_disable_unprepare(adev->core_clk);
0897
0898     return ret;
0899 }
0900
0901 static int adm_dma_remove(struct platform_device *pdev)
0902 {
0903     struct adm_device *adev = platform_get_drvdata(pdev);
0904     struct adm_chan *achan;
0905     u32 i;
0906
0907     of_dma_controller_free(pdev->dev.of_node);
0908     dma_async_device_unregister(&adev->common);
0909
0910     for (i = 0; i < ADM_MAX_CHANNELS; i++) {
0911         achan = &adev->channels[i];
0912
0913         /* mask IRQs for this channel/EE pair */
0914         writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
0915
0916         tasklet_kill(&adev->channels[i].vc.task);
0917         adm_terminate_all(&adev->channels[i].vc.chan);
0918     }
0919
0920     devm_free_irq(adev->dev, adev->irq, adev);
0921
0922     clk_disable_unprepare(adev->core_clk);
0923     clk_disable_unprepare(adev->iface_clk);
0924
0925     return 0;
0926 }
0927
0928 static const struct of_device_id adm_of_match[] = {
0929     { .compatible = "qcom,adm", },
0930     {}
0931 };
0932 MODULE_DEVICE_TABLE(of, adm_of_match);
0933
0934 static struct platform_driver adm_dma_driver = {
0935     .probe = adm_dma_probe,
0936     .remove = adm_dma_remove,
0937     .driver = {
0938         .name = "adm-dma-engine",
0939         .of_match_table = adm_of_match,
0940     },
0941 };
0942
0943 module_platform_driver(adm_dma_driver);
0944
0945 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
0946 MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
0947 MODULE_LICENSE("GPL v2");