dma/qcom/hidma_mgmt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Qualcomm Technologies HIDMA DMA engine Management interface
0004  *
0005  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
0006  */
0007
0008 #include <linux/dmaengine.h>
0009 #include <linux/acpi.h>
0010 #include <linux/of.h>
0011 #include <linux/property.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/module.h>
0016 #include <linux/uaccess.h>
0017 #include <linux/slab.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/bitops.h>
0020 #include <linux/dma-mapping.h>
0021
0022 #include "hidma_mgmt.h"
0023
0024 #define HIDMA_QOS_N_OFFSET      0x700
0025 #define HIDMA_CFG_OFFSET        0x400
0026 #define HIDMA_MAX_BUS_REQ_LEN_OFFSET    0x41C
0027 #define HIDMA_MAX_XACTIONS_OFFSET   0x420
0028 #define HIDMA_HW_VERSION_OFFSET 0x424
0029 #define HIDMA_CHRESET_TIMEOUT_OFFSET    0x418
0030
0031 #define HIDMA_MAX_WR_XACTIONS_MASK  GENMASK(4, 0)
0032 #define HIDMA_MAX_RD_XACTIONS_MASK  GENMASK(4, 0)
0033 #define HIDMA_WEIGHT_MASK       GENMASK(6, 0)
0034 #define HIDMA_MAX_BUS_REQ_LEN_MASK  GENMASK(15, 0)
0035 #define HIDMA_CHRESET_TIMEOUT_MASK  GENMASK(19, 0)
0036
0037 #define HIDMA_MAX_WR_XACTIONS_BIT_POS   16
0038 #define HIDMA_MAX_BUS_WR_REQ_BIT_POS    16
0039 #define HIDMA_WRR_BIT_POS       8
0040 #define HIDMA_PRIORITY_BIT_POS      15
0041
0042 #define HIDMA_AUTOSUSPEND_TIMEOUT   2000
0043 #define HIDMA_MAX_CHANNEL_WEIGHT    15
0044
0045 static unsigned int max_write_request;
0046 module_param(max_write_request, uint, 0644);
0047 MODULE_PARM_DESC(max_write_request,
0048         "maximum write burst (default: ACPI/DT value)");
0049
0050 static unsigned int max_read_request;
0051 module_param(max_read_request, uint, 0644);
0052 MODULE_PARM_DESC(max_read_request,
0053         "maximum read burst (default: ACPI/DT value)");
0054
0055 static unsigned int max_wr_xactions;
0056 module_param(max_wr_xactions, uint, 0644);
0057 MODULE_PARM_DESC(max_wr_xactions,
0058     "maximum number of write transactions (default: ACPI/DT value)");
0059
0060 static unsigned int max_rd_xactions;
0061 module_param(max_rd_xactions, uint, 0644);
0062 MODULE_PARM_DESC(max_rd_xactions,
0063     "maximum number of read transactions (default: ACPI/DT value)");
0064
0065 int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
0066 {
0067     unsigned int i;
0068     u32 val;
0069
0070     if (!is_power_of_2(mgmtdev->max_write_request) ||
0071         (mgmtdev->max_write_request < 128) ||
0072         (mgmtdev->max_write_request > 1024)) {
0073         dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
0074             mgmtdev->max_write_request);
0075         return -EINVAL;
0076     }
0077
0078     if (!is_power_of_2(mgmtdev->max_read_request) ||
0079         (mgmtdev->max_read_request < 128) ||
0080         (mgmtdev->max_read_request > 1024)) {
0081         dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
0082             mgmtdev->max_read_request);
0083         return -EINVAL;
0084     }
0085
0086     if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
0087         dev_err(&mgmtdev->pdev->dev,
0088             "max_wr_xactions cannot be bigger than %ld\n",
0089             HIDMA_MAX_WR_XACTIONS_MASK);
0090         return -EINVAL;
0091     }
0092
0093     if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
0094         dev_err(&mgmtdev->pdev->dev,
0095             "max_rd_xactions cannot be bigger than %ld\n",
0096             HIDMA_MAX_RD_XACTIONS_MASK);
0097         return -EINVAL;
0098     }
0099
0100     for (i = 0; i < mgmtdev->dma_channels; i++) {
0101         if (mgmtdev->priority[i] > 1) {
0102             dev_err(&mgmtdev->pdev->dev,
0103                 "priority can be 0 or 1\n");
0104             return -EINVAL;
0105         }
0106
0107         if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
0108             dev_err(&mgmtdev->pdev->dev,
0109                 "max value of weight can be %d.\n",
0110                 HIDMA_MAX_CHANNEL_WEIGHT);
0111             return -EINVAL;
0112         }
0113
0114         /* weight needs to be at least one */
0115         if (mgmtdev->weight[i] == 0)
0116             mgmtdev->weight[i] = 1;
0117     }
0118
0119     pm_runtime_get_sync(&mgmtdev->pdev->dev);
0120     val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
0121     val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
0122     val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
0123     val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
0124     val |= mgmtdev->max_read_request;
0125     writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
0126
0127     val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
0128     val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
0129     val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
0130     val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
0131     val |= mgmtdev->max_rd_xactions;
0132     writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
0133
0134     mgmtdev->hw_version =
0135         readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
0136     mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
0137     mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
0138
0139     for (i = 0; i < mgmtdev->dma_channels; i++) {
0140         u32 weight = mgmtdev->weight[i];
0141         u32 priority = mgmtdev->priority[i];
0142
0143         val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
0144         val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
0145         val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
0146         val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
0147         val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
0148         writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
0149     }
0150
0151     val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
0152     val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
0153     val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
0154     writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
0155
0156     pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
0157     pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
0158     return 0;
0159 }
0160 EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
0161
0162 static int hidma_mgmt_probe(struct platform_device *pdev)
0163 {
0164     struct hidma_mgmt_dev *mgmtdev;
0165     struct resource *res;
0166     void __iomem *virtaddr;
0167     int irq;
0168     int rc;
0169     u32 val;
0170
0171     pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
0172     pm_runtime_use_autosuspend(&pdev->dev);
0173     pm_runtime_set_active(&pdev->dev);
0174     pm_runtime_enable(&pdev->dev);
0175     pm_runtime_get_sync(&pdev->dev);
0176
0177     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0178     virtaddr = devm_ioremap_resource(&pdev->dev, res);
0179     if (IS_ERR(virtaddr)) {
0180         rc = -ENOMEM;
0181         goto out;
0182     }
0183
0184     irq = platform_get_irq(pdev, 0);
0185     if (irq < 0) {
0186         rc = irq;
0187         goto out;
0188     }
0189
0190     mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
0191     if (!mgmtdev) {
0192         rc = -ENOMEM;
0193         goto out;
0194     }
0195
0196     mgmtdev->pdev = pdev;
0197     mgmtdev->addrsize = resource_size(res);
0198     mgmtdev->virtaddr = virtaddr;
0199
0200     rc = device_property_read_u32(&pdev->dev, "dma-channels",
0201                       &mgmtdev->dma_channels);
0202     if (rc) {
0203         dev_err(&pdev->dev, "number of channels missing\n");
0204         goto out;
0205     }
0206
0207     rc = device_property_read_u32(&pdev->dev,
0208                       "channel-reset-timeout-cycles",
0209                       &mgmtdev->chreset_timeout_cycles);
0210     if (rc) {
0211         dev_err(&pdev->dev, "channel reset timeout missing\n");
0212         goto out;
0213     }
0214
0215     rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
0216                       &mgmtdev->max_write_request);
0217     if (rc) {
0218         dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
0219         goto out;
0220     }
0221
0222     if (max_write_request &&
0223             (max_write_request != mgmtdev->max_write_request)) {
0224         dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
0225             max_write_request);
0226         mgmtdev->max_write_request = max_write_request;
0227     } else
0228         max_write_request = mgmtdev->max_write_request;
0229
0230     rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
0231                       &mgmtdev->max_read_request);
0232     if (rc) {
0233         dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
0234         goto out;
0235     }
0236     if (max_read_request &&
0237             (max_read_request != mgmtdev->max_read_request)) {
0238         dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
0239             max_read_request);
0240         mgmtdev->max_read_request = max_read_request;
0241     } else
0242         max_read_request = mgmtdev->max_read_request;
0243
0244     rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
0245                       &mgmtdev->max_wr_xactions);
0246     if (rc) {
0247         dev_err(&pdev->dev, "max-write-transactions missing\n");
0248         goto out;
0249     }
0250     if (max_wr_xactions &&
0251             (max_wr_xactions != mgmtdev->max_wr_xactions)) {
0252         dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
0253             max_wr_xactions);
0254         mgmtdev->max_wr_xactions = max_wr_xactions;
0255     } else
0256         max_wr_xactions = mgmtdev->max_wr_xactions;
0257
0258     rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
0259                       &mgmtdev->max_rd_xactions);
0260     if (rc) {
0261         dev_err(&pdev->dev, "max-read-transactions missing\n");
0262         goto out;
0263     }
0264     if (max_rd_xactions &&
0265             (max_rd_xactions != mgmtdev->max_rd_xactions)) {
0266         dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
0267             max_rd_xactions);
0268         mgmtdev->max_rd_xactions = max_rd_xactions;
0269     } else
0270         max_rd_xactions = mgmtdev->max_rd_xactions;
0271
0272     mgmtdev->priority = devm_kcalloc(&pdev->dev,
0273                      mgmtdev->dma_channels,
0274                      sizeof(*mgmtdev->priority),
0275                      GFP_KERNEL);
0276     if (!mgmtdev->priority) {
0277         rc = -ENOMEM;
0278         goto out;
0279     }
0280
0281     mgmtdev->weight = devm_kcalloc(&pdev->dev,
0282                        mgmtdev->dma_channels,
0283                        sizeof(*mgmtdev->weight), GFP_KERNEL);
0284     if (!mgmtdev->weight) {
0285         rc = -ENOMEM;
0286         goto out;
0287     }
0288
0289     rc = hidma_mgmt_setup(mgmtdev);
0290     if (rc) {
0291         dev_err(&pdev->dev, "setup failed\n");
0292         goto out;
0293     }
0294
0295     /* start the HW */
0296     val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
0297     val |= 1;
0298     writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
0299
0300     rc = hidma_mgmt_init_sys(mgmtdev);
0301     if (rc) {
0302         dev_err(&pdev->dev, "sysfs setup failed\n");
0303         goto out;
0304     }
0305
0306     dev_info(&pdev->dev,
0307          "HW rev: %d.%d @ %pa with %d physical channels\n",
0308          mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
0309          &res->start, mgmtdev->dma_channels);
0310
0311     platform_set_drvdata(pdev, mgmtdev);
0312     pm_runtime_mark_last_busy(&pdev->dev);
0313     pm_runtime_put_autosuspend(&pdev->dev);
0314     return 0;
0315 out:
0316     pm_runtime_put_sync_suspend(&pdev->dev);
0317     pm_runtime_disable(&pdev->dev);
0318     return rc;
0319 }
0320
0321 #if IS_ENABLED(CONFIG_ACPI)
0322 static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
0323     {"QCOM8060"},
0324     {},
0325 };
0326 MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
0327 #endif
0328
0329 static const struct of_device_id hidma_mgmt_match[] = {
0330     {.compatible = "qcom,hidma-mgmt-1.0",},
0331     {},
0332 };
0333 MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
0334
0335 static struct platform_driver hidma_mgmt_driver = {
0336     .probe = hidma_mgmt_probe,
0337     .driver = {
0338            .name = "hidma-mgmt",
0339            .of_match_table = hidma_mgmt_match,
0340            .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
0341     },
0342 };
0343
0344 #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
0345 static int object_counter;
0346
0347 static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
0348 {
0349     struct platform_device *pdev_parent = of_find_device_by_node(np);
0350     struct platform_device_info pdevinfo;
0351     struct device_node *child;
0352     struct resource *res;
0353     int ret = 0;
0354
0355     /* allocate a resource array */
0356     res = kcalloc(3, sizeof(*res), GFP_KERNEL);
0357     if (!res)
0358         return -ENOMEM;
0359
0360     for_each_available_child_of_node(np, child) {
0361         struct platform_device *new_pdev;
0362
0363         ret = of_address_to_resource(child, 0, &res[0]);
0364         if (!ret)
0365             goto out;
0366
0367         ret = of_address_to_resource(child, 1, &res[1]);
0368         if (!ret)
0369             goto out;
0370
0371         ret = of_irq_to_resource(child, 0, &res[2]);
0372         if (ret <= 0)
0373             goto out;
0374
0375         memset(&pdevinfo, 0, sizeof(pdevinfo));
0376         pdevinfo.fwnode = &child->fwnode;
0377         pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
0378         pdevinfo.name = child->name;
0379         pdevinfo.id = object_counter++;
0380         pdevinfo.res = res;
0381         pdevinfo.num_res = 3;
0382         pdevinfo.data = NULL;
0383         pdevinfo.size_data = 0;
0384         pdevinfo.dma_mask = DMA_BIT_MASK(64);
0385         new_pdev = platform_device_register_full(&pdevinfo);
0386         if (IS_ERR(new_pdev)) {
0387             ret = PTR_ERR(new_pdev);
0388             goto out;
0389         }
0390         new_pdev->dev.of_node = child;
0391         of_dma_configure(&new_pdev->dev, child, true);
0392         /*
0393          * It is assumed that calling of_msi_configure is safe on
0394          * platforms with or without MSI support.
0395          */
0396         of_msi_configure(&new_pdev->dev, child);
0397     }
0398
0399     kfree(res);
0400
0401     return ret;
0402
0403 out:
0404     of_node_put(child);
0405     kfree(res);
0406
0407     return ret;
0408 }
0409 #endif
0410
0411 static int __init hidma_mgmt_init(void)
0412 {
0413 #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
0414     struct device_node *child;
0415
0416     for_each_matching_node(child, hidma_mgmt_match) {
0417         /* device tree based firmware here */
0418         hidma_mgmt_of_populate_channels(child);
0419     }
0420 #endif
0421     /*
0422      * We do not check for return value here, as it is assumed that
0423      * platform_driver_register must not fail. The reason for this is that
0424      * the (potential) hidma_mgmt_of_populate_channels calls above are not
0425      * cleaned up if it does fail, and to do this work is quite
0426      * complicated. In particular, various calls of of_address_to_resource,
0427      * of_irq_to_resource, platform_device_register_full, of_dma_configure,
0428      * and of_msi_configure which then call other functions and so on, must
0429      * be cleaned up - this is not a trivial exercise.
0430      *
0431      * Currently, this module is not intended to be unloaded, and there is
0432      * no module_exit function defined which does the needed cleanup. For
0433      * this reason, we have to assume success here.
0434      */
0435     platform_driver_register(&hidma_mgmt_driver);
0436
0437     return 0;
0438 }
0439 module_init(hidma_mgmt_init);
0440 MODULE_LICENSE("GPL v2");