dma/ppc4xx/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * 440SPe's DMA engines support header file
0004  *
0005  * 2006-2009 (C) DENX Software Engineering.
0006  *
0007  * Author: Yuri Tikhonov <yur@emcraft.com>
0008  */
0009
0010 #ifndef _PPC440SPE_DMA_H
0011 #define _PPC440SPE_DMA_H
0012
0013 #include <linux/types.h>
0014
0015 /* Number of elements in the array with statical CDBs */
0016 #define MAX_STAT_DMA_CDBS   16
0017 /* Number of DMA engines available on the contoller */
0018 #define DMA_ENGINES_NUM     2
0019
0020 /* Maximum h/w supported number of destinations */
0021 #define DMA_DEST_MAX_NUM    2
0022
0023 /* FIFO's params */
0024 #define DMA0_FIFO_SIZE      0x1000
0025 #define DMA1_FIFO_SIZE      0x1000
0026 #define DMA_FIFO_ENABLE     (1<<12)
0027
0028 /* DMA Configuration Register. Data Transfer Engine PLB Priority: */
0029 #define DMA_CFG_DXEPR_LP    (0<<26)
0030 #define DMA_CFG_DXEPR_HP    (3<<26)
0031 #define DMA_CFG_DXEPR_HHP   (2<<26)
0032 #define DMA_CFG_DXEPR_HHHP  (1<<26)
0033
0034 /* DMA Configuration Register. DMA FIFO Manager PLB Priority: */
0035 #define DMA_CFG_DFMPP_LP    (0<<23)
0036 #define DMA_CFG_DFMPP_HP    (3<<23)
0037 #define DMA_CFG_DFMPP_HHP   (2<<23)
0038 #define DMA_CFG_DFMPP_HHHP  (1<<23)
0039
0040 /* DMA Configuration Register. Force 64-byte Alignment */
0041 #define DMA_CFG_FALGN       (1 << 19)
0042
0043 /*UIC0:*/
0044 #define D0CPF_INT       (1<<12)
0045 #define D0CSF_INT       (1<<11)
0046 #define D1CPF_INT       (1<<10)
0047 #define D1CSF_INT       (1<<9)
0048 /*UIC1:*/
0049 #define DMAE_INT        (1<<9)
0050
0051 /* I2O IOP Interrupt Mask Register */
0052 #define I2O_IOPIM_P0SNE     (1<<3)
0053 #define I2O_IOPIM_P0EM      (1<<5)
0054 #define I2O_IOPIM_P1SNE     (1<<6)
0055 #define I2O_IOPIM_P1EM      (1<<8)
0056
0057 /* DMA CDB fields */
0058 #define DMA_CDB_MSK     (0xF)
0059 #define DMA_CDB_64B_ADDR    (1<<2)
0060 #define DMA_CDB_NO_INT      (1<<3)
0061 #define DMA_CDB_STATUS_MSK  (0x3)
0062 #define DMA_CDB_ADDR_MSK    (0xFFFFFFF0)
0063
0064 /* DMA CDB OpCodes */
0065 #define DMA_CDB_OPC_NO_OP   (0x00)
0066 #define DMA_CDB_OPC_MV_SG1_SG2  (0x01)
0067 #define DMA_CDB_OPC_MULTICAST   (0x05)
0068 #define DMA_CDB_OPC_DFILL128    (0x24)
0069 #define DMA_CDB_OPC_DCHECK128   (0x23)
0070
0071 #define DMA_CUED_XOR_BASE   (0x10000000)
0072 #define DMA_CUED_XOR_HB     (0x00000008)
0073
0074 #ifdef CONFIG_440SP
0075 #define DMA_CUED_MULT1_OFF  0
0076 #define DMA_CUED_MULT2_OFF  8
0077 #define DMA_CUED_MULT3_OFF  16
0078 #define DMA_CUED_REGION_OFF 24
0079 #define DMA_CUED_XOR_WIN_MSK    (0xFC000000)
0080 #else
0081 #define DMA_CUED_MULT1_OFF  2
0082 #define DMA_CUED_MULT2_OFF  10
0083 #define DMA_CUED_MULT3_OFF  18
0084 #define DMA_CUED_REGION_OFF 26
0085 #define DMA_CUED_XOR_WIN_MSK    (0xF0000000)
0086 #endif
0087
0088 #define DMA_CUED_REGION_MSK 0x3
0089 #define DMA_RXOR123     0x0
0090 #define DMA_RXOR124     0x1
0091 #define DMA_RXOR125     0x2
0092 #define DMA_RXOR12      0x3
0093
0094 /* S/G addresses */
0095 #define DMA_CDB_SG_SRC      1
0096 #define DMA_CDB_SG_DST1     2
0097 #define DMA_CDB_SG_DST2     3
0098
0099 /*
0100  * DMAx engines Command Descriptor Block Type
0101  */
0102 struct dma_cdb {
0103     /*
0104      * Basic CDB structure (Table 20-17, p.499, 440spe_um_1_22.pdf)
0105      */
0106     u8  pad0[2];        /* reserved */
0107     u8  attr;       /* attributes */
0108     u8  opc;        /* opcode */
0109     u32 sg1u;       /* upper SG1 address */
0110     u32 sg1l;       /* lower SG1 address */
0111     u32 cnt;        /* SG count, 3B used */
0112     u32 sg2u;       /* upper SG2 address */
0113     u32 sg2l;       /* lower SG2 address */
0114     u32 sg3u;       /* upper SG3 address */
0115     u32 sg3l;       /* lower SG3 address */
0116 };
0117
0118 /*
0119  * DMAx hardware registers (p.515 in 440SPe UM 1.22)
0120  */
0121 struct dma_regs {
0122     u32 cpfpl;
0123     u32 cpfph;
0124     u32 csfpl;
0125     u32 csfph;
0126     u32 dsts;
0127     u32 cfg;
0128     u8  pad0[0x8];
0129     u16 cpfhp;
0130     u16 cpftp;
0131     u16 csfhp;
0132     u16 csftp;
0133     u8  pad1[0x8];
0134     u32 acpl;
0135     u32 acph;
0136     u32 s1bpl;
0137     u32 s1bph;
0138     u32 s2bpl;
0139     u32 s2bph;
0140     u32 s3bpl;
0141     u32 s3bph;
0142     u8  pad2[0x10];
0143     u32 earl;
0144     u32 earh;
0145     u8  pad3[0x8];
0146     u32 seat;
0147     u32 sead;
0148     u32 op;
0149     u32 fsiz;
0150 };
0151
0152 /*
0153  * I2O hardware registers (p.528 in 440SPe UM 1.22)
0154  */
0155 struct i2o_regs {
0156     u32 ists;
0157     u32 iseat;
0158     u32 isead;
0159     u8  pad0[0x14];
0160     u32 idbel;
0161     u8  pad1[0xc];
0162     u32 ihis;
0163     u32 ihim;
0164     u8  pad2[0x8];
0165     u32 ihiq;
0166     u32 ihoq;
0167     u8  pad3[0x8];
0168     u32 iopis;
0169     u32 iopim;
0170     u32 iopiq;
0171     u8  iopoq;
0172     u8  pad4[3];
0173     u16 iiflh;
0174     u16 iiflt;
0175     u16 iiplh;
0176     u16 iiplt;
0177     u16 ioflh;
0178     u16 ioflt;
0179     u16 ioplh;
0180     u16 ioplt;
0181     u32 iidc;
0182     u32 ictl;
0183     u32 ifcpp;
0184     u8  pad5[0x4];
0185     u16 mfac0;
0186     u16 mfac1;
0187     u16 mfac2;
0188     u16 mfac3;
0189     u16 mfac4;
0190     u16 mfac5;
0191     u16 mfac6;
0192     u16 mfac7;
0193     u16 ifcfh;
0194     u16 ifcht;
0195     u8  pad6[0x4];
0196     u32 iifmc;
0197     u32 iodb;
0198     u32 iodbc;
0199     u32 ifbal;
0200     u32 ifbah;
0201     u32 ifsiz;
0202     u32 ispd0;
0203     u32 ispd1;
0204     u32 ispd2;
0205     u32 ispd3;
0206     u32 ihipl;
0207     u32 ihiph;
0208     u32 ihopl;
0209     u32 ihoph;
0210     u32 iiipl;
0211     u32 iiiph;
0212     u32 iiopl;
0213     u32 iioph;
0214     u32 ifcpl;
0215     u32 ifcph;
0216     u8  pad7[0x8];
0217     u32 iopt;
0218 };
0219
0220 #endif /* _PPC440SPE_DMA_H */