dma/ppc4xx/adma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * 2006-2009 (C) DENX Software Engineering.
0004  *
0005  * Author: Yuri Tikhonov <yur@emcraft.com>
0006  */
0007
0008 #ifndef _PPC440SPE_ADMA_H
0009 #define _PPC440SPE_ADMA_H
0010
0011 #include <linux/types.h>
0012 #include "dma.h"
0013 #include "xor.h"
0014
0015 #define to_ppc440spe_adma_chan(chan) \
0016         container_of(chan, struct ppc440spe_adma_chan, common)
0017 #define to_ppc440spe_adma_device(dev) \
0018         container_of(dev, struct ppc440spe_adma_device, common)
0019 #define tx_to_ppc440spe_adma_slot(tx) \
0020         container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
0021
0022 /* Default polynomial (for 440SP is only available) */
0023 #define PPC440SPE_DEFAULT_POLY  0x4d
0024
0025 #define PPC440SPE_ADMA_ENGINES_NUM  (XOR_ENGINES_NUM + DMA_ENGINES_NUM)
0026
0027 #define PPC440SPE_ADMA_WATCHDOG_MSEC    3
0028 #define PPC440SPE_ADMA_THRESHOLD    1
0029
0030 #define PPC440SPE_DMA0_ID   0
0031 #define PPC440SPE_DMA1_ID   1
0032 #define PPC440SPE_XOR_ID    2
0033
0034 #define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT   0xFFFFFFUL
0035 /* this is the XOR_CBBCR width */
0036 #define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT   (1 << 31)
0037 #define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
0038
0039 #define PPC440SPE_RXOR_RUN  0
0040
0041 #define MQ0_CF2H_RXOR_BS_MASK   0x1FF
0042
0043 #undef ADMA_LL_DEBUG
0044
0045 /**
0046  * struct ppc440spe_adma_device - internal representation of an ADMA device
0047  * @dev: device
0048  * @dma_reg: base for DMAx register access
0049  * @xor_reg: base for XOR register access
0050  * @i2o_reg: base for I2O register access
0051  * @id: HW ADMA Device selector
0052  * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
0053  * @dma_desc_pool: base of DMA descriptor region (DMA address)
0054  * @pool_size: size of the pool
0055  * @irq: DMAx or XOR irq number
0056  * @err_irq: DMAx error irq number
0057  * @common: embedded struct dma_device
0058  */
0059 struct ppc440spe_adma_device {
0060     struct device *dev;
0061     struct dma_regs __iomem *dma_reg;
0062     struct xor_regs __iomem *xor_reg;
0063     struct i2o_regs __iomem *i2o_reg;
0064     int id;
0065     void *dma_desc_pool_virt;
0066     dma_addr_t dma_desc_pool;
0067     size_t pool_size;
0068     int irq;
0069     int err_irq;
0070     struct dma_device common;
0071 };
0072
0073 /**
0074  * struct ppc440spe_adma_chan - internal representation of an ADMA channel
0075  * @lock: serializes enqueue/dequeue operations to the slot pool
0076  * @device: parent device
0077  * @chain: device chain view of the descriptors
0078  * @common: common dmaengine channel object members
0079  * @all_slots: complete domain of slots usable by the channel
0080  * @pending: allows batching of hardware operations
0081  * @slots_allocated: records the actual size of the descriptor slot pool
0082  * @hw_chain_inited: h/w descriptor chain initialization flag
0083  * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
0084  * @needs_unmap: if buffers should not be unmapped upon final processing
0085  * @pdest_page: P destination page for async validate operation
0086  * @qdest_page: Q destination page for async validate operation
0087  * @pdest: P dma addr for async validate operation
0088  * @qdest: Q dma addr for async validate operation
0089  */
0090 struct ppc440spe_adma_chan {
0091     spinlock_t lock;
0092     struct ppc440spe_adma_device *device;
0093     struct list_head chain;
0094     struct dma_chan common;
0095     struct list_head all_slots;
0096     struct ppc440spe_adma_desc_slot *last_used;
0097     int pending;
0098     int slots_allocated;
0099     int hw_chain_inited;
0100     struct tasklet_struct irq_tasklet;
0101     u8 needs_unmap;
0102     struct page *pdest_page;
0103     struct page *qdest_page;
0104     dma_addr_t pdest;
0105     dma_addr_t qdest;
0106 };
0107
0108 struct ppc440spe_rxor {
0109     u32 addrl;
0110     u32 addrh;
0111     int len;
0112     int xor_count;
0113     int addr_count;
0114     int desc_count;
0115     int state;
0116 };
0117
0118 /**
0119  * struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
0120  * @phys: hardware address of the hardware descriptor chain
0121  * @group_head: first operation in a transaction
0122  * @hw_next: pointer to the next descriptor in chain
0123  * @async_tx: support for the async_tx api
0124  * @slot_node: node on the iop_adma_chan.all_slots list
0125  * @chain_node: node on the op_adma_chan.chain list
0126  * @group_list: list of slots that make up a multi-descriptor transaction
0127  *              for example transfer lengths larger than the supported hw max
0128  * @unmap_len: transaction bytecount
0129  * @hw_desc: virtual address of the hardware descriptor chain
0130  * @stride: currently chained or not
0131  * @idx: pool index
0132  * @slot_cnt: total slots used in an transaction (group of operations)
0133  * @src_cnt: number of sources set in this descriptor
0134  * @dst_cnt: number of destinations set in the descriptor
0135  * @slots_per_op: number of slots per operation
0136  * @descs_per_op: number of slot per P/Q operation see comment
0137  *                for ppc440spe_prep_dma_pqxor function
0138  * @flags: desc state/type
0139  * @reverse_flags: 1 if a corresponding rxor address uses reversed address order
0140  * @xor_check_result: result of zero sum
0141  * @crc32_result: result crc calculation
0142  */
0143 struct ppc440spe_adma_desc_slot {
0144     dma_addr_t phys;
0145     struct ppc440spe_adma_desc_slot *group_head;
0146     struct ppc440spe_adma_desc_slot *hw_next;
0147     struct dma_async_tx_descriptor async_tx;
0148     struct list_head slot_node;
0149     struct list_head chain_node; /* node in channel ops list */
0150     struct list_head group_list; /* list */
0151     unsigned int unmap_len;
0152     void *hw_desc;
0153     u16 stride;
0154     u16 idx;
0155     u16 slot_cnt;
0156     u8 src_cnt;
0157     u8 dst_cnt;
0158     u8 slots_per_op;
0159     u8 descs_per_op;
0160     unsigned long flags;
0161     unsigned long reverse_flags[8];
0162
0163 #define PPC440SPE_DESC_INT  0   /* generate interrupt on complete */
0164 #define PPC440SPE_ZERO_P    1   /* clear P destionaion */
0165 #define PPC440SPE_ZERO_Q    2   /* clear Q destination */
0166 #define PPC440SPE_COHERENT  3   /* src/dst are coherent */
0167
0168 #define PPC440SPE_DESC_WXOR 4   /* WXORs are in chain */
0169 #define PPC440SPE_DESC_RXOR 5   /* RXOR is in chain */
0170
0171 #define PPC440SPE_DESC_RXOR123  8   /* CDB for RXOR123 operation */
0172 #define PPC440SPE_DESC_RXOR124  9   /* CDB for RXOR124 operation */
0173 #define PPC440SPE_DESC_RXOR125  10  /* CDB for RXOR125 operation */
0174 #define PPC440SPE_DESC_RXOR12   11  /* CDB for RXOR12 operation */
0175 #define PPC440SPE_DESC_RXOR_REV 12  /* CDB has srcs in reversed order */
0176
0177 #define PPC440SPE_DESC_PCHECK   13
0178 #define PPC440SPE_DESC_QCHECK   14
0179
0180 #define PPC440SPE_DESC_RXOR_MSK 0x3
0181
0182     struct ppc440spe_rxor rxor_cursor;
0183
0184     union {
0185         u32 *xor_check_result;
0186         u32 *crc32_result;
0187     };
0188 };
0189
0190 #endif /* _PPC440SPE_ADMA_H */