drivers/dma/mv_xor.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2007, 2008, Marvell International Ltd.
0004  */
0005
0006 #ifndef MV_XOR_H
0007 #define MV_XOR_H
0008
0009 #include <linux/types.h>
0010 #include <linux/io.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/interrupt.h>
0013
0014 #define MV_XOR_POOL_SIZE        (MV_XOR_SLOT_SIZE * 3072)
0015 #define MV_XOR_SLOT_SIZE        64
0016 #define MV_XOR_THRESHOLD        1
0017 #define MV_XOR_MAX_CHANNELS             2
0018
0019 #define MV_XOR_MIN_BYTE_COUNT       SZ_128
0020 #define MV_XOR_MAX_BYTE_COUNT       (SZ_16M - 1)
0021
0022 /* Values for the XOR_CONFIG register */
0023 #define XOR_OPERATION_MODE_XOR      0
0024 #define XOR_OPERATION_MODE_MEMCPY   2
0025 #define XOR_OPERATION_MODE_IN_DESC      7
0026 #define XOR_DESCRIPTOR_SWAP     BIT(14)
0027 #define XOR_DESC_SUCCESS        0x40000000
0028
0029 #define XOR_DESC_OPERATION_XOR          (0 << 24)
0030 #define XOR_DESC_OPERATION_CRC32C       (1 << 24)
0031 #define XOR_DESC_OPERATION_MEMCPY       (2 << 24)
0032
0033 #define XOR_DESC_DMA_OWNED      BIT(31)
0034 #define XOR_DESC_EOD_INT_EN     BIT(31)
0035
0036 #define XOR_CURR_DESC(chan) (chan->mmr_high_base + 0x10 + (chan->idx * 4))
0037 #define XOR_NEXT_DESC(chan) (chan->mmr_high_base + 0x00 + (chan->idx * 4))
0038 #define XOR_BYTE_COUNT(chan)    (chan->mmr_high_base + 0x20 + (chan->idx * 4))
0039 #define XOR_DEST_POINTER(chan)  (chan->mmr_high_base + 0xB0 + (chan->idx * 4))
0040 #define XOR_BLOCK_SIZE(chan)    (chan->mmr_high_base + 0xC0 + (chan->idx * 4))
0041 #define XOR_INIT_VALUE_LOW(chan)    (chan->mmr_high_base + 0xE0)
0042 #define XOR_INIT_VALUE_HIGH(chan)   (chan->mmr_high_base + 0xE4)
0043
0044 #define XOR_CONFIG(chan)    (chan->mmr_base + 0x10 + (chan->idx * 4))
0045 #define XOR_ACTIVATION(chan)    (chan->mmr_base + 0x20 + (chan->idx * 4))
0046 #define XOR_INTR_CAUSE(chan)    (chan->mmr_base + 0x30)
0047 #define XOR_INTR_MASK(chan) (chan->mmr_base + 0x40)
0048 #define XOR_ERROR_CAUSE(chan)   (chan->mmr_base + 0x50)
0049 #define XOR_ERROR_ADDR(chan)    (chan->mmr_base + 0x60)
0050
0051 #define XOR_INT_END_OF_DESC BIT(0)
0052 #define XOR_INT_END_OF_CHAIN    BIT(1)
0053 #define XOR_INT_STOPPED     BIT(2)
0054 #define XOR_INT_PAUSED      BIT(3)
0055 #define XOR_INT_ERR_DECODE  BIT(4)
0056 #define XOR_INT_ERR_RDPROT  BIT(5)
0057 #define XOR_INT_ERR_WRPROT  BIT(6)
0058 #define XOR_INT_ERR_OWN     BIT(7)
0059 #define XOR_INT_ERR_PAR     BIT(8)
0060 #define XOR_INT_ERR_MBUS    BIT(9)
0061
0062 #define XOR_INTR_ERRORS     (XOR_INT_ERR_DECODE | XOR_INT_ERR_RDPROT | \
0063                  XOR_INT_ERR_WRPROT | XOR_INT_ERR_OWN    | \
0064                  XOR_INT_ERR_PAR    | XOR_INT_ERR_MBUS)
0065
0066 #define XOR_INTR_MASK_VALUE (XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | \
0067                  XOR_INT_STOPPED     | XOR_INTR_ERRORS)
0068
0069 #define WINDOW_BASE(w)      (0x50 + ((w) << 2))
0070 #define WINDOW_SIZE(w)      (0x70 + ((w) << 2))
0071 #define WINDOW_REMAP_HIGH(w)    (0x90 + ((w) << 2))
0072 #define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
0073 #define WINDOW_OVERRIDE_CTRL(chan)  (0xA0 + ((chan) << 2))
0074
0075 #define WINDOW_COUNT        8
0076
0077 struct mv_xor_device {
0078     void __iomem         *xor_base;
0079     void __iomem         *xor_high_base;
0080     struct clk       *clk;
0081     struct mv_xor_chan   *channels[MV_XOR_MAX_CHANNELS];
0082     int          xor_type;
0083
0084     u32                  win_start[WINDOW_COUNT];
0085     u32                  win_end[WINDOW_COUNT];
0086 };
0087
0088 /**
0089  * struct mv_xor_chan - internal representation of a XOR channel
0090  * @pending: allows batching of hardware operations
0091  * @lock: serializes enqueue/dequeue operations to the descriptors pool
0092  * @mmr_base: memory mapped register base
0093  * @idx: the index of the xor channel
0094  * @chain: device chain view of the descriptors
0095  * @free_slots: free slots usable by the channel
0096  * @allocated_slots: slots allocated by the driver
0097  * @completed_slots: slots completed by HW but still need to be acked
0098  * @device: parent device
0099  * @common: common dmaengine channel object members
0100  * @slots_allocated: records the actual size of the descriptor slot pool
0101  * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
0102  * @op_in_desc: new mode of driver, each op is writen to descriptor.
0103  */
0104 struct mv_xor_chan {
0105     int         pending;
0106     spinlock_t      lock; /* protects the descriptor slot pool */
0107     void __iomem        *mmr_base;
0108     void __iomem        *mmr_high_base;
0109     unsigned int        idx;
0110     int                     irq;
0111     struct list_head    chain;
0112     struct list_head    free_slots;
0113     struct list_head    allocated_slots;
0114     struct list_head    completed_slots;
0115     dma_addr_t      dma_desc_pool;
0116     void            *dma_desc_pool_virt;
0117     size_t                  pool_size;
0118     struct dma_device   dmadev;
0119     struct dma_chan     dmachan;
0120     int         slots_allocated;
0121     struct tasklet_struct   irq_tasklet;
0122     int                     op_in_desc;
0123     char            dummy_src[MV_XOR_MIN_BYTE_COUNT];
0124     char            dummy_dst[MV_XOR_MIN_BYTE_COUNT];
0125     dma_addr_t      dummy_src_addr, dummy_dst_addr;
0126     u32                     saved_config_reg, saved_int_mask_reg;
0127
0128     struct mv_xor_device    *xordev;
0129 };
0130
0131 /**
0132  * struct mv_xor_desc_slot - software descriptor
0133  * @node: node on the mv_xor_chan lists
0134  * @hw_desc: virtual address of the hardware descriptor chain
0135  * @phys: hardware address of the hardware descriptor chain
0136  * @slot_used: slot in use or not
0137  * @idx: pool index
0138  * @tx_list: list of slots that make up a multi-descriptor transaction
0139  * @async_tx: support for the async_tx api
0140  */
0141 struct mv_xor_desc_slot {
0142     struct list_head    node;
0143     struct list_head    sg_tx_list;
0144     enum dma_transaction_type   type;
0145     void            *hw_desc;
0146     u16         idx;
0147     struct dma_async_tx_descriptor  async_tx;
0148 };
0149
0150 /*
0151  * This structure describes XOR descriptor size 64bytes. The
0152  * mv_phy_src_idx() macro must be used when indexing the values of the
0153  * phy_src_addr[] array. This is due to the fact that the 'descriptor
0154  * swap' feature, used on big endian systems, swaps descriptors data
0155  * within blocks of 8 bytes. So two consecutive values of the
0156  * phy_src_addr[] array are actually swapped in big-endian, which
0157  * explains the different mv_phy_src_idx() implementation.
0158  */
0159 #if defined(__LITTLE_ENDIAN)
0160 struct mv_xor_desc {
0161     u32 status;     /* descriptor execution status */
0162     u32 crc32_result;   /* result of CRC-32 calculation */
0163     u32 desc_command;   /* type of operation to be carried out */
0164     u32 phy_next_desc;  /* next descriptor address pointer */
0165     u32 byte_count;     /* size of src/dst blocks in bytes */
0166     u32 phy_dest_addr;  /* destination block address */
0167     u32 phy_src_addr[8];    /* source block addresses */
0168     u32 reserved0;
0169     u32 reserved1;
0170 };
0171 #define mv_phy_src_idx(src_idx) (src_idx)
0172 #else
0173 struct mv_xor_desc {
0174     u32 crc32_result;   /* result of CRC-32 calculation */
0175     u32 status;     /* descriptor execution status */
0176     u32 phy_next_desc;  /* next descriptor address pointer */
0177     u32 desc_command;   /* type of operation to be carried out */
0178     u32 phy_dest_addr;  /* destination block address */
0179     u32 byte_count;     /* size of src/dst blocks in bytes */
0180     u32 phy_src_addr[8];    /* source block addresses */
0181     u32 reserved1;
0182     u32 reserved0;
0183 };
0184 #define mv_phy_src_idx(src_idx) (src_idx ^ 1)
0185 #endif
0186
0187 #define to_mv_sw_desc(addr_hw_desc)     \
0188     container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
0189
0190 #define mv_hw_desc_slot_idx(hw_desc, idx)   \
0191     ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
0192
0193 #endif