Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2019 Linaro Ltd.
0004 // Copyright (C) 2019 Socionext Inc.
0005 
0006 #include <linux/bits.h>
0007 #include <linux/clk.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/list.h>
0012 #include <linux/module.h>
0013 #include <linux/of_dma.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/slab.h>
0016 #include <linux/types.h>
0017 #include <linux/bitfield.h>
0018 
0019 #include "virt-dma.h"
0020 
0021 #define MLB_HDMAC_DMACR     0x0 /* global */
0022 #define MLB_HDMAC_DE        BIT(31)
0023 #define MLB_HDMAC_DS        BIT(30)
0024 #define MLB_HDMAC_PR        BIT(28)
0025 #define MLB_HDMAC_DH        GENMASK(27, 24)
0026 
0027 #define MLB_HDMAC_CH_STRIDE 0x10
0028 
0029 #define MLB_HDMAC_DMACA     0x0 /* channel */
0030 #define MLB_HDMAC_EB        BIT(31)
0031 #define MLB_HDMAC_PB        BIT(30)
0032 #define MLB_HDMAC_ST        BIT(29)
0033 #define MLB_HDMAC_IS        GENMASK(28, 24)
0034 #define MLB_HDMAC_BT        GENMASK(23, 20)
0035 #define MLB_HDMAC_BC        GENMASK(19, 16)
0036 #define MLB_HDMAC_TC        GENMASK(15, 0)
0037 #define MLB_HDMAC_DMACB     0x4
0038 #define MLB_HDMAC_TT        GENMASK(31, 30)
0039 #define MLB_HDMAC_MS        GENMASK(29, 28)
0040 #define MLB_HDMAC_TW        GENMASK(27, 26)
0041 #define MLB_HDMAC_FS        BIT(25)
0042 #define MLB_HDMAC_FD        BIT(24)
0043 #define MLB_HDMAC_RC        BIT(23)
0044 #define MLB_HDMAC_RS        BIT(22)
0045 #define MLB_HDMAC_RD        BIT(21)
0046 #define MLB_HDMAC_EI        BIT(20)
0047 #define MLB_HDMAC_CI        BIT(19)
0048 #define HDMAC_PAUSE     0x7
0049 #define MLB_HDMAC_SS        GENMASK(18, 16)
0050 #define MLB_HDMAC_SP        GENMASK(15, 12)
0051 #define MLB_HDMAC_DP        GENMASK(11, 8)
0052 #define MLB_HDMAC_DMACSA    0x8
0053 #define MLB_HDMAC_DMACDA    0xc
0054 
0055 #define MLB_HDMAC_BUSWIDTHS     (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
0056                     BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
0057                     BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
0058 
0059 struct milbeaut_hdmac_desc {
0060     struct virt_dma_desc vd;
0061     struct scatterlist *sgl;
0062     unsigned int sg_len;
0063     unsigned int sg_cur;
0064     enum dma_transfer_direction dir;
0065 };
0066 
0067 struct milbeaut_hdmac_chan {
0068     struct virt_dma_chan vc;
0069     struct milbeaut_hdmac_device *mdev;
0070     struct milbeaut_hdmac_desc *md;
0071     void __iomem *reg_ch_base;
0072     unsigned int slave_id;
0073     struct dma_slave_config cfg;
0074 };
0075 
0076 struct milbeaut_hdmac_device {
0077     struct dma_device ddev;
0078     struct clk *clk;
0079     void __iomem *reg_base;
0080     struct milbeaut_hdmac_chan channels[];
0081 };
0082 
0083 static struct milbeaut_hdmac_chan *
0084 to_milbeaut_hdmac_chan(struct virt_dma_chan *vc)
0085 {
0086     return container_of(vc, struct milbeaut_hdmac_chan, vc);
0087 }
0088 
0089 static struct milbeaut_hdmac_desc *
0090 to_milbeaut_hdmac_desc(struct virt_dma_desc *vd)
0091 {
0092     return container_of(vd, struct milbeaut_hdmac_desc, vd);
0093 }
0094 
0095 /* mc->vc.lock must be held by caller */
0096 static struct milbeaut_hdmac_desc *
0097 milbeaut_hdmac_next_desc(struct milbeaut_hdmac_chan *mc)
0098 {
0099     struct virt_dma_desc *vd;
0100 
0101     vd = vchan_next_desc(&mc->vc);
0102     if (!vd) {
0103         mc->md = NULL;
0104         return NULL;
0105     }
0106 
0107     list_del(&vd->node);
0108 
0109     mc->md = to_milbeaut_hdmac_desc(vd);
0110 
0111     return mc->md;
0112 }
0113 
0114 /* mc->vc.lock must be held by caller */
0115 static void milbeaut_chan_start(struct milbeaut_hdmac_chan *mc,
0116                 struct milbeaut_hdmac_desc *md)
0117 {
0118     struct scatterlist *sg;
0119     u32 cb, ca, src_addr, dest_addr, len;
0120     u32 width, burst;
0121 
0122     sg = &md->sgl[md->sg_cur];
0123     len = sg_dma_len(sg);
0124 
0125     cb = MLB_HDMAC_CI | MLB_HDMAC_EI;
0126     if (md->dir == DMA_MEM_TO_DEV) {
0127         cb |= MLB_HDMAC_FD;
0128         width = mc->cfg.dst_addr_width;
0129         burst = mc->cfg.dst_maxburst;
0130         src_addr = sg_dma_address(sg);
0131         dest_addr = mc->cfg.dst_addr;
0132     } else {
0133         cb |= MLB_HDMAC_FS;
0134         width = mc->cfg.src_addr_width;
0135         burst = mc->cfg.src_maxburst;
0136         src_addr = mc->cfg.src_addr;
0137         dest_addr = sg_dma_address(sg);
0138     }
0139     cb |= FIELD_PREP(MLB_HDMAC_TW, (width >> 1));
0140     cb |= FIELD_PREP(MLB_HDMAC_MS, 2);
0141 
0142     writel_relaxed(MLB_HDMAC_DE, mc->mdev->reg_base + MLB_HDMAC_DMACR);
0143     writel_relaxed(src_addr, mc->reg_ch_base + MLB_HDMAC_DMACSA);
0144     writel_relaxed(dest_addr, mc->reg_ch_base + MLB_HDMAC_DMACDA);
0145     writel_relaxed(cb, mc->reg_ch_base + MLB_HDMAC_DMACB);
0146 
0147     ca = FIELD_PREP(MLB_HDMAC_IS, mc->slave_id);
0148     if (burst == 16)
0149         ca |= FIELD_PREP(MLB_HDMAC_BT, 0xf);
0150     else if (burst == 8)
0151         ca |= FIELD_PREP(MLB_HDMAC_BT, 0xd);
0152     else if (burst == 4)
0153         ca |= FIELD_PREP(MLB_HDMAC_BT, 0xb);
0154     burst *= width;
0155     ca |= FIELD_PREP(MLB_HDMAC_TC, (len / burst - 1));
0156     writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
0157     ca |= MLB_HDMAC_EB;
0158     writel_relaxed(ca, mc->reg_ch_base + MLB_HDMAC_DMACA);
0159 }
0160 
0161 /* mc->vc.lock must be held by caller */
0162 static void milbeaut_hdmac_start(struct milbeaut_hdmac_chan *mc)
0163 {
0164     struct milbeaut_hdmac_desc *md;
0165 
0166     md = milbeaut_hdmac_next_desc(mc);
0167     if (md)
0168         milbeaut_chan_start(mc, md);
0169 }
0170 
0171 static irqreturn_t milbeaut_hdmac_interrupt(int irq, void *dev_id)
0172 {
0173     struct milbeaut_hdmac_chan *mc = dev_id;
0174     struct milbeaut_hdmac_desc *md;
0175     u32 val;
0176 
0177     spin_lock(&mc->vc.lock);
0178 
0179     /* Ack and Disable irqs */
0180     val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACB);
0181     val &= ~(FIELD_PREP(MLB_HDMAC_SS, HDMAC_PAUSE));
0182     writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
0183     val &= ~MLB_HDMAC_EI;
0184     val &= ~MLB_HDMAC_CI;
0185     writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACB);
0186 
0187     md = mc->md;
0188     if (!md)
0189         goto out;
0190 
0191     md->sg_cur++;
0192 
0193     if (md->sg_cur >= md->sg_len) {
0194         vchan_cookie_complete(&md->vd);
0195         md = milbeaut_hdmac_next_desc(mc);
0196         if (!md)
0197             goto out;
0198     }
0199 
0200     milbeaut_chan_start(mc, md);
0201 
0202 out:
0203     spin_unlock(&mc->vc.lock);
0204     return IRQ_HANDLED;
0205 }
0206 
0207 static void milbeaut_hdmac_free_chan_resources(struct dma_chan *chan)
0208 {
0209     vchan_free_chan_resources(to_virt_chan(chan));
0210 }
0211 
0212 static int
0213 milbeaut_hdmac_chan_config(struct dma_chan *chan, struct dma_slave_config *cfg)
0214 {
0215     struct virt_dma_chan *vc = to_virt_chan(chan);
0216     struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
0217 
0218     spin_lock(&mc->vc.lock);
0219     mc->cfg = *cfg;
0220     spin_unlock(&mc->vc.lock);
0221 
0222     return 0;
0223 }
0224 
0225 static int milbeaut_hdmac_chan_pause(struct dma_chan *chan)
0226 {
0227     struct virt_dma_chan *vc = to_virt_chan(chan);
0228     struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
0229     u32 val;
0230 
0231     spin_lock(&mc->vc.lock);
0232     val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
0233     val |= MLB_HDMAC_PB;
0234     writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
0235     spin_unlock(&mc->vc.lock);
0236 
0237     return 0;
0238 }
0239 
0240 static int milbeaut_hdmac_chan_resume(struct dma_chan *chan)
0241 {
0242     struct virt_dma_chan *vc = to_virt_chan(chan);
0243     struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
0244     u32 val;
0245 
0246     spin_lock(&mc->vc.lock);
0247     val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
0248     val &= ~MLB_HDMAC_PB;
0249     writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
0250     spin_unlock(&mc->vc.lock);
0251 
0252     return 0;
0253 }
0254 
0255 static struct dma_async_tx_descriptor *
0256 milbeaut_hdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
0257                  unsigned int sg_len,
0258                  enum dma_transfer_direction direction,
0259                  unsigned long flags, void *context)
0260 {
0261     struct virt_dma_chan *vc = to_virt_chan(chan);
0262     struct milbeaut_hdmac_desc *md;
0263     int i;
0264 
0265     if (!is_slave_direction(direction))
0266         return NULL;
0267 
0268     md = kzalloc(sizeof(*md), GFP_NOWAIT);
0269     if (!md)
0270         return NULL;
0271 
0272     md->sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
0273     if (!md->sgl) {
0274         kfree(md);
0275         return NULL;
0276     }
0277 
0278     for (i = 0; i < sg_len; i++)
0279         md->sgl[i] = sgl[i];
0280 
0281     md->sg_len = sg_len;
0282     md->dir = direction;
0283 
0284     return vchan_tx_prep(vc, &md->vd, flags);
0285 }
0286 
0287 static int milbeaut_hdmac_terminate_all(struct dma_chan *chan)
0288 {
0289     struct virt_dma_chan *vc = to_virt_chan(chan);
0290     struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
0291     unsigned long flags;
0292     u32 val;
0293 
0294     LIST_HEAD(head);
0295 
0296     spin_lock_irqsave(&vc->lock, flags);
0297 
0298     val = readl_relaxed(mc->reg_ch_base + MLB_HDMAC_DMACA);
0299     val &= ~MLB_HDMAC_EB; /* disable the channel */
0300     writel_relaxed(val, mc->reg_ch_base + MLB_HDMAC_DMACA);
0301 
0302     if (mc->md) {
0303         vchan_terminate_vdesc(&mc->md->vd);
0304         mc->md = NULL;
0305     }
0306 
0307     vchan_get_all_descriptors(vc, &head);
0308 
0309     spin_unlock_irqrestore(&vc->lock, flags);
0310 
0311     vchan_dma_desc_free_list(vc, &head);
0312 
0313     return 0;
0314 }
0315 
0316 static void milbeaut_hdmac_synchronize(struct dma_chan *chan)
0317 {
0318     vchan_synchronize(to_virt_chan(chan));
0319 }
0320 
0321 static enum dma_status milbeaut_hdmac_tx_status(struct dma_chan *chan,
0322                         dma_cookie_t cookie,
0323                         struct dma_tx_state *txstate)
0324 {
0325     struct virt_dma_chan *vc;
0326     struct virt_dma_desc *vd;
0327     struct milbeaut_hdmac_chan *mc;
0328     struct milbeaut_hdmac_desc *md = NULL;
0329     enum dma_status stat;
0330     unsigned long flags;
0331     int i;
0332 
0333     stat = dma_cookie_status(chan, cookie, txstate);
0334     /* Return immediately if we do not need to compute the residue. */
0335     if (stat == DMA_COMPLETE || !txstate)
0336         return stat;
0337 
0338     vc = to_virt_chan(chan);
0339 
0340     spin_lock_irqsave(&vc->lock, flags);
0341 
0342     mc = to_milbeaut_hdmac_chan(vc);
0343 
0344     /* residue from the on-flight chunk */
0345     if (mc->md && mc->md->vd.tx.cookie == cookie) {
0346         struct scatterlist *sg;
0347         u32 done;
0348 
0349         md = mc->md;
0350         sg = &md->sgl[md->sg_cur];
0351 
0352         if (md->dir == DMA_DEV_TO_MEM)
0353             done = readl_relaxed(mc->reg_ch_base
0354                          + MLB_HDMAC_DMACDA);
0355         else
0356             done = readl_relaxed(mc->reg_ch_base
0357                          + MLB_HDMAC_DMACSA);
0358         done -= sg_dma_address(sg);
0359 
0360         txstate->residue = -done;
0361     }
0362 
0363     if (!md) {
0364         vd = vchan_find_desc(vc, cookie);
0365         if (vd)
0366             md = to_milbeaut_hdmac_desc(vd);
0367     }
0368 
0369     if (md) {
0370         /* residue from the queued chunks */
0371         for (i = md->sg_cur; i < md->sg_len; i++)
0372             txstate->residue += sg_dma_len(&md->sgl[i]);
0373     }
0374 
0375     spin_unlock_irqrestore(&vc->lock, flags);
0376 
0377     return stat;
0378 }
0379 
0380 static void milbeaut_hdmac_issue_pending(struct dma_chan *chan)
0381 {
0382     struct virt_dma_chan *vc = to_virt_chan(chan);
0383     struct milbeaut_hdmac_chan *mc = to_milbeaut_hdmac_chan(vc);
0384     unsigned long flags;
0385 
0386     spin_lock_irqsave(&vc->lock, flags);
0387 
0388     if (vchan_issue_pending(vc) && !mc->md)
0389         milbeaut_hdmac_start(mc);
0390 
0391     spin_unlock_irqrestore(&vc->lock, flags);
0392 }
0393 
0394 static void milbeaut_hdmac_desc_free(struct virt_dma_desc *vd)
0395 {
0396     struct milbeaut_hdmac_desc *md = to_milbeaut_hdmac_desc(vd);
0397 
0398     kfree(md->sgl);
0399     kfree(md);
0400 }
0401 
0402 static struct dma_chan *
0403 milbeaut_hdmac_xlate(struct of_phandle_args *dma_spec, struct of_dma *of_dma)
0404 {
0405     struct milbeaut_hdmac_device *mdev = of_dma->of_dma_data;
0406     struct milbeaut_hdmac_chan *mc;
0407     struct virt_dma_chan *vc;
0408     struct dma_chan *chan;
0409 
0410     if (dma_spec->args_count != 1)
0411         return NULL;
0412 
0413     chan = dma_get_any_slave_channel(&mdev->ddev);
0414     if (!chan)
0415         return NULL;
0416 
0417     vc = to_virt_chan(chan);
0418     mc = to_milbeaut_hdmac_chan(vc);
0419     mc->slave_id = dma_spec->args[0];
0420 
0421     return chan;
0422 }
0423 
0424 static int milbeaut_hdmac_chan_init(struct platform_device *pdev,
0425                     struct milbeaut_hdmac_device *mdev,
0426                     int chan_id)
0427 {
0428     struct device *dev = &pdev->dev;
0429     struct milbeaut_hdmac_chan *mc = &mdev->channels[chan_id];
0430     char *irq_name;
0431     int irq, ret;
0432 
0433     irq = platform_get_irq(pdev, chan_id);
0434     if (irq < 0)
0435         return irq;
0436 
0437     irq_name = devm_kasprintf(dev, GFP_KERNEL, "milbeaut-hdmac-%d",
0438                   chan_id);
0439     if (!irq_name)
0440         return -ENOMEM;
0441 
0442     ret = devm_request_irq(dev, irq, milbeaut_hdmac_interrupt,
0443                    IRQF_SHARED, irq_name, mc);
0444     if (ret)
0445         return ret;
0446 
0447     mc->mdev = mdev;
0448     mc->reg_ch_base = mdev->reg_base + MLB_HDMAC_CH_STRIDE * (chan_id + 1);
0449     mc->vc.desc_free = milbeaut_hdmac_desc_free;
0450     vchan_init(&mc->vc, &mdev->ddev);
0451 
0452     return 0;
0453 }
0454 
0455 static int milbeaut_hdmac_probe(struct platform_device *pdev)
0456 {
0457     struct device *dev = &pdev->dev;
0458     struct milbeaut_hdmac_device *mdev;
0459     struct dma_device *ddev;
0460     int nr_chans, ret, i;
0461 
0462     nr_chans = platform_irq_count(pdev);
0463     if (nr_chans < 0)
0464         return nr_chans;
0465 
0466     ret = dma_set_mask(dev, DMA_BIT_MASK(32));
0467     if (ret)
0468         return ret;
0469 
0470     mdev = devm_kzalloc(dev, struct_size(mdev, channels, nr_chans),
0471                 GFP_KERNEL);
0472     if (!mdev)
0473         return -ENOMEM;
0474 
0475     mdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
0476     if (IS_ERR(mdev->reg_base))
0477         return PTR_ERR(mdev->reg_base);
0478 
0479     mdev->clk = devm_clk_get(dev, NULL);
0480     if (IS_ERR(mdev->clk)) {
0481         dev_err(dev, "failed to get clock\n");
0482         return PTR_ERR(mdev->clk);
0483     }
0484 
0485     ret = clk_prepare_enable(mdev->clk);
0486     if (ret)
0487         return ret;
0488 
0489     ddev = &mdev->ddev;
0490     ddev->dev = dev;
0491     dma_cap_set(DMA_SLAVE, ddev->cap_mask);
0492     dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
0493     ddev->src_addr_widths = MLB_HDMAC_BUSWIDTHS;
0494     ddev->dst_addr_widths = MLB_HDMAC_BUSWIDTHS;
0495     ddev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
0496     ddev->device_free_chan_resources = milbeaut_hdmac_free_chan_resources;
0497     ddev->device_config = milbeaut_hdmac_chan_config;
0498     ddev->device_pause = milbeaut_hdmac_chan_pause;
0499     ddev->device_resume = milbeaut_hdmac_chan_resume;
0500     ddev->device_prep_slave_sg = milbeaut_hdmac_prep_slave_sg;
0501     ddev->device_terminate_all = milbeaut_hdmac_terminate_all;
0502     ddev->device_synchronize = milbeaut_hdmac_synchronize;
0503     ddev->device_tx_status = milbeaut_hdmac_tx_status;
0504     ddev->device_issue_pending = milbeaut_hdmac_issue_pending;
0505     INIT_LIST_HEAD(&ddev->channels);
0506 
0507     for (i = 0; i < nr_chans; i++) {
0508         ret = milbeaut_hdmac_chan_init(pdev, mdev, i);
0509         if (ret)
0510             goto disable_clk;
0511     }
0512 
0513     ret = dma_async_device_register(ddev);
0514     if (ret)
0515         goto disable_clk;
0516 
0517     ret = of_dma_controller_register(dev->of_node,
0518                      milbeaut_hdmac_xlate, mdev);
0519     if (ret)
0520         goto unregister_dmac;
0521 
0522     platform_set_drvdata(pdev, mdev);
0523 
0524     return 0;
0525 
0526 unregister_dmac:
0527     dma_async_device_unregister(ddev);
0528 disable_clk:
0529     clk_disable_unprepare(mdev->clk);
0530 
0531     return ret;
0532 }
0533 
0534 static int milbeaut_hdmac_remove(struct platform_device *pdev)
0535 {
0536     struct milbeaut_hdmac_device *mdev = platform_get_drvdata(pdev);
0537     struct dma_chan *chan;
0538     int ret;
0539 
0540     /*
0541      * Before reaching here, almost all descriptors have been freed by the
0542      * ->device_free_chan_resources() hook. However, each channel might
0543      * be still holding one descriptor that was on-flight at that moment.
0544      * Terminate it to make sure this hardware is no longer running. Then,
0545      * free the channel resources once again to avoid memory leak.
0546      */
0547     list_for_each_entry(chan, &mdev->ddev.channels, device_node) {
0548         ret = dmaengine_terminate_sync(chan);
0549         if (ret)
0550             return ret;
0551         milbeaut_hdmac_free_chan_resources(chan);
0552     }
0553 
0554     of_dma_controller_free(pdev->dev.of_node);
0555     dma_async_device_unregister(&mdev->ddev);
0556     clk_disable_unprepare(mdev->clk);
0557 
0558     return 0;
0559 }
0560 
0561 static const struct of_device_id milbeaut_hdmac_match[] = {
0562     { .compatible = "socionext,milbeaut-m10v-hdmac" },
0563     { /* sentinel */ }
0564 };
0565 MODULE_DEVICE_TABLE(of, milbeaut_hdmac_match);
0566 
0567 static struct platform_driver milbeaut_hdmac_driver = {
0568     .probe = milbeaut_hdmac_probe,
0569     .remove = milbeaut_hdmac_remove,
0570     .driver = {
0571         .name = "milbeaut-m10v-hdmac",
0572         .of_match_table = milbeaut_hdmac_match,
0573     },
0574 };
0575 module_platform_driver(milbeaut_hdmac_driver);
0576 
0577 MODULE_DESCRIPTION("Milbeaut HDMAC DmaEngine driver");
0578 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!