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OSCL-LXR

 
 

    


0001 # SPDX-License-Identifier: GPL-2.0-only
0002 
0003 config MTK_HSDMA
0004         tristate "MediaTek High-Speed DMA controller support"
0005         depends on ARCH_MEDIATEK || COMPILE_TEST
0006         select DMA_ENGINE
0007         select DMA_VIRTUAL_CHANNELS
0008         help
0009           Enable support for High-Speed DMA controller on MediaTek
0010           SoCs.
0011 
0012           This controller provides the channels which is dedicated to
0013           memory-to-memory transfer to offload from CPU through ring-
0014           based descriptor management.
0015 
0016 config MTK_CQDMA
0017         tristate "MediaTek Command-Queue DMA controller support"
0018         depends on ARCH_MEDIATEK || COMPILE_TEST
0019         select DMA_ENGINE
0020         select DMA_VIRTUAL_CHANNELS
0021         select ASYNC_TX_ENABLE_CHANNEL_SWITCH
0022         help
0023           Enable support for Command-Queue DMA controller on MediaTek
0024           SoCs.
0025 
0026           This controller provides the channels which is dedicated to
0027           memory-to-memory transfer to offload from CPU.
0028 
0029 config MTK_UART_APDMA
0030         tristate "MediaTek SoCs APDMA support for UART"
0031         depends on OF && SERIAL_8250_MT6577
0032         select DMA_ENGINE
0033         select DMA_VIRTUAL_CHANNELS
0034         help
0035           Support for the UART DMA engine found on MediaTek MTK SoCs.
0036           When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
0037           you can enable the config. The DMA engine can only be used
0038           with MediaTek SoCs.