drivers/dma/mcf-edma.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
0004 // Copyright (c) 2017 Sysam, Angelo Dureghello  <angelo@sysam.it>
0005
0006 #include <linux/module.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/dmaengine.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/platform_data/dma-mcf-edma.h>
0011
0012 #include "fsl-edma-common.h"
0013
0014 #define EDMA_CHANNELS       64
0015 #define EDMA_MASK_CH(x)     ((x) & GENMASK(5, 0))
0016
0017 static irqreturn_t mcf_edma_tx_handler(int irq, void *dev_id)
0018 {
0019     struct fsl_edma_engine *mcf_edma = dev_id;
0020     struct edma_regs *regs = &mcf_edma->regs;
0021     unsigned int ch;
0022     struct fsl_edma_chan *mcf_chan;
0023     u64 intmap;
0024
0025     intmap = ioread32(regs->inth);
0026     intmap <<= 32;
0027     intmap |= ioread32(regs->intl);
0028     if (!intmap)
0029         return IRQ_NONE;
0030
0031     for (ch = 0; ch < mcf_edma->n_chans; ch++) {
0032         if (intmap & BIT(ch)) {
0033             iowrite8(EDMA_MASK_CH(ch), regs->cint);
0034
0035             mcf_chan = &mcf_edma->chans[ch];
0036
0037             spin_lock(&mcf_chan->vchan.lock);
0038
0039             if (!mcf_chan->edesc) {
0040                 /* terminate_all called before */
0041                 spin_unlock(&mcf_chan->vchan.lock);
0042                 continue;
0043             }
0044
0045             if (!mcf_chan->edesc->iscyclic) {
0046                 list_del(&mcf_chan->edesc->vdesc.node);
0047                 vchan_cookie_complete(&mcf_chan->edesc->vdesc);
0048                 mcf_chan->edesc = NULL;
0049                 mcf_chan->status = DMA_COMPLETE;
0050                 mcf_chan->idle = true;
0051             } else {
0052                 vchan_cyclic_callback(&mcf_chan->edesc->vdesc);
0053             }
0054
0055             if (!mcf_chan->edesc)
0056                 fsl_edma_xfer_desc(mcf_chan);
0057
0058             spin_unlock(&mcf_chan->vchan.lock);
0059         }
0060     }
0061
0062     return IRQ_HANDLED;
0063 }
0064
0065 static irqreturn_t mcf_edma_err_handler(int irq, void *dev_id)
0066 {
0067     struct fsl_edma_engine *mcf_edma = dev_id;
0068     struct edma_regs *regs = &mcf_edma->regs;
0069     unsigned int err, ch;
0070
0071     err = ioread32(regs->errl);
0072     if (!err)
0073         return IRQ_NONE;
0074
0075     for (ch = 0; ch < (EDMA_CHANNELS / 2); ch++) {
0076         if (err & BIT(ch)) {
0077             fsl_edma_disable_request(&mcf_edma->chans[ch]);
0078             iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
0079             mcf_edma->chans[ch].status = DMA_ERROR;
0080             mcf_edma->chans[ch].idle = true;
0081         }
0082     }
0083
0084     err = ioread32(regs->errh);
0085     if (!err)
0086         return IRQ_NONE;
0087
0088     for (ch = (EDMA_CHANNELS / 2); ch < EDMA_CHANNELS; ch++) {
0089         if (err & (BIT(ch - (EDMA_CHANNELS / 2)))) {
0090             fsl_edma_disable_request(&mcf_edma->chans[ch]);
0091             iowrite8(EDMA_CERR_CERR(ch), regs->cerr);
0092             mcf_edma->chans[ch].status = DMA_ERROR;
0093             mcf_edma->chans[ch].idle = true;
0094         }
0095     }
0096
0097     return IRQ_HANDLED;
0098 }
0099
0100 static int mcf_edma_irq_init(struct platform_device *pdev,
0101                 struct fsl_edma_engine *mcf_edma)
0102 {
0103     int ret = 0, i;
0104     struct resource *res;
0105
0106     res = platform_get_resource_byname(pdev,
0107                 IORESOURCE_IRQ, "edma-tx-00-15");
0108     if (!res)
0109         return -1;
0110
0111     for (ret = 0, i = res->start; i <= res->end; ++i)
0112         ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
0113     if (ret)
0114         return ret;
0115
0116     res = platform_get_resource_byname(pdev,
0117             IORESOURCE_IRQ, "edma-tx-16-55");
0118     if (!res)
0119         return -1;
0120
0121     for (ret = 0, i = res->start; i <= res->end; ++i)
0122         ret |= request_irq(i, mcf_edma_tx_handler, 0, "eDMA", mcf_edma);
0123     if (ret)
0124         return ret;
0125
0126     ret = platform_get_irq_byname(pdev, "edma-tx-56-63");
0127     if (ret != -ENXIO) {
0128         ret = request_irq(ret, mcf_edma_tx_handler,
0129                   0, "eDMA", mcf_edma);
0130         if (ret)
0131             return ret;
0132     }
0133
0134     ret = platform_get_irq_byname(pdev, "edma-err");
0135     if (ret != -ENXIO) {
0136         ret = request_irq(ret, mcf_edma_err_handler,
0137                   0, "eDMA", mcf_edma);
0138         if (ret)
0139             return ret;
0140     }
0141
0142     return 0;
0143 }
0144
0145 static void mcf_edma_irq_free(struct platform_device *pdev,
0146                 struct fsl_edma_engine *mcf_edma)
0147 {
0148     int irq;
0149     struct resource *res;
0150
0151     res = platform_get_resource_byname(pdev,
0152             IORESOURCE_IRQ, "edma-tx-00-15");
0153     if (res) {
0154         for (irq = res->start; irq <= res->end; irq++)
0155             free_irq(irq, mcf_edma);
0156     }
0157
0158     res = platform_get_resource_byname(pdev,
0159             IORESOURCE_IRQ, "edma-tx-16-55");
0160     if (res) {
0161         for (irq = res->start; irq <= res->end; irq++)
0162             free_irq(irq, mcf_edma);
0163     }
0164
0165     irq = platform_get_irq_byname(pdev, "edma-tx-56-63");
0166     if (irq != -ENXIO)
0167         free_irq(irq, mcf_edma);
0168
0169     irq = platform_get_irq_byname(pdev, "edma-err");
0170     if (irq != -ENXIO)
0171         free_irq(irq, mcf_edma);
0172 }
0173
0174 static struct fsl_edma_drvdata mcf_data = {
0175     .version = v2,
0176     .setup_irq = mcf_edma_irq_init,
0177 };
0178
0179 static int mcf_edma_probe(struct platform_device *pdev)
0180 {
0181     struct mcf_edma_platform_data *pdata;
0182     struct fsl_edma_engine *mcf_edma;
0183     struct fsl_edma_chan *mcf_chan;
0184     struct edma_regs *regs;
0185     struct resource *res;
0186     int ret, i, len, chans;
0187
0188     pdata = dev_get_platdata(&pdev->dev);
0189     if (!pdata) {
0190         dev_err(&pdev->dev, "no platform data supplied\n");
0191         return -EINVAL;
0192     }
0193
0194     chans = pdata->dma_channels;
0195     len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
0196     mcf_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
0197     if (!mcf_edma)
0198         return -ENOMEM;
0199
0200     mcf_edma->n_chans = chans;
0201
0202     /* Set up drvdata for ColdFire edma */
0203     mcf_edma->drvdata = &mcf_data;
0204     mcf_edma->big_endian = 1;
0205
0206     if (!mcf_edma->n_chans) {
0207         dev_info(&pdev->dev, "setting default channel number to 64");
0208         mcf_edma->n_chans = 64;
0209     }
0210
0211     mutex_init(&mcf_edma->fsl_edma_mutex);
0212
0213     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0214
0215     mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
0216     if (IS_ERR(mcf_edma->membase))
0217         return PTR_ERR(mcf_edma->membase);
0218
0219     fsl_edma_setup_regs(mcf_edma);
0220     regs = &mcf_edma->regs;
0221
0222     INIT_LIST_HEAD(&mcf_edma->dma_dev.channels);
0223     for (i = 0; i < mcf_edma->n_chans; i++) {
0224         struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
0225
0226         mcf_chan->edma = mcf_edma;
0227         mcf_chan->slave_id = i;
0228         mcf_chan->idle = true;
0229         mcf_chan->dma_dir = DMA_NONE;
0230         mcf_chan->vchan.desc_free = fsl_edma_free_desc;
0231         vchan_init(&mcf_chan->vchan, &mcf_edma->dma_dev);
0232         iowrite32(0x0, &regs->tcd[i].csr);
0233     }
0234
0235     iowrite32(~0, regs->inth);
0236     iowrite32(~0, regs->intl);
0237
0238     ret = mcf_edma->drvdata->setup_irq(pdev, mcf_edma);
0239     if (ret)
0240         return ret;
0241
0242     dma_cap_set(DMA_PRIVATE, mcf_edma->dma_dev.cap_mask);
0243     dma_cap_set(DMA_SLAVE, mcf_edma->dma_dev.cap_mask);
0244     dma_cap_set(DMA_CYCLIC, mcf_edma->dma_dev.cap_mask);
0245
0246     mcf_edma->dma_dev.dev = &pdev->dev;
0247     mcf_edma->dma_dev.device_alloc_chan_resources =
0248             fsl_edma_alloc_chan_resources;
0249     mcf_edma->dma_dev.device_free_chan_resources =
0250             fsl_edma_free_chan_resources;
0251     mcf_edma->dma_dev.device_config = fsl_edma_slave_config;
0252     mcf_edma->dma_dev.device_prep_dma_cyclic =
0253             fsl_edma_prep_dma_cyclic;
0254     mcf_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
0255     mcf_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
0256     mcf_edma->dma_dev.device_pause = fsl_edma_pause;
0257     mcf_edma->dma_dev.device_resume = fsl_edma_resume;
0258     mcf_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
0259     mcf_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
0260
0261     mcf_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
0262     mcf_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
0263     mcf_edma->dma_dev.directions =
0264             BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
0265
0266     mcf_edma->dma_dev.filter.fn = mcf_edma_filter_fn;
0267     mcf_edma->dma_dev.filter.map = pdata->slave_map;
0268     mcf_edma->dma_dev.filter.mapcnt = pdata->slavecnt;
0269
0270     platform_set_drvdata(pdev, mcf_edma);
0271
0272     ret = dma_async_device_register(&mcf_edma->dma_dev);
0273     if (ret) {
0274         dev_err(&pdev->dev,
0275             "Can't register Freescale eDMA engine. (%d)\n", ret);
0276         return ret;
0277     }
0278
0279     /* Enable round robin arbitration */
0280     iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
0281
0282     return 0;
0283 }
0284
0285 static int mcf_edma_remove(struct platform_device *pdev)
0286 {
0287     struct fsl_edma_engine *mcf_edma = platform_get_drvdata(pdev);
0288
0289     mcf_edma_irq_free(pdev, mcf_edma);
0290     fsl_edma_cleanup_vchan(&mcf_edma->dma_dev);
0291     dma_async_device_unregister(&mcf_edma->dma_dev);
0292
0293     return 0;
0294 }
0295
0296 static struct platform_driver mcf_edma_driver = {
0297     .driver     = {
0298         .name   = "mcf-edma",
0299     },
0300     .probe      = mcf_edma_probe,
0301     .remove     = mcf_edma_remove,
0302 };
0303
0304 bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
0305 {
0306     if (chan->device->dev->driver == &mcf_edma_driver.driver) {
0307         struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
0308
0309         return (mcf_chan->slave_id == (uintptr_t)param);
0310     }
0311
0312     return false;
0313 }
0314 EXPORT_SYMBOL(mcf_edma_filter_fn);
0315
0316 static int __init mcf_edma_init(void)
0317 {
0318     return platform_driver_register(&mcf_edma_driver);
0319 }
0320 subsys_initcall(mcf_edma_init);
0321
0322 static void __exit mcf_edma_exit(void)
0323 {
0324     platform_driver_unregister(&mcf_edma_driver);
0325 }
0326 module_exit(mcf_edma_exit);
0327
0328 MODULE_ALIAS("platform:mcf-edma");
0329 MODULE_DESCRIPTION("Freescale eDMA engine driver, ColdFire family");
0330 MODULE_LICENSE("GPL v2");